[coreboot] Assigning PCI resources clobbers console with io-mapped / memory-mapped UART

We ran into an issue where we were not getting a full coreboot log on Denverton with the Harcuvar CRB, where it just abruptly stops the serial console output during the assignment of the PCI resources. Root Device assign_resources, bus 0 link: 0 DOMAIN: assign_resources, bus 0 link: 0

Re: [coreboot] shrdw question

On Thu, Mar 29, 2018 at 3:16 PM Nico Huber wrote: > On 29.03.2018 23:58, ron minnich wrote: > > believe it or not that code runs on coreboot simulator, hardware, and > qemu, > > What is `coreboot simulator`? > > > the 8086 one in yabel. So here's what I think is going on. you're

Re: [coreboot] shrdw question

On 29.03.2018 23:58, ron minnich wrote: > believe it or not that code runs on coreboot simulator, hardware, and qemu, What is `coreboot simulator`? > and gets a different answer on each. Same binary and same processor (e.g. 32-bit protected) mode? Without knowing what your assembler translated

Re: [coreboot] shrdw question

believe it or not that code runs on coreboot simulator, hardware, and qemu, and gets a different answer on each. On Thu, Mar 29, 2018 at 12:54 PM Nico Huber wrote: > On 29.03.2018 20:25, ron minnich wrote: > > I have the following code: > > > > movl $0x12345678, %eax > > movl

Re: [coreboot] shrdw question

On 29/03/2018 21:25, ron minnich wrote: > I have the following code: > > movl $0x12345678, %eax > movl $0x, %ebx > movb $0x10, %cl > shrdw %ebx, %eax > > quiz: what's the value of %ax after this instruction? Given 'w', correct notation for the last instruction should be shrdw %bx, %ax ?

Re: [coreboot] shrdw question

On 29.03.2018 20:25, ron minnich wrote: > I have the following code: > > movl $0x12345678, %eax > movl $0x, %ebx > movb $0x10, %cl > shrdw %ebx, %eax If I had to assemble it, I would have refuse it... *w with 32-bit registers? how should that work? Though, after reading a little about

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

On 02/18/2018 07:03 AM, Rudolf Marek wrote: > Hi, Thanks for the detailed reply :] > What do you want to protect? I just looked at the AMD page saw they said they would be releasing updates and I figured I should have them even though there is no description of as to what they actually will do. >

[coreboot] shrdw question

I have the following code: movl $0x12345678, %eax movl $0x, %ebx movb $0x10, %cl shrdw %ebx, %eax quiz: what's the value of %ax after this instruction? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Missing ACPI ASL code for Denverton GPIO controller

Hi Sumo, It was more to get some motivation to clean some of the code. The branch is here: https://review.coreboot.org/c/coreboot/+/25446 I’ve really not looked on GPIO on ACPI (cause I don’t need it) but I really think it should be a better