Re: [coreboot] Out of MTRRs

On Sat, Mar 31, 2018 at 10:21 AM, Nico Huber wrote: > On 31.03.2018 17:31, Nico Huber wrote: >> >> On 23.03.2018 16:29, Jay Talbott wrote: >>> >>> Do you think they will resolve the issue that I am seeing? >> >> >> I don't know. As you top posted, I haven't looked at it yet. I'll

Re: [coreboot] Assigning PCI resources clobbers console with io-mapped / memory-mapped UART

On Thu, Mar 29, 2018 at 3:36 PM, Jay Talbott wrote: > We ran into an issue where we were not getting a full coreboot log on > Denverton with the Harcuvar CRB, where it just abruptly stops the serial > console output during the assignment of the PCI resources. > >

Re: [coreboot] SATA init on FSP 2.0 for Skylake

I met the same problem. I use the FSP1.1 and the 0:17h:0 disappears after raminit. It seems that the FSP disable the SATA. The SATA device can be disabled if SCFD is set. But it can not re-enable. SATA Controller Function Disable (SCFD): BIOS program this bit to 1 to disable the SATA Controller