you can take a look at all my configs as as well as all the patches in my
tree in my github there. They aren't all fully up to date, but should be
useful. Check Caroline, Cave, Chell, Sentry for Skylake CrOS devices,
which should all be the same ACPI-wise as kblrvp3. I haven't pushed the
config
That unfortunately did not help. Would it be possible to take a look at your
.config? Perhaps I'll be able to spot something
From: Matt DeVillier
Sent: Wednesday, April 25, 2018 4:14 PM
To: alexfein...@hotmail.com
Cc: coreboot
Subject:
On Thu, Apr 26, 2018 at 1:59 AM, Alex Feinman wrote:
> I've built a Coreboot image (from the HEAD) for my custom Kaby Lake board.
> The build uses Chrome EC and is based on kblrvp3 mainboard configuration.
> Linux runs fine, but when I attempt to install Windows 10 (or
I have Windows booting on a KBL CrOS device, and looking at my tree, pretty
sure the only change I have that would potentially address that error is
adding the pcon value to the IGD ACPI OpRegion header:
https://github.com/MattDevo/coreboot/commit/3349065354709c85276168272469797dd3f6
there
I've built a Coreboot image (from the HEAD) for my custom Kaby Lake board. The
build uses Chrome EC and is based on kblrvp3 mainboard configuration. Linux
runs fine, but when I attempt to install Windows 10 (or boot a preinstalled
Windows image from USB) I instantly get ACPI_BIOS_ERROR
Hello Rudolf,
First thank your for finding these blobs and the hack to use them, and for
testing and validating them.
But please could you tell us what was the setup for your tests :
- what was your hardware : cpu + mobo (chipset)?
- what was your linux kernel version?
Thank you beforehand.
April 18, 2018 3:54 PM, "Kyösti Mälkki" wrote:
> Having romstage stack smashed seems irrelevant for the no-boot issue.
> That nehalem raminit code, struct raminfo, seems to eat a lot of stack
> and an error message for that case was added with commit 2c3fd49. You
> could
If I understood all this correctly, the updated microcodes should be
forcing the CPU to do these MSR writes (or the low level action which
stands behind them) by default. So that, when you got this updated
microcode on your CPU, its already fixed and no further operations are
necessary!
At the
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