On 08/11/2018 03:44 AM, Matt DeVillier wrote:
> or outputting the boot console to a non-existent serial port (which can slow
> everything down).
Yeah ditto, and it could also be a high log level or other debug
features enabled that you don't need like the EHCI debug
console...probably a
Hey,
I also have that panel in my X200 and it's working fine here. Don't
remember if it worked with stock BIOS, but the latest libreboot release
(20160907) is working fine. I will also try latest coreboot in the next
weeks, and will report back if I experience strange behaviour.
For now it works
Hi,
Thanks for your feedback.
We enabled ENABLE_FSP_FAST_BOOT and MRC cache Training data in FSP using binary
configuration tool. Also we reduced the console log level to 0.
Now the boot time is reduced to 23 secs for initial boot and 11 secs for
upcoming power cycles.
Is this a normal
Hi,
Thanks for your feedback.
We enabled ENABLE_FSP_FAST_BOOT and MRC cache Training data in FSP using binary
configuration tool. Also we reduced the console log level to 0.
Now the boot time is reduced to 23 secs for initial boot and 11 secs for
upcoming power cycles.
Is this a normal
assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run
the cbmem utility and see how long each stage/section of coreboot is taking
(up to the point of handing off control to the payload). 30s to boot
sounds like either you're not caching the RAM training data (MRC cache) and
Hi,
We have developed a coreboot image for Apollo lake custom board. The time taken
for boot up is around 30 seconds.
We would like to reduce the boot time as much as possible.
Following codes are removed:
1. Non-intel Apollolake specific codes in below folders
* Arch
* Soc
Hi,
I just wanted to share my experience of using alternative screens for ThinkPad
X200 (HV121WX4-120) with coreboot.
After fitting the screen, it became apparent that something is wrong.
Having turned on the X200, it ran happily for about 1 minute, then the screen
just powered off. It didn't
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