[coreboot] Burn 2MB coreboot.rom on 8MB flash chip

Hello, I have an Intel's ATOM Bay Trail board. The output of "inteltool" is: CPU: ID 0x30679, Processor Type 0x0, Family 0x6, Model 0x37, Stepping 0x9 Northbridge: 8086:0f00 (Bay Trail) Southbridge: 8086:0f1c (Bay Trail) IGD: 8086:0f31 (unknown) In coreboot configuration I selected: Mainboard

[coreboot] (no subject)

Hello, I have an Intel's ATOM Bay Trail board. The output of "inteltool" is: CPU: ID 0x30679, Processor Type 0x0, Family 0x6, Model 0x37, Stepping 0x9 Northbridge: 8086:0f00 (Bay Trail) Southbridge: 8086:0f1c (Bay Trail) IGD: 8086:0f31 (unknown) In coreboot configuration I selected: Mainboard

Re: [coreboot] Loading Linux payloads on RISC-V

On Sun, Sep 23, 2018 at 9:00 AM ron minnich wrote: > > ah sorry I forgot. > > I think selfboot could be reworked (and should be) to interpret "0" as > "somewhere useful"? Why is the kernel being loaded at 0? > > On Sat, Sep 22, 2018 at 10:47 PM ron minnich wrote: >> >> shouldn't we fix the

Re: [coreboot] Kabylake unable to boot with post code 0x71 "SGX: pre-conditions not met"

Hi Alex, I will keep in mind this but before I will check about the EC on my system because this is not an RVP board. Thank you for your advise, I'll do that. Jose Trujillo. ‐‐‐ Original Message ‐‐‐ On Monday, September 24, 2018 4:46 PM, Alex Feinman wrote: > Keep in mind that Intel

Re: [coreboot] Kabylake unable to boot with post code 0x71 "SGX: pre-conditions not met"

Keep in mind that Intel RVP boards ship with Intel EC code, which is not compatible with Coreboot. You need to reflash it with Google EC - it's built as a part of Coreboot, or it can be built separately as well. From: coreboot on behalf of Nico Huber Sent:

[coreboot] Wired problems with Intel skylake based board

Hi all I have an almost working coreboot/u-boot boot solution based on kabylake FSP. Most of the time the system works as expected but from time to rebooting the system fails completely. On my board, which is powered by an COM Express module (i3-6100U), there are two FPGAs connected via PCIe to

Re: [coreboot] Tianocore and TPM

Hi Ben, Changing gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid do the trick! Now when I boot my system I can see the PCRs 0 to 9 populated. I have some questions regarding the values I see in the PCRs (different versions of coreboot+tianocore populate the PCRs0-7 with the same values)

Re: [coreboot] compile coreboot for xeon 5570

Hello Zahra, On 9/24/18 2:51 PM, zahra rahimkhani wrote: > I am trying to use coreboot for a motherboard that have cpu of Xeon x5570. TLDR; it won't work. coreboot needs to be adapted to every mainboard, and, in this case, even to the processor and chipset. Without docu- mentation from Intel