Hi!
Thank you for the report.
If you're still on it, can you try the latest update? There was
seemingly incorrect reset sequence after setting the HT disable bit. I'm
not sure if it was the reason of problems, but would be good to test again.
On 6/16/20 12:31 PM, Lars Hochstetter wrote:
Am Mi., 17. Juni 2020 um 02:47 Uhr schrieb Julius Werner <
jwer...@chromium.org>:
> Patrick, any further concerns from your side? If not, would you mind
> creating a new repository for this? I can write the patches to move
> blobs and adjust the Makefiles afterwards.
>
I will create a repo for
Hi Jay,
Regarding the APIC ID problem, besides updating devicetree.cb with the
correct value do you think something else is required?
I have created a patch to make the APIC ID of devicetree.cb "dynamic" for
Denverton SoC, so it can be updated during runtime, see below:
diff --git
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