[coreboot] Re: Change wcaps value through cim_verb_data[]

Paul wrote… What board is this and what chipset? It is a custom laptop platform where we have been tasked to replace the stock AMI BIOS with coreboot. It uses Intel Comet Lake. Sorry, I do not know the exact answer, but looking at the quirk implementation in Linux 5.10-rc5, it consists

[coreboot] Re: Change wcaps value through cim_verb_data[]

Dear Andy, Am 27.11.20 um 12:47 schrieb Andy Pont: With the stock BIOS in the board I am working on one of the nodes for the ALC256 CODEC is: What board is this and what chipset? Node 0x21 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out   Control: name="Headphone Playback Switch", index=0,

[coreboot] Change wcaps value through cim_verb_data[]

Hello, With the stock BIOS in the board I am working on one of the nodes for the ALC256 CODEC is: Node 0x21 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out Control: name="Headphone Playback Switch", index=0, device=0 ControlAmp: chs=3, dir=Out, idx=0, ofs=0 Amp-Out caps: ofs=0x00,

[coreboot] Re: Accessing extended capabilities PCI registers?

Hi, On 25. 11. 20 20:26, Rafael Send wrote: > Any ideas for what I could try here, or reasons why it might not (be expected > to) work? The extended PCI configuration space access requires a special memory region (up 256MiB) which translate accesses to the PCI configuration cycles. It is

[coreboot] Re: Splashscreens

Matt wrote… exactly this. On most devices, the payload will execute ~600ms after coreboot starts, and the image probably wouldn't start being displayed until halfway thru that. So it would be up for ~300ms and likely just appear as a flicker. Not to mention needing a different sized/formatted