[coreboot] Re: [SPECIFICATION RFC] The firmware and bootloader log specification

[Tom Rini]

On Fri, Dec 04, 2020 at 02:23:23PM +0100, Paul Menzel wrote:
> Dear Wim, dear Daniel,
> 
> 
> First, thank you for including all parties in the discussion.
> Am 04.12.20 um 13:52 schrieb Wim Vervoorn:
> 
> > I agree with you. Using an existing standard is better than inventing
> > a new one in this case. I think using the coreboot logging is a good
> > idea as there is indeed a lot of support already available and it is
> > lightweight and simple.
> In my opinion coreboot’s format is lacking, that it does not record the
> timestamp, and the log level is not stored as metadata, but (in coreboot)
> only used to decide if to print the message or not.
> 
> I agree with you, that an existing standard should be used, and in my
> opinion it’s Linux message format. That is most widely supported, and
> existing tools could then also work with pre-Linux messages.
> 
> Sean Hudson from Mentor Graphics presented that idea at Embedded Linux
> Conference Europe 2016 [1]. No idea, if anything came out of that effort.
> (Unfortunately, I couldn’t find an email. Does somebody have contacts at
> Mentor to find out, how to reach him?)

I believe the main thing that came out of this was the reminder that
there was an even older attempt by U-Boot to have such a mechanism, and
that at the time getting the work accepted in Linux faced some hurdles
or another.

That said, I too agree with taking what's already a de facto standard,
the coreboot logging, and expand on it as needed.

-- 
Tom


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[coreboot] Re: Master currently broken on Thinkpad X230 when using option table

[Julius Werner]

Sorry for the breakage and thanks for narrowing down the issue. I
think Arthur had also just figured out the same problem and uploaded a
quick fix here: https://review.coreboot.org/48407

On Sun, Dec 6, 2020 at 11:09 PM Iru Cai  wrote:
>
> By using gdb, I can debug on QEMU. I can see in bootblock, romstage and 
> postcar,
> when USE_OPTION_TABLE is set, the debug_level option is always read, so there
> is a cbfs_map_ro() in each stage. The buggy thing is in postcar stage, the 
> cbfs mcache
> cannot be found, so its size becomes zero, then all the files in the cbfs 
> cannot be loaded
> because of the mcache overflow, which results in failing to load the ramstage.
>
> On Mon, Dec 7, 2020 at 12:18 PM Iru Cai  wrote:
>>
>> Confirmed on qemu-i440fx. It's strange that it already has different
>> behavior in romstage between setting and not setting
>> USE_OPTION_TABLE. I still don't know what is broken in this commit.
>>
>> On Sun, Dec 06, 2020 at 11:24:11PM +0100, Merlin Büge wrote:
>> >
>> > 9d0cc2aea9 cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
>> > https://review.coreboot.org/c/coreboot/+/39306
>> >
>
>
>
> --
> My website: https://vimacs.lcpu.club
>
> Please do not send me Microsoft Office/Apple iWork documents. Send 
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[coreboot] Re: Apollo Lake cannot load coreboot

[Wolfgang Kamp - datakamp]

Hi Anatolii,

The boot process of Apollo Lake is well described in the PDF “Apollolake 
implementation” from Andrey Petrov Intel.
In the XML file for the Fit Tool I have SMP Signing Key and OEM Key Manifest 
Binary for testing empty. The OEM Public Key Hash is all zero. The Boot Guard 
Profile 0 is Legacy.
Do you use the Winbond W25Q128FWPIQ SPI FLASH? Did you connect IO0 – IO3 to the 
CPU for Quad SPI?

Kind regards
Wolfgang

Von: Anatolii Vorobev [mailto:anatolii.voro...@wayray.com]
Gesendet: Freitag, 4. Dezember 2020 12:54
An: Wolfgang Kamp - datakamp 
Cc: coreboot@coreboot.org
Betreff: [coreboot] Re: Apollo Lake cannot load coreboot

Hi Wolfgang,
We have TI650944 PMIC and LPDDR4 memory down configuration. SPI flash chip JDEC 
ID do present in IFD VSCC table. SPI boot strap is selected, TXE ROM Bypass is 
disabled.
I program flash device with Dediprog programmer.
Yes, I can see __FMAP__ signature in the dumped binary at 0x30 offset.

I have a question. Is it TXE that copies bootblock and romstage into RAM(cache)?

I also wonder what differences can be between UP2 and my board? May be I should 
preprogram something into FPF (signing keys maybe) before loading coreboot? Can 
it be related to Boot Guard?

Best Regards,
Anatolii Vorobev
Lead Developer, Firmware | WayRay
anatolii.voro...@wayray.com | 
http://wayray.com
+7 915 423-87-68 (RU)

From: Wolfgang Kamp - datakamp mailto:wmk...@datakamp.de>>
Sent: Thursday, December 3, 2020 11:40 AM
To: Anatolii Vorobev 
mailto:anatolii.voro...@wayray.com>>
Cc: coreboot@coreboot.org
Subject: AW: [coreboot] Re: Apollo Lake cannot load coreboot

Hi Anatolii,

If you search the web for “apollolake implementation – coreboot”, you will find 
interesting information about the Apollo Lake boot process. The IFD will be 
processed from the internal microcontroller which looks for the correct Flash 
device and the PMIC. The PMIC must be the TI chip TPS65094x in the case of 
using the UP Squared board BIOS components. To boot from SPI the SOC_COM1_TXD 
(eMMC boot) signal must be pulled low and the SOC_COM1_RTS_N (SPI boot) signal 
must be pulled high.
How do you program the on board FLASH device?
If you dump the binary contents you can see –FMAP-- signature at 0x30?

Kind regards,
Wolfgang

Von: Anatolii Vorobev [mailto:anatolii.voro...@wayray.com]
Gesendet: Mittwoch, 2. Dezember 2020 13:44
An: Wolfgang Kamp - datakamp mailto:wmk...@datakamp.de>>
Cc: coreboot@coreboot.org
Betreff: RE: [coreboot] Re: Apollo Lake cannot load coreboot

Hi Wolfgang,
If I read memory at address 0xFF00 -0xFFFE  after SPI is initialized by 
bootblock_soc_early_init() then I will get only 0xFF bytes. So there is no 
mapped SPI image there – it is empty. But I should see at least IFD at 0xFF00 
-0xFF00 1000, am I right?

The mainboard I’m debugging is not UP Squared, the schematics are just a bit 
resembling (as far as I see, because UP2 design files are disclosed). That’s 
why there are some hardware differences that lead to problems above. Is it GPIO 
settings or bootstraps? What would you suggest me to check first?

Best Regards,
Anatolii Vorobev

From: Wolfgang Kamp - datakamp mailto:wmk...@datakamp.de>>
Sent: Tuesday, December 1, 2020 5:33 PM
To: Anatolii Vorobev 
mailto:anatolii.voro...@wayray.com>>
Cc: ger...@coreboot.org
Subject: AW: [coreboot] Re: Apollo Lake cannot load coreboot

Hi Anatolii,

In this early stage there is no RAM initialized. The SPI Flash is memory mapped 
starting at 0xFF00  if the FLASH size is 16M, which is on UP Squared 
default.  On address 0xFF30  (0x30 relative to FLASH start address) 
starts FMAP. You will find the header –FMAP—on this position. With an in 
circuit programmer like DEDIPROG 100 you can check this on UP Squared board.

Kind regards,
Wolfgan


Von: Anatolii Vorobev [mailto:anatolii.voro...@wayray.com]
Gesendet: Dienstag, 1. Dezember 2020 12:44
An: Maxim Polyakov 
mailto:max.senia.pol...@gmail.com>>
Cc: coreboot@coreboot.org
Betreff: [coreboot] Re: Apollo Lake cannot load coreboot

Hi, Maxim. Sure, I’ve attached .config file.
Here is cbfstool output:

./build/cbfstool build/coreboot.rom print
FMAP REGION: COREBOOT
Name   Offset Type   Size   Comp
cbfs master header 0x0cbfs header32 none
fallback/romstage  0x80   stage   48164 none
cpu_microcode_blob.bin 0xbd00 microcode   48128 none
fallback/ramstage  0x17980stage  106068 none
vgaroms/seavgabios.bin 0x31840raw 28160 none
config 0x386c0raw   283 none
revision   0x38840raw   681 none
fallback/dsdt.aml  0x38b40raw  6338 none
fspm.bin   0x3a480fsp  

[coreboot] Re: Master currently broken on Thinkpad X230 when using option table

[Tom Englund]

im hitting the same issue on my x230, however i do have a ft232h and
fetched some logs of booting with the bad commit, http://ix.io/2GJ0 , are
some CBFS ERROR: CBFS mcache overflow! , at the bottom of it.
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