[coreboot] Re: search_isolinux usb

[Iru Cai]

Hi Geert,

On 2022/8/8 03:51, Geert Stappers wrote:

Hello coreboot developers,

An .iso is fetched from Internet and `dd` to USB-memory-stick.
The USB-thumbdrive is then inserted in the X230, on the left side,
in the USB-slot closest to user[1].
I use my tool liveusb-builder (https://github.com/mytbk/liveusb-builder) 
to make your multiboot USB stick, which supports several common types of 
GNU/Linux iso images. It can generate a grub.cfg file that works with 
GRUB payload.

___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Master currently broken on Thinkpad X230 when using option table

[Iru Cai]

By using gdb, I can debug on QEMU. I can see in bootblock, romstage and
postcar,
when USE_OPTION_TABLE is set, the debug_level option is always read, so
there
is a cbfs_map_ro() in each stage. The buggy thing is in postcar stage, the
cbfs mcache
cannot be found, so its size becomes zero, then all the files in the cbfs
cannot be loaded
because of the mcache overflow, which results in failing to load the
ramstage.

On Mon, Dec 7, 2020 at 12:18 PM Iru Cai  wrote:

> Confirmed on qemu-i440fx. It's strange that it already has different
> behavior in romstage between setting and not setting
> USE_OPTION_TABLE. I still don't know what is broken in this commit.
>
> On Sun, Dec 06, 2020 at 11:24:11PM +0100, Merlin Büge wrote:
> >
> > 9d0cc2aea9 cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
> > https://review.coreboot.org/c/coreboot/+/39306
> >
>


-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Master currently broken on Thinkpad X230 when using option table

[Iru Cai]

Confirmed on qemu-i440fx. It's strange that it already has different
behavior in romstage between setting and not setting
USE_OPTION_TABLE. I still don't know what is broken in this commit.

On Sun, Dec 06, 2020 at 11:24:11PM +0100, Merlin Büge wrote:
> 
> 9d0cc2aea9 cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
> https://review.coreboot.org/c/coreboot/+/39306
> 
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: T440p Audio Out

[Iru Cai]

Hi,
On Sat, May 23, 2020 at 12:50:52PM -, acaleech...@gmail.com wrote:
> 
> When docked the mic is enabled by default but headphone is not detected. 
> Strangely if i plug another headphone in the laptop headphone jack, the dock 
> headphones start working!
> 
> Could it be that the file 
> https://github.com/coreboot/coreboot/blob/master/src/mainboard/lenovo/t440p/hda_verb.c
>  is missing the info about the jack being a combo port just like in the t520 
> https://github.com/rockchip-linux/coreboot/blob/master/src/mainboard/lenovo/t520/hda_verb.c

I think it makes sense. I don't have a T440p right now. I can only
give you some information I found when I worked on this machine.

I once searched in the OEM firmware, and found the HDA verbs are
stored in a UEFI module named PchConfigDxe. I don't know how many of
these the Lenovo firmware uses. I've pasted the list of HDA verbs in
this module dumped with Ghidra in [1]. I've tried to add the function
reset verbs (the four 0x0017ff00) to coreboot before, but it doesn't
seem to help.

Also I found other coreboot laptops using Realtek HDA have some verbs
used to tune jack detection, with hex like 0x02xx. There are also
some of these in this verb list. I don't know if it can help.

[1] https://paste.debian.net/1148430/

Regards,
Iru
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Laptop EC questions

[Iru Cai]

Have you turned off HP Sure Start in the BIOS setting when running the
OEM firmware (in "Security->BIOS Integrity Checking")? There's a PEI
and bootblock volume in the EC chip, which Sure Start may use to
recover the BIOS.

> The only thing I can think of would be the Embedded Controller.
> Unfortunately there isnt a lot of documentation on how the EC could cause
> these problems nor are there any hints towards how to potentially integrate
> them into the build. I have found that the EC is an MEC1322 which is a part
> of the chrome-ec project and was wondering if there may be an easy way to
> do this integration to further test.

___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Laptop EC questions

[Iru Cai]

Hi Lomár,

I'm currently trying to port coreboot to HP EliteBook 820 G1, which
uses the same EC chip MEC1322 and may have the same kind of EC
firmware.

On Mon, Apr 06, 2020 at 07:12:24PM -0400, Lomár Berry wrote:
> I have been looking at trying to port coreboot to my HP zBook 15 G2.
> Everything is seemingly fine, I can get an image built as this machine is
> similar to the Lenovo t440p. Unfortunately I have yet to have a successful
> startup. There are a few differences in the machine which include having a

What can you see when you try to start up your machine?

> 
> The only thing I can think of would be the Embedded Controller.
> Unfortunately there isnt a lot of documentation on how the EC could cause
> these problems nor are there any hints towards how to potentially integrate
> them into the build. I have found that the EC is an MEC1322 which is a part
> of the chrome-ec project and was wondering if there may be an easy way to
> do this integration to further test.

EC is really a problem. HP uses a different kind of EC firmware, so we
can't use the chrome-ec support code, unless we port chrome-ec to
these laptops (I have thought of doing this, but it's another hard
problem.). We don't need to extract the EC to put into the coreboot
build process if the EC is located in another chip (as is the case in
EliteBook 820 G1/G2). What we need to do is to find out how the BIOS
code initialize the EC so that the machine can be brought up.

Regards,
Iru
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Debug MRC.BIN, how to make ramstage CBMEM persistant across reboot ?

[Iru Cai]

Hi Baylee4,

On Fri, Apr 03, 2020 at 01:10:52AM -, None via coreboot wrote:
> Hi,
> 
> There is no serial port on the T440p, and the USB 2.0 debug port is not 
> exposed, so it seems that using CBMEM is the only option.
> 

There is an EHCI debug port on the right side. You just need to enable
the USB debug config option.

https://doc.coreboot.org/mainboard/lenovo/t440p.html#working


Regards,
Iru
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: HP Elitebook 8540w

[Iru Cai]

On Mon, Sep 23, 2019 at 6:07 AM Dane Medic  wrote:

> Hi,
>
> is anyone working on porting HP Elitebook 8540w?
> Reading on wikipedia , it has
> different (older) chipset than those elitebooks already ported,
>

Yes, it's older than the Sandy/Ivy Bridge Elitebooks that is already
ported. The code for northbridge
and southbridge will be different.


> so this might add more work I'm guessing.
>
> Have a nice day everyone!
> ___
> coreboot mailing list -- coreboot@coreboot.org
> To unsubscribe send an email to coreboot-le...@coreboot.org
>


-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: t420s USB 3.0 port

[Iru Cai]

Hi Jason,

On Fri, Mar 1, 2019 at 10:33 AM Jason Andryuk  wrote:

> Hi,
>
> I have a Lenovo Thinkpad t420s on which I've installed coreboot.
> However, the USB 3.0 port is not active and the controller is not
> listed under lspci.
>
> Under the original Lenovo bios, the xhci device was at pci address
> 0d:00.0 behind bridge 00:1c.4.
>
> It looks like the t420s devicetree.cb is set up for the xhci
> controller to be behind 00:1c.6.  I changed that to 00:1c.4 and that
> got the xhci pci device to show up as 03:00.0.  Strangely, booting
> into linux, it shows 001c.3 as the bridge to 03:00.0.  Additionally,
> plugged in USB devices were not detected.
>

Note that the mainboard has pcie_port_coalesce set in the devicetree, so it
can be wrong to just see the BDF address to know which port the XHCI device
is connected to.

However, lspci also shows the port, it'll show `PCI Express Root Port X`
where X is actually the port number (PCI function number + 1). The function
number in the device tree is based on this port number.


> Here's where it gets weird.  I had a mouse plugged in, and I was
> looking in sysfs.
> cat /sys/devices/pci\:00/\:00\:1c.3/\:03\:00.0/enable
> 0
> So the xhci pci device is disabled.  I ran `lspci -vvnn` a few times
> in quick sucession - I was looking to see if it showed disabled - and
> the mouse lit up!
>
> Plugging in a USB Flash drive, it was again not detected.  The lspci
> trigger worked.  Later, promptly switching USB devices resulted in the
> new USB device still being detected.
>
> Is "PCH: PCIe map 1c.4 -> 1c.3" the remapping from the device tree
> 1c.4 to the 1c.3 that I see?
>
> Below I've included the cbmem -c output and a snippet from an old
> lenovo BIOS dmesg w/ the pci address.
>
> Does anyone have an idea of what is going on, or what I should
> investigate next?  A total guess, but could poking the PCI device with
> lspci turn it on so that it may detect an attached device and then
> stay active?  Maybe something with power management?  Again, I'm just
> guessing.  Any suggestions are appreciated.
>
> Thanks,
> Jason
>
>
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

[coreboot] Re: Status on Dell OptiPlex 7010 support

[Iru Cai]

在 2018/12/25 上午3:05, Kumonie Williams 写道:
> Hello there, I have a question regarding coreboot.
>
> I was wondering if work was still being done to port coreboot to the
> Dell OptiPlex 7010. I was looking at commit
> 882d3c3574cc24f1bcf16b71c5090cc71ef725a6, but it seems the board
> didn’t boot at that stage in time. I have also not found much
> information regarding 4f19f4a7ebe7783830343d5ffc917142266fabf9 either,
> so I was wondering if work was still being
The upstream coreboot repository doesn't have these two commits. What
source tree are you using?
OptiPlex 7010 is still on gerrit
https://review.coreboot.org/c/coreboot/+/25095.

> done to port coreboot to the OptiPlex 7010, given its stock firmware
> doesn’t really work that great (I'd be happy to elaborate), even at
> revision A29, so I wanted to replace it with coreboot.
>
> Thanks.
>
___
coreboot mailing list -- coreboot@coreboot.org
To unsubscribe send an email to coreboot-le...@coreboot.org

Re: [coreboot] coreboot on ASRock H81M-HDS cannot load a payload

[Iru Cai]

I'm thinking of using a Linux payload before, but I failed to use an 8MB
flash (W25Q64FVAIG) on ASRock H81M-HDS with all flash space used.
I can only use the first 4MB with the original IFD, and the board doesn't
boot after I change the IFD to use the whole 8MB flash.

On Mon, Dec 17, 2018 at 12:31 PM ron minnich  wrote:

> I don't know, but as a test, I'd be very interested to see what
> happens with a linux payload. You probably don't have time for such a
> thing but I had to ask :-)
>
> On Sun, Dec 16, 2018 at 8:15 PM Iru Cai  wrote:
> >
> > Hi,
> >
> > I'm trying to run coreboot on ASRock H81M-HDS with a Xeon E3 and 8G*2
> RAM. I chose to use my GRUB payload, but coreboot cannot load it with the
> following error (full log in attachment):
> >
> > CBFS: 'Master Header Locator' located CBFS at [1a:40)
> > CBFS: Locating 'fallback/payload'
> > CBFS: Found @ offset 2fb80 size 1929bd
> > Checking segment from ROM address 0xffdcfbb8
> > Payload being loaded at below 1MiB without region being marked as RAM
> usable.
> > Checking segment from ROM address 0xffdcfbd4
> > SELF segment doesn't target RAM: 0x0010, 5203948 bytes
> >  0. -0fff: CONFIGURATION TABLES
> >  1. 7f751000-7f78efff: CONFIGURATION TABLES
> >  2. 7f78f000-7f7ccfff: RAMSTAGE
> >  3. 7f7cd000-7f7f: CONFIGURATION TABLES
> > Payload not loaded.
> >
> > If I use SeaBIOS as payload, SeaBIOS can run, but it can't allocate
> resources for SATA, EHCI and XHCI and can't find any boot devices.
> >
> > What is the problem in it?
> >
> > Iru
> >
> > --
> > My website: https://vimacs.lcpu.club
> >
> > Please do not send me Microsoft Office/Apple iWork documents. Send
> OpenDocument instead! http://fsf.org/campaigns/opendocument/
> > --
> > coreboot mailing list: coreboot@coreboot.org
> > https://mail.coreboot.org/mailman/listinfo/coreboot
>


-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] coreboot on ASRock H81M-HDS cannot load a payload

[Iru Cai]

Thanks, it now works.
A patch is submitted: https://review.coreboot.org/c/coreboot/+/30266

On Mon, Dec 17, 2018 at 12:39 PM Marshall Dawson <
marshalldawson...@gmail.com> wrote:

> I believe the Xeon hostbridge wasn't properly ID'ed.  Try adding 0x0c08 to
> the mc_pci_device_ids list near the bottom of
> northbridge/intel/haswell/northbridge.c.
>
>
> On Sun, Dec 16, 2018 at 9:32 PM ron minnich  wrote:
>
>> I don't know, but as a test, I'd be very interested to see what
>> happens with a linux payload. You probably don't have time for such a
>> thing but I had to ask :-)
>>
>> On Sun, Dec 16, 2018 at 8:15 PM Iru Cai  wrote:
>> >
>> > Hi,
>> >
>> > I'm trying to run coreboot on ASRock H81M-HDS with a Xeon E3 and 8G*2
>> RAM. I chose to use my GRUB payload, but coreboot cannot load it with the
>> following error (full log in attachment):
>> >
>> > CBFS: 'Master Header Locator' located CBFS at [1a:40)
>> > CBFS: Locating 'fallback/payload'
>> > CBFS: Found @ offset 2fb80 size 1929bd
>> > Checking segment from ROM address 0xffdcfbb8
>> > Payload being loaded at below 1MiB without region being marked as RAM
>> usable.
>> > Checking segment from ROM address 0xffdcfbd4
>> > SELF segment doesn't target RAM: 0x0010, 5203948 bytes
>> >  0. -0fff: CONFIGURATION TABLES
>> >  1. 7f751000-7f78efff: CONFIGURATION TABLES
>> >  2. 7f78f000-7f7ccfff: RAMSTAGE
>> >  3. 7f7cd000-7f7f: CONFIGURATION TABLES
>> > Payload not loaded.
>> >
>> > If I use SeaBIOS as payload, SeaBIOS can run, but it can't allocate
>> resources for SATA, EHCI and XHCI and can't find any boot devices.
>> >
>> > What is the problem in it?
>> >
>> > Iru
>> >
>> > --
>> > My website: https://vimacs.lcpu.club
>> >
>> > Please do not send me Microsoft Office/Apple iWork documents. Send
>> OpenDocument instead! http://fsf.org/campaigns/opendocument/
>> > --
>> > coreboot mailing list: coreboot@coreboot.org
>> > https://mail.coreboot.org/mailman/listinfo/coreboot
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://mail.coreboot.org/mailman/listinfo/coreboot
>>
>

-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] coreboot on ASRock H81M-HDS cannot load a payload

[Iru Cai]

Hi,

I'm trying to run coreboot on ASRock H81M-HDS with a Xeon E3 and 8G*2 RAM.
I chose to use my GRUB payload, but coreboot cannot load it with the
following error (full log in attachment):

CBFS: 'Master Header Locator' located CBFS at [1a:40)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 2fb80 size 1929bd
Checking segment from ROM address 0xffdcfbb8
Payload being loaded at below 1MiB without region being marked as RAM
usable.
Checking segment from ROM address 0xffdcfbd4
SELF segment doesn't target RAM: 0x0010, 5203948 bytes
 0. -0fff: CONFIGURATION TABLES
 1. 7f751000-7f78efff: CONFIGURATION TABLES
 2. 7f78f000-7f7ccfff: RAMSTAGE
 3. 7f7cd000-7f7f: CONFIGURATION TABLES
Payload not loaded.

If I use SeaBIOS as payload, SeaBIOS can run, but it can't allocate
resources for SATA, EHCI and XHCI and can't find any boot devices.

What is the problem in it?

Iru

-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
coreboot-4.8-2526-gad8478f643-dirty Sun Dec 16 16:50:38 UTC 2018 romstage starting...
Disabling Watchdog reboot... done.
SMBus controller enabled.
Setting up static northbridge registers... done.
Initializing Graphics...
Back from haswell_early_initialization()
CPU id(306c3) ucode:0024 Intel(R) Xeon(R) CPU E3-1271 v3 @ 3.60GHz
AES supported, TXT supported, VT supported
PCH type: H81, device id: 8c5c, rev id 5
Starting UEFI PEI System Agent
FMAP: Found "FLASH" version 1.1 at 18.
FMAP: base = ffc0 size = 40 #areas = 4
FMAP: area RW_MRC_CACHE found @ 19 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
FMAP: area COREBOOT found @ 1a (2490368 bytes)
CBFS: Locating 'mrc.bin'
CBFS: Found @ offset 1fffc0 size 2e6e4
System Agent: Starting up...
System Agent: Initializing PCH
install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USB)
System Agent: Initializing PCH (SA Init)
System Agent: Initializing PCH (Me UMA)
System Agent: Initializing Memory
System Agent: Done.
Sanity checking heap.
System Agent Version 1.6.1 Build 2
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00620020):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 8192 MB width x8 or x32 dual rank, selected
   DIMMB 0 MB width x8 or x32 single rank
memcfg channel[1] config (00620020):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 8192 MB width x8 or x32 dual rank, selected
   DIMMB 0 MB width x8 or x32 single rank
ME: FW Partition Table  : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode  : NO
ME: Boot Options Present: NO
ME: Update In Progress  : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code  : No Error
ME: Progress Phase  : uKernel Phase
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State: Unknown phase: 0x02 sate: 0x00
CBMEM:
IMD: root @ 7f7ff000 254 entries.
IMD: root @ 7f7fec00 62 entries.
External stage cache:
IMD: root @ 7fbff000 254 entries.
IMD: root @ 7fbfec00 62 entries.
MTRR Range: Start=ffc0 End=0 (Size 40)
MTRR Range: Start=0 End=100 (Size 100)
MTRR Range: Start=7f00 End=8000 (Size 100)
CBFS: 'Master Header Locator' located CBFS at [1a:40)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset 28900 size 4364
Decompressing stage fallback/postcar @ 0x7f7cdfc0 (33808 bytes)
Loading module at 7f7ce000 with entry 7f7ce000. filesize: 0x4110 memsize: 0x83d0
Processing 126 relocs. Offset value of 0x7d7ce000


coreboot-4.8-2526-gad8478f643-dirty Sun Dec 16 16:50:38 UTC 2018 postcar starting...
CBFS: 'Master Header Locator' located CBFS at [1a:40)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 14100 size 13e4a
Decompressing stage fallback/ramstage @ 0x7f78efc0 (252344 bytes)
Loading module at 7f78f000 with entry 7f78f000. filesize: 0x29d70 memsize: 0x3d978
Processing 2823 relocs. Offset value of 0x7e98f000


coreboot-4.8-2526-gad8478f643-dirty Sun Dec 16 16:50:38 UTC 2018 ramstage starting...
Normal boot.
BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
Enumerating buses...
CPU_CLUSTER: 0 enabled
DOMAIN:  enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0c08] enabled
PCI: Static device PCI: 00:01.0 not found, disabling it.
PCI: Static device PCI: 00:02.0 not found, disabling it.
PCI: Static device PCI: 00:03.0 not found, disabling it.
PCI: 00:14.0 [8086/8c31] enabled
PCI: 00:16.0 [8086/8c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 

Re: [coreboot] Matrix instead (or additionally to) IRC

[Iru Cai]

Previously it works, but now #coreboot needs registered nicks.

On Mon, Oct 29, 2018 at 3:43 AM Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:

> Not sure if that is still working but
> https://matrix.org/blog/2015/06/22/the-matrix-org-irc-bridge-now-bridges-all-of-freenode/
> should help connect to IRC via matrix.
>
> Choose your own protocol ;-)
>
> Am So., 28. Okt. 2018, 15:11 hat Philipp Stanner 
> geschrieben:
>
>> Hey,
>>
>> have you guys already heard of Matrix?
>> https://matrix.org/blog/home/
>>
>> It's some sort of modern IRC, using JSON to format messages. It's more
>> modern than IRC. Features are:
>>  * Source code formatting and highlighting in messages
>>  * multiple devices
>>  * history + history synchronization between multiple devices
>>  * possible E2C encryption
>>
>> and many more.
>> In theory it will be a decentralized protocol, but there aren't that
>> many servers yet and actually only one working server-software
>>
>> Many projects, especially tech-based ones like the Rust programming
>> language already use the service.
>>
>> Personally I think it's an enormous progress to IRC. I would give it a
>> chance if I were you :)
>>
>> P.
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://mail.coreboot.org/mailman/listinfo/coreboot
>>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>


-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] T520 vs. T530

[Iru Cai]

The iGPU T520 and dGPU T420 have stability problems when running coreboot. (
https://ticket.coreboot.org/issues/121)
So get a T530/W530/W520/dGPU T520.

I don't know the eGPU status of notebooks running coreboot.

On Tue, Oct 23, 2018 at 3:01 PM  wrote:

> Hello guys,
>
> I am planning to buy a used Lenovo Thinkpad and install coreboot on it. I
> am completely new to coreboot and I need help in the decision if I should
> buy a T520 or a T530. I read the wiki and some other pages but it's still
> hard for me to decide which model I should buy.
>
> 1. I need CPU power. I read that it is possible to put a i7-3940XM in a
> T530. Because of coreboot it should also possible to put it in a T520?
>
> 2. I would like to use an eGPU. Any differences between these two models?
>
> 3. With which model it is easier to install coreboot on it?
>
> 4. What are the general pros and cons of a T520/T530, especially with
> coreboot?
>
> Thanks for your help!
> Kind regards--
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot



-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] lower memory performance with coreboot on KGPE-D16

[Iru Cai]

Hi Daniel,

Thanks for your reply, but it's not the case with me.

I'm not using DDR3L-RDIMMs. My dmidecode output of one DIMM is:

Handle 0x0007, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0006
Error Information Handle: Not Provided
Total Width: 72 bits
Data Width: 64 bits
Size: 16384 MB
Form Factor: DIMM
Set: None
Locator: NODE 0 DIMM_A2
Bank Locator: Not Specified
Type: DDR3
Type Detail: Synchronous Registered (Buffered)
Speed: 800 MT/s
Manufacturer: Samsung
Serial Number: 7FCC9C13
Asset Tag: Not Specified
Part Number: M393B2G70BH0-CK0
Rank: 2
Configured Memory Speed: 800 MT/s
Minimum Voltage: 1.5 V
Maximum Voltage: 1.5 V
Configured Voltage: 1.5 V

Iru

On Sat, Oct 6, 2018 at 3:58 AM Daniel Kulesz 
wrote:

> Hi Iru,
>
> > I just found the memory performance on KGPE-D16 is lower when running
> with
> > coreboot. I have two Opteron 6276 and 8 16GB DDR3-1600 RDIMM on all
> orange
> > slots. I tested it with `hdparm -tT /dev/sda` and see the `Timing cached
> > reads` result. With coreboot, this value is around 3000 MB/s, but with
> OEM
> > firmware it can go to around 3600 MB/s. I think the disk cached read
> speed
> > is related to memory performance.
>
> Are you using DDR3L-RDIMMs? And did you check whether your memory really
> runs at 800 MHz? My experience is that coreboot sets the clock down to 667
> MHz when running on 1.35V (low voltage), while the vendor bios seems to run
> modules at 800 MHz in low voltage mode,  resulting in higher performance.
> According to Timothy, this is  "over the spec" and thus not set in coreboot
> by default (you can choose between 1.5V 800 MHz or 1.35V at 667 MHz - but
> may depend on the used modules).
>
> You can check e.g. in dmidecode. Below is an example (serial number x'd
> out):
>
> Handle 0x000E, DMI type 17, 40 bytes
> Memory Device
> Array Handle: 0x0006
> Error Information Handle: Not Provided
> Total Width: 72 bits
> Data Width: 64 bits
> Size: 8192 MB
> Form Factor: DIMM
> Set: None
> Locator: NODE 0 DIMM_D2
> Bank Locator: Not Specified
> Type: DDR3
> Type Detail: Synchronous Registered (Buffered)
> Speed: 800 MHz
> Manufacturer: Samsung
> Serial Number: x
> Asset Tag: Not Specified
> Part Number: M393B1K70DH0-YK0
> Rank: 2
> Configured Clock Speed: 800 MHz
> Minimum Voltage: 1.35 V
> Maximum Voltage: 1.5 V
> Configured Voltage: 1.5 V
>
> Btw.: I am getting around 3700 MB/sec with hdparm -Tt on my /dev/sda
> (mechanical disk) and around 3840 MB/sec on /dev/nvme0n1 (PCIe M.2 SSD).
>
> Cheers, Daniel
>


-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] lower memory performance with coreboot on KGPE-D16

[Iru Cai]

Hi,

I just found the memory performance on KGPE-D16 is lower when running with
coreboot. I have two Opteron 6276 and 8 16GB DDR3-1600 RDIMM on all orange
slots. I tested it with `hdparm -tT /dev/sda` and see the `Timing cached
reads` result. With coreboot, this value is around 3000 MB/s, but with OEM
firmware it can go to around 3600 MB/s. I think the disk cached read speed
is related to memory performance.

Iru

-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Fwd: Thinkpad W520 external monitor over Nvdia GPU

[Iru Cai]

The coreboot port of Lenovo W520 is in the upstream code now, are you using
the upstream code?

On Sat, Sep 29, 2018 at 10:36 PM Kinky Nekoboi 
wrote:

> Hello !
>
> Thank to charlotteplusplus`s reddit post i have succesfully running
> coreboot with a skrinked ME image on my W520. Everything works fine
> exacpt the fact that the nvidia GPU is not reconnicest by any linux
> distro. (not shown in lspci)
>
> is here anyuser with an W520 and got coreboot running with the nvidia
> GPU enabled?
>
> Maybe somebody can send me their rom or help somehow.
>
> Greetings
>
> the kinky nekoboi
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>


-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Build fails on Thinkpad W520

[Iru Cai]

commit 9fe248fb removes the use of addr and reg variable in this function,
that's why this code doesn't compile with CONFIG_DEBUG_RAM_SETUP.
I've submitted a fix for this:
https://review.coreboot.org/#/c/coreboot/+/28117/
or remove the printram statement?

On Thu, Aug 16, 2018 at 4:27 PM, Andreas Restle 
wrote:

> Hi Nico,
>
> thanks for the quick reply. If it’s on, it must have been by accident.
> I’ll check later today and report back.
>
> Building with the same .config worked fine two weeks ago though. But your
> last sentence probably is an explanation for that.
>
> Viele Grüße
>
> Andreas Restle
>
>
> --
> <°)))><
> Andreas Restle
> andreas.res...@gmail.com
>
> On 16. Aug 2018, at 10:10, Nico Huber  wrote:
>
> Hi Andreas,
>
> On 16.08.2018 08:25, Andreas Restle wrote:
>
> Building coreboot for Thinkpad W520 currently fails with the following
>
> error:
>
>
>CC romstage/northbridge/intel/sandybridge/raminit_common.o
>
> In file included from src/northbridge/intel/sandybridge/raminit_common.c:
> 18:
>
> src/northbridge/intel/sandybridge/raminit_common.c: In function
>
> 'dram_odt_stretch':
>
> src/northbridge/intel/sandybridge/raminit_common.c:211:49: error: 'reg'
>
> undeclared (first use in this function); did you mean 'prog'?
>
>   printram("OTHP Workaround [%x] = %x\n", addr, reg);
>
>
> it seems you have CONFIG_DEBUG_RAM_SETUP enabled. This is really only
> for debugging and nothing for end users / production builds. Debugging
> code is often broken (even when it does compile).
>
> Nico
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>



-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] asrock-B75-pro3-m

[Iru Cai]

Just ignore the CPU socket thing, it stands for a type of CPU which may not
be using the socket.
--ifd of flashrom means reading the IFD to get the layout, but
coreboot.rom's fake IFD doesn't have the BIOS region, are you sure you're
doing it correctly?
If the firmware is executed, you can use the serial port (as I can
remember, B75 Pro3-M's serial port is a 9-pin pinout on board) to see the
console output.

On Mon, Apr 16, 2018 at 12:52 PM, CarlosGonzalez 
wrote:

> HI coreboot
> I have an 'Asrock B75-Pro3-m socket 1155', But coreboot motherboard
> support page  show that 'Asrock B75-Pro3-m socket 989' is compatible but
> this do not exist,only socket 1155. can you check this?
> I am trying many time install coreboot on my motherboard , But not
> success, I compiled  coreboot with minimun configuration like ,Motherboard
> Name/Model, Chipset size 8 mb, only  this then i flashed with:  sudo
> flashrom -p ch341a_spi --ifd -i bios -w coreboot.rom , but in this way my
> computer not boot onle fans get turn on but i do not see any verbose on the
> screen.
> I really want coreboot on my system...Any help is much appreciate
> Once Thanks...
> /carlosgonz
>



-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] HP Elitebook 8770w Suspend-to-RAM

[Iru Cai]

Hi, Rob

SeaBIOS 1.11.0 has some bug which can make S3 resume failed [1], you can
try to use SeaBIOS 1.10.3:

Payload
Add a payload (SeaBIOS)  --->
SeaBIOS version (git revision)  --->
(rel-1.10.3) Insert a commit's SHA-1 or a branch name

[1] https://mail.coreboot.org/pipermail/seabios/2017-December/011962.html

Iru

On Thu, Jan 11, 2018 at 8:57 PM, Robert Reeves  wrote:

> Hi,
>
> I'm working on porting coreboot to the elitebook 8770w, with the goal
> of submitting what I've come up with once I get it working the way it
> should. Hardware wise it's very similar to the EB 8470p which I based
> the port off of. Almost everything works right now, except for suspend
> to RAM (and grub, but I'll figure that out later). It goes into
> suspend fine, but on resume it simply restarts. I've never done this
> before and I don't really know what I'm doing. I've attached a log
> which includes serial output from both coreboot and debian over
> several power/suspend/resume cycles with every debug option I could
> think of turned on. I'm not sure what to look for, I see several error
> messages, but I'm having a hard time telling which ones are serious
> and which can be ignored. I would appreciate any help, and I would
> like to gain enough experience to be a regular contributor to this
> project.
>
> -Rob
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>



-- 
My website: https://vimacs.lcpu.club

Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFC] Successful build with GCC 7.2 and IASL 20170831 for coreboot 4.7

[Iru Cai]

Hi all,

I found that ACPICA released version 20170929 yesterday, and it's more
strict than previous versions. I can't even use it to build qemu-i440fx
because many dsdt files have methods that are not used, which will make
iasl warn about this.

Iru

On Tue, Oct 3, 2017 at 11:50 AM, Matt DeVillier 
wrote:

> hi Paul,
>
> I took a look at this, and the error appears to be the result of a change
> in IASL 20170531:
>
> "Improved the behavior of the iASL compiler and disassembler to detect
> improper use of external declarations"
>
> According to the ACPI 6.2 spec, "The External directive informs the ASL
> compiler that the object is declared external to this table.."  This reads
> to me that if an object is declared External in one table (eg, the DSDT),
> then its declaration must be in another table, not in the table in which
> contains the External reference.  As _SB.DPTF.TEVT is declared in the DSDT
> (in SoC .asl code), then the External declaration in the
> chromeec/acpi/ec.asl is invalid.
>
> To test this, I removed the External declaration in ec.asl, and the
> previously failing boards now build properly with iASL 20170831.  I also
> retested using the current iASL version (20161222), and the aforementioned
> boards still build correctly.
>
> If someone wants to corroborate my analysis, then I'm happy to submit a
> patch to correct the issue
>
> cheers,
> Matt
>
> On Mon, Oct 2, 2017 at 1:56 AM, Paul Menzel  sourceforge.net> wrote:
>
>> Dear coreboot folks,
>>
>>
>> Am Mittwoch, den 20.09.2017, 08:17 +0200 schrieb Paul Menzel:
>>
>> > I’d like to propose the following goal for the upcoming coreboot 4.7
>> > release.
>> >
>> > All boards have to build with GCC 7.2 [1] and IASL 20170831 [2].
>> >
>> > For the latter, several Intel boards fail to build [3]. It’d be great
>> > if the maintainers looked into it.
>>
>> Unfortunately, there was no reply yet. Patrick already blocked the
>> change-set, and commented that it’ll only go in after the coreboot 4.7
>> release, which is fine. But the boards should still build in my
>> opinion.
>>
>> The boards below are affected by the IASL update.
>>
>> ```
>> $ git grep TEVT
>> src/ec/google/chromeec/acpi/ec.asl:External (\_SB.DPTF.TEVT, MethodObj)
>> src/ec/google/chromeec/acpi/ec.asl: If (CondRefOf
>> (\_SB.DPTF.TEVT)) {
>> src/ec/google/chromeec/acpi/ec.asl:
>>  \_SB.DPTF.TEVT (Local0)
>> src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl:Method
>> (TEVT, 1, NotSerialized)
>> src/soc/intel/baytrail/acpi/dptf/thermal.asl:Method (TEVT, 1,
>> NotSerialized)
>> src/soc/intel/braswell/acpi/dptf/thermal.asl:Method (TEVT, 1,
>> NotSerialized)
>> src/soc/intel/common/acpi/dptf/thermal.asl:Method (TEVT, 1,
>> NotSerialized)
>> src/soc/intel/skylake/acpi/dptf/thermal.asl:Method (TEVT, 1,
>> NotSerialized)
>> ```
>>
>> What is the process for this? Are the maintainers of the board that
>> fail to build subscribed on this mailing list?
>>
>>
>> Kind regards,
>>
>> Paul
>>
>>
>> > [1] https://review.coreboot.org/20809/
>> > [2] https://review.coreboot.org/21156/
>> > [3] https://ticket.coreboot.org/issues/138
>>
>> --
>> coreboot mailing list: coreboot@coreboot.org
>> https://mail.coreboot.org/mailman/listinfo/coreboot
>>
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] KGPE-D16 PCI passthrough

[Iru Cai]

I seem to know what happened to me. Now I pass throught 00.12.{0,1,2} and
there's no problem now. But if I plug in my keyboard and mouse, then
because of the USB controller is passed to the VM, then I have no keyboard
or mouse to use, so the system seems to hang.

However, I still don't know why there exists some kernel oops in previous
tests.

On Fri, Sep 8, 2017 at 2:33 PM, taii...@gmx.com <taii...@gmx.com> wrote:

> On 09/08/2017 02:12 AM, Iru Cai wrote:
>
> On Fri, Sep 8, 2017 at 2:02 PM, taii...@gmx.com <taii...@gmx.com> wrote:
>>
>> On 09/08/2017 12:44 AM, Iru Cai wrote:
>>>
>>> On Fri, Sep 8, 2017 at 11:42 AM, taii...@gmx.com <taii...@gmx.com>
>>> wrote:
>>>
>>>> On 09/07/2017 11:21 PM, Iru Cai wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I have a problem about PCI passthrough on KGPE-D16. I plugged in a PCI
>>>>>> to
>>>>>> USB adapter to the PCI slot, and it's in IOMMU group 7 with the ASpeed
>>>>>> video card and the LSI 1394a controller. I try to pass them all to a
>>>>>> VM,
>>>>>> but then kernel crashes. I tried in Linux 4.9.47 and Linux 4.12.10.
>>>>>>
>>>>>> Does anyone with KGPE-D16 have this problem?
>>>>>>
>>>>>> Iru
>>>>>>
>>>>>> You are attempting to pass the primary video device to a VM which
>>>>>> hardly
>>>>>>
>>>>> ever works, I tried the same thing and it didn't work (I wanted my PCI
>>>>> sound card in the VM, and as PCI doesn't support ACS and all the PCI
>>>>> devices on the D16 are behind the same bridge they are in the same
>>>>> IOMMU
>>>>> group so I had to do that - I ended up buying a USB sound adapter)
>>>>>
>>>>> Now I'm using GTX 650 as my primary video device and not using the on
>>>>>
>>>> board
>>>> ASpeed  video card.
>>>>
>>>> Also I tried to pass the onboard USB controller to the VM, and also
>>>> crashed
>>>> the kernel.
>>>>
>>>> Damn :[
>>> FYI you forgot to reply all - please re post this to the list :]
>>>
>>> Hmm can I have dmesg logs and your libvirt or w/e VM config files? for
>>> the
>>> new config you are trying.
>>> I am playing games right now with my pass thru usb ports.
>>>
>>> So are you using vfio-pci or pci-stub? I don't know if I can use pci-stub
>> in libvirt, but vfio-pci will require all devices
>> in an IOMMU group passed to a VM, and I don't use a modded kernel.
>>
> VFIO-PCI
> I pass thru my video card, an onboard nic and an onboard usb controller
> (all three usb subdevices) - works great and they're all in their own iommu
> group.
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] KGPE-D16 PCI passthrough

[Iru Cai]

On Fri, Sep 8, 2017 at 2:02 PM, taii...@gmx.com <taii...@gmx.com> wrote:

> On 09/08/2017 12:44 AM, Iru Cai wrote:
>
> On Fri, Sep 8, 2017 at 11:42 AM, taii...@gmx.com <taii...@gmx.com> wrote:
>>
>> On 09/07/2017 11:21 PM, Iru Cai wrote:
>>>
>>> Hi,
>>>
>>>> I have a problem about PCI passthrough on KGPE-D16. I plugged in a PCI
>>>> to
>>>> USB adapter to the PCI slot, and it's in IOMMU group 7 with the ASpeed
>>>> video card and the LSI 1394a controller. I try to pass them all to a VM,
>>>> but then kernel crashes. I tried in Linux 4.9.47 and Linux 4.12.10.
>>>>
>>>> Does anyone with KGPE-D16 have this problem?
>>>>
>>>> Iru
>>>>
>>>> You are attempting to pass the primary video device to a VM which hardly
>>> ever works, I tried the same thing and it didn't work (I wanted my PCI
>>> sound card in the VM, and as PCI doesn't support ACS and all the PCI
>>> devices on the D16 are behind the same bridge they are in the same IOMMU
>>> group so I had to do that - I ended up buying a USB sound adapter)
>>>
>>> Now I'm using GTX 650 as my primary video device and not using the on
>> board
>> ASpeed  video card.
>>
>> Also I tried to pass the onboard USB controller to the VM, and also
>> crashed
>> the kernel.
>>
> Damn :[
> FYI you forgot to reply all - please re post this to the list :]
>
> Hmm can I have dmesg logs and your libvirt or w/e VM config files? for the
> new config you are trying.
> I am playing games right now with my pass thru usb ports.
>

So are you using vfio-pci or pci-stub? I don't know if I can use pci-stub
in libvirt, but vfio-pci will require all devices
in an IOMMU group passed to a VM, and I don't use a modded kernel.


-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] KGPE-D16 PCI passthrough

[Iru Cai]

Hi,

I have a problem about PCI passthrough on KGPE-D16. I plugged in a PCI to
USB adapter to the PCI slot, and it's in IOMMU group 7 with the ASpeed
video card and the LSI 1394a controller. I try to pass them all to a VM,
but then kernel crashes. I tried in Linux 4.9.47 and Linux 4.12.10.

Does anyone with KGPE-D16 have this problem?

Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890 Northbridge 
only dual slot (2x16) PCI-e GFX Hydra part (rev 02)
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD/ATI] RD890S/RD990 I/O Memory 
Management Unit (IOMMU)
00:02.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 
PCI to PCI bridge (PCI Express GFX port 0)
00:04.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 
PCI to PCI bridge (PCI Express GPP Port 0)
00:09.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 
PCI to PCI bridge (PCI Express GPP Port 4)
00:0a.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 
PCI to PCI bridge (PCI Express GPP Port 5)
00:0b.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD990 PCI to 
PCI bridge (PCI Express GFX2 port 0)
00:0c.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD990 PCI to 
PCI bridge (PCI Express GFX2 port 1)
00:0d.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] RD890/RD9x0/RX980 
PCI to PCI bridge (PCI Express GPP2 Port 0)
00:11.0 SATA controller: Advanced Micro Devices, Inc. [AMD/ATI] 
SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode]
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] 
SB7x0/SB8x0/SB9x0 USB OHCI0 Controller
00:12.1 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 
Controller
00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] 
SB7x0/SB8x0/SB9x0 USB EHCI Controller
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] 
SB7x0/SB8x0/SB9x0 USB OHCI0 Controller
00:13.1 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0 USB OHCI1 
Controller
00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] 
SB7x0/SB8x0/SB9x0 USB EHCI Controller
00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 SMBus Controller 
(rev 3d)
00:14.1 IDE interface: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 
IDE Controller
00:14.2 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 Azalia 
(Intel HDA)
00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD/ATI] SB7x0/SB8x0/SB9x0 
LPC host controller
00:14.4 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] SBx00 PCI to PCI 
Bridge
00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD/ATI] 
SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 0
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 1
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 2
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 3
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 4
00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 5
00:19.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 0
00:19.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 1
00:19.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 2
00:19.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 3
00:19.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 4
00:19.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 5
00:1a.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 0
00:1a.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 1
00:1a.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 2
00:1a.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 3
00:1a.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 4
00:1a.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 5
00:1b.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 0
00:1b.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 1
00:1b.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 2
00:1b.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 3
00:1b.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 4
00:1b.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 15h Processor 
Function 5
03:00.0 Ethernet controller: Intel Corporation 82574L 

[coreboot] What GPU are you using on KGPE-D16

[Iru Cai]

Hi,

I've just flashed the most recent coreboot with Linux payload on my
KGPE-D16. However, there're some problems with GPU.

I have an RX550, but it seems that amdgpu has bug with AMD-Vi which I found
in some mailing list (
https://lists.freedesktop.org/archives/amd-gfx/2017-March/006490.html), and
it still doesn't work after I use amd_iommu=fullflush, and using
amd_iommu=off will make the machine not able to find USB devices.

And I have a GTX750, but xf86-video-nouveau doesn't work on this Maxwell
card.

Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Boot from a M.2 NVMe ssd on an ASUS KGPE-D16

[Iru Cai]

On Mon, Sep 4, 2017 at 3:47 PM, BogDan Vatra  wrote:

> Hi,
>
> Is it possible to boot from a M.2 NVMe ssd on KGPE-D16?
> If not, how hard it will be to add such support, I'd like to give it a
> try myself.
>
>
I'm using Linux kernel payload with petitboot.
Now SeaBIOS also supports NVMe.

Yours,
> BogDan.
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] qemu to launch coreboot

[Iru Cai]

On Fri, Aug 04, 2017 at 04:17:29PM +, ron minnich wrote:
> Sorry, don't know what sh4 is ...
>

Some kind of architecture... (https://en.wikipedia.org/wiki/SuperH#SH-4)

> 
> 
> On Fri, Aug 4, 2017 at 9:09 AM ingegneriafore...@alice.it <
> ingegneriafore...@alice.it> wrote:
> 
> > Hello everybody,
> >
> >
> > I've used
> >
> > atp-get install qemu
> >
> > to install qemu on my Ubuntu 16.04 PC. Is it right ?
> >
> > Now i have several qemu file in /usr/bin.
> >
> > For coreboot i need to use qemu-sh4 ?
> >

You should use the right QEMU of the right architecture (for most of
beginners it's x86 or x86_64), and emulate the bare metal system. So
you need to use qemu-system-i386 or qemu-system-x86_64.

> > Is it right the command that i found on the coreboot wiki
> >
> > $ qemu -bios path/to/coreboot.rom -hda disk.img -nographic
> >
> > to launch coreboot on qemu-sh4 ?
> >
> >
> > Thanks very much.
> >
> > Regards.
> >
> > Vincenzo.
> >
> >
> > Forensic Consultant
> > Tribunale di Lecce
> >
> > Studio: Strada di Garibaldi - Contrada Paradisi
> > 73010 Lequile (LE)
> >
> > cell: 339.7968555 <(339)%20796-8555>
> > skype: vincenzo.di_salvo
> > --
> > coreboot mailing list: coreboot@coreboot.org
> > https://mail.coreboot.org/mailman/listinfo/coreboot

> -- 
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot



signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] question on libgfxinit DP port number

[Iru Cai]

Thanks, Nico


On 2017年07月18日 16:20, Nico Huber wrote:
> Hi Iru,
>
> On 18.07.2017 09:28, Iru Cai wrote:
>> Hi,
>>
>> I found the mainboard DP port doesn't have output before kernel starts in
>> hp/2570p (https://review.coreboot.org/c/20489/). After I added DP3 and
>> HDMI3 in port list, the DP port had output, and cbmem log said it's DP3.
>> However, xrandr says this port is DP2. What is the problem?
> libgfxinit only knows about physical ports (i.e. how they are ordered*
> in the datasheet). Linux ignores ports that aren't strapped to be active
> (or are disabled by VBT) and renumbers the ports to fill the holes.
>
> Nico
>
> * The numbering is not perfect. As historically VGA was the first port
>   (port A in datasheets), digital ports are counted from B, so DP1 is
>   port B, DP2 is port C, etc.

Now I found /sys/class/drm_dp_aux_dev/drm_dp_aux{0,1} (Linux 4.4) and
`cat /sys/class/drm_dp_aux_dev/*/name` gives me:
  DPDDC-B
  DPDDC-D

So should the ports be DP1 and DP3?

Iru

-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] question on libgfxinit DP port number

[Iru Cai]

Hi,

I found the mainboard DP port doesn't have output before kernel starts in
hp/2570p (https://review.coreboot.org/c/20489/). After I added DP3 and
HDMI3 in port list, the DP port had output, and cbmem log said it's DP3.
However, xrandr says this port is DP2. What is the problem?

I also checked lenovo/x230, but the port named DP2 in xrandr or
/sys/class/drm/card0-DP-2 is also shown as DP2 in cbmem log.

Thanks,
Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Wiki page for Lenovo Thinkpad W520

[Iru Cai]

Hi Charlotte,

On Tue, Jul 18, 2017 at 1:37 PM, Charlotte Plusplus <
pluspluscharlo...@gmail.com> wrote:

> Hello
>
> I would be very happy to help with pictures, source, binaries, info etc.
> But since Denver, I have been just a bit behind. Too many side projects :-)
>
> Anyway, I will get back in touch soon. If you use my previously released
> binary, you should be fine.
>
> The port to the current coreboot I did in Denver has new ram issues that I
> am investigating. It may need again some dirty workarounds, like adding +1
> or +2 to some SPD settings to get memtest work without any failure.
> Optimus is still not working yet.
>

Maybe you need to rebase your code on master coreboot, which has some
improvements on Sandy/Ivy Bridge RAM init. There's also some changes in the
codebase.

Iru


> Thanks
> Charlotte
>
>
> On Sun, Jul 16, 2017 at 8:49 AM, Nico Rikken  wrote:
>
>> I created a wiki page for the Lenovo W520 based on information shared
>> on this mailinglist:
>>
>> https://www.coreboot.org/Board:lenovo/w520
>>
>> I hope others can contribute more details, so I can benefit when taking
>> on the challenge of flashing a W520 myself.
>>
>> Kind regards,
>> Nico Rikken (NL)
>>
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] What do each of the letters B...? , L...? , O...? , B...? represent in the acronym BLOB ?

[Iru Cai]

https://en.wikipedia.org/wiki/Binary_blob

The term *blob * was
first used in database management systems
 to describe a
collection of binary data 
stored as a single entity.

On Wed, May 31, 2017 at 3:57 PM, Don Saklad  wrote:

> What do each of the letters B...? , L...? , O...? , B...? represent in
> the acronym BLOB ?
>
>
>   Paul Menzel  writes:
>   > [1:multipart/signed Hide]
>   > [1/1:text/plain Hide]
>   > Dear coreboot folks,
>   > I am looking for a new portable device available in Europe.
>   > Is it true, that the Acer Chromebook R 13 [1], is the only current BLOB
>   > free device? The device currently costs 400 €. Is MediaTek “a good
>   > citizen”, that means, do they provide datasheets and work on drivers?
>   > The Samsung Chromebook Plus/Pro with RK3399 [2] are only available in
>   > the USA, right?
>   > Thanks,
>   > Paul
>   > [1] https://www.acer.com/ac/en/US/content/series/acerchromebookr13
>   > [2] https://chromeunboxed.com/samsung-chromebook-pros-
> processor-rk3399-gets-benchmarked-and-it-is-fast/
>   > [1/2:application/pgp-signature Show Save:signature.asc (195B)]
>   > [2:text/plain Hide]
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot




-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] What's the relationship between ACPI and SMM?

[Iru Cai]

Hello,

I'm trying to write some ACPI code to support an EC. I don't know if I need
to write an smihandler.c for the boards.

I saw some mainboard code. Older boards such as lenovo/x200 have no
smihandler.c, but newer boards such as lenovo/x220 have. Also, I don't know
much about things like GPE, SCI, ..., even after I look at the ACPI
specification.

So can some one sort out what happens when there is a event (e.g. Lid
open/close), and what the EC and ACPI OS should do. What needs to be added
in the mainboard code?

Thanks,
Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] How come the community meeting is hosted by proprietary software?

[Iru Cai]

Have you tried the Matrix protocol (https://matrix.org) that I mentioned?
It supports WebRTC as well as talk with text and files.

If you are not satisfied with the existing public servers (
https://www.hello-matrix.net/public_servers.php), you can even host one.

On Fri, Mar 17, 2017 at 11:05 PM, Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:

> 2017-03-17 15:50 GMT+01:00 Juliana Rodrigues :
> > that I know uses jitsi: https://meet.jit.si
> > It's MIT, but works very well.
> Thanks for the pointer.
>
> We already tried jitsi, but I think without the bridge service (which
> only seems to exist for about a year).
> So, something to re-evaluate, but the last time we tried "works very
> well" was the opposite of our experience due to bandwidth
> requirements.
>
>
> Patrick
> (note to all so I don't have to sound like a grumpy, broken record: Is
> it FOSS and reasonably popular? Then it's rather likely that we
> already tried it)
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] How come the community meeting is hosted by proprietary software?

[Iru Cai]

I love Matrix (https://matrix.org) and there are already some public
servers (https://www.hello-matrix.net/public_servers.php), including
matrixim.cc hosted by me.

On Tue, Mar 14, 2017 at 12:36 PM, taii...@gmx.com  wrote:

> Discord is proprietary software, why don't we use something free and open
> source?
>
> I would be more than pleased to set up a SIP server or something to that
> effect (I have only 10mbps upload but I know folks who will give me a VPS
> if I want one).
> There are plenty of FOSS softphones for every OS and you can also use a
> desktop VoIP phone so it would be more convenient.
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Improving KBC1126 support for HP laptops

[Iru Cai]

On Fri, Feb 24, 2017 at 8:14 AM, Peter Stuge <pe...@stuge.se> wrote:

> Iru Cai wrote:
> > I have searched and downloaded two SMSC confidential document: a KBC1122
> > preliminary datasheet and a KBC1122 BIOS porting guide. Is there any
> > problem if I use them to write some code?
>
> Obviously they are copyrighted works, so you can't contribute any
> code which you may have copied from them.
>
>
I see. I just found out that some initialization code from these documents
is just some PNP device init code from pnp_device.c,
and some is already documented in superio/smsc/kbc1100/kbc1100.h, so
currently I don't need these documents. I'm going to use
the DSDT dump to implement other features.

Iru


>
> //Peter
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Improving KBC1126 support for HP laptops

[Iru Cai]

Hi,

I'm now doing the port for HP Elitebook 2760p (
https://review.coreboot.org/#/c/18241/) and other HP laptops, but I'm now
having trouble with the EC+SuperIO chip KBC1126.

Now I can use superio/smsc/kbc1100 to enable keyboard support. However, I
still cannot access the EC with ectool, which will give me all 0xff when I
run `ectool -d`. Also I cannot use the touchscreen even I write some ACPI
code.

I have searched and downloaded two SMSC confidential document: a KBC1122
preliminary datasheet and a KBC1122 BIOS porting guide. Is there any
problem if I use them to write some code?

Thanks,
Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Coreboot on Thinkpad "X62" (i7-5600u)?

[Iru Cai]

Hello,

On Thu, Feb 23, 2017 at 3:46 PM, Rafael Send  wrote:

> Hello there-
> I'm assuming this is the right way to ask a general question, but please
> let me know if it isn't.
>
> I have an "X62" laptop, which is actually an old Thinkpad X61 with a
> custom motherboard in it.
> This board has an i7-5600u CPU on it, and I was wondering if it was
> possible to build a version of coreboot for this machine.
> I see an existing mailing list entry in the archive discussing a
> Chromebook Pixel with the same CPU, so I'm thinking it may be possible
> unless I'm missing something major.
> Since this is a custom motherboard, how would I find out about the Intel
> Boot Guard and related issues so that I can provide the details for the
> good folks here?
>

You can try https://review.coreboot.org/#/c/16328/, or modify some
instructions in the firmware to see if it still boots.

If boot guard is not enabled, I think booting with coreboot is not so hard,
but it may be hard to make the EC interface work fine.

Iru

I'm pretty comfortable around Linux but probably would have trouble
> building this from scratch.
> Thanks in advance!
>
> Rafael
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] T520 2630QM 16GB DIMM

[Iru Cai]

Ivy Bridge doesn't support 16GB DIMMs either. I've opened a ticket before.
https://ticket.coreboot.org/issues/56

On Thu, Feb 23, 2017 at 8:33 AM,  wrote:

> It would be really great if you could test out a Core i7-3840QM in the G2
> socket of the Thinkpad T520. Its the best ivy bridge with 45W TDP and the
> Core i7-3840QM officialy support 32GB of RAM.
>
> The Lenovo OEM Bios wont support ivy bridge. Coreboot didnt have such
> limitations ;)
>
> Thanks!
>
> 21. Feb 2017 22:08 by coreb...@tricnet.de
> 
> :
>
> Hi Arthur,
>
> Zitat von Arthur Heymans  >:
>
> >* Thomas Richter  >> writes:
> *>>* Is Sandy Bridge E so different from Sandy Bridge? Would it be possible
> *>>* Sandy Bridge E are high end desktop/server CPUs that have a different
> *>* socket (lga2011) and likely a different memory controller (4 channels
> *>* instead of 2).
> *>* A quick look at datasheet says nothing about maximum rank size.
> *
> I see.
>
> >>* to replace the 2620QM with an Ivy Bridge CPU?
> *>>* Afaik that should be possible since the CPU is socketed on that model
> *>* but won't overcome your issue. (same limitation)
> *
> Thank your for your time to explain. Seems like I have to look for a
> new laptop then ;-).
>
> It was a fun project, I learned a lot and I'm really impressed by the
> usability. Will definitely keep coreboot on the t520!
>
> Best,
>
> Thomas
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>



-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Using as default external monitor for booting in x230

[Iru Cai]

Hi,

I've just flashed my X230 using Linux payload with petitboot. It can
light up the screen when the payload runs without any graphics init
(native gfx or VGA BIOS) in coreboot.

My petitboot payload is built with the buildroot project from Arthur
Heymans[0]. I forked it and updated buildroot to a newer version.

[0]: https://github.com/ArthurHeymans/petitboot_for_coreboot

[1]: https://github.com/mytbk/petitboot_for_coreboot/tree/buildroot-2016.11

Iru


On 2017年01月13日 20:46, Car.cuevas via coreboot wrote:
>
> Hi all,
>
> First thanks to all for such an amazing job, I just realized that
> Coreboot is already working in the lenovo x230, and I am really
> thinking in flash it and give a try :) But since I have a mod in my
> x230 for having FHD (edp screen), somehow I will need to somehow setup
> on the bios that I need to use the external Digital output (the one
> used for the dock station) as default... Is it any way to configure that?
>
> thanks very much in advance :)
>
>
>
>
>
>


-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] "FCH SPI: Too much to write" on KGPE-D16

[Iru Cai]

Hello Timothy,

On 2017年01月06日 01:14, Timothy Pearson wrote:
> On 01/05/2017 04:33 AM, Iru Cai wrote:
> > Hello,
>
> > I've set up a computer with Asus KGPE-D16 recently. I use an Winbond
> > W25Q64.V 8M flash chip and tested with this config with only ROM size
> > changed:
>
> >
> https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.5-759-gab8f7d3/2017-01-04T21_18_55Z/config.short.txt
>
> > And it can boot to my OS on disk. However, after I enabled the serial
> > console, I can only see:
> > "FCH SPI: Too much to write. Does your SPI chip driver use
> > spi_crop_chunk()?"
>
> Do you see any other messages at all from a cold start (i.e. AC power
> removed from the system, then reapplied after 15 seconds while the
> serial console is being logged)?
>

I have other console logs, but not about this SPI issue, I came into
other problems when I try other configurations.

I don't know if it's related to serial console. The config on board
status and the ROMs from libreboot all boots, but they all have no
serial console output.

> I have not personally tested the 8M chips; it could be that there is an
> issue with coreboot's generic driver for those devices.  I know it's not
> a general issue with large Flash chips since the 16M chips work fine.
>
Thanks for the info.
> Thanks!
>
Iru


-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] "FCH SPI: Too much to write" on KGPE-D16

[Iru Cai]

Hello,

I've set up a computer with Asus KGPE-D16 recently. I use an Winbond
W25Q64.V 8M flash chip and tested with this config with only ROM size
changed:

https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.5-759-gab8f7d3/2017-01-04T21_18_55Z/config.short.txt

And it can boot to my OS on disk. However, after I enabled the serial
console, I can only see:
"FCH SPI: Too much to write. Does your SPI chip driver use
spi_crop_chunk()?"

And the machine cannot boot.

Has anyone seen this issue before?

Thanks,
Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] commit 94f8699 bricks my Lenovo X230

[Iru Cai]

Hi,

The latest git code bricks my Lenovo X230. After a git bisect, I found the
bad commit is 9438699[1] and reverting will work. The log from USB debug
console says there's an exception after the ``erase MRC cache`` message.

Lenovo X230 has two flash chips. I don't know if it's related to this.

[1]: https://review.coreboot.org/#/c/17684/

Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] T430s or T430 (Was: latest greatest thinkpad with coreboot)

[Iru Cai]

On 2016年12月04日 07:18, Nico Huber wrote:
> On 03.12.2016 01:46, Sam Kuper wrote:
>> On 02/12/2016, Nico Huber  wrote:
>>> The T430 seems to be unsupported.
>>> Also I guess, it would only be one or two days of work
>> One or two days of work for whom? E.g. did you have in mind a specific
>> person (if so, who?), or a non-specific person with a specific skill
>> set (if so, which skill set?)?
> Well, it's a really rough estimate to be honest. I'd say one day for
> somebody who already did a Sandy/Ivy Bridge ThinkPad port. Two days
> for somebody who knows his way around Intel boards in coreboot. Maybe
> it can also be done in two days with autoport and asking questions in
> IRC (by somebody coreboot experienced who is skilled in C).

I guess maybe a "Clone of: lenovo/t530" is enough.

>
> This doesn't account for hardware access (flashing, debugging) ofc.
>
> Nico
>
>


-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Powersavings: 8W of difference between bios and coreboot

[Iru Cai]

Hi,

On Fri, Nov 18, 2016 at 4:43 PM, Felix Held 
wrote:

> Hi!
>
>
> BIOS: 11W Coreboot: 19W [...]
>>
> Can you also measure the power consumption with the GPU enabled under the
> vendor firmware?
>
> and no, the NVidia GPU was not enabled in corebooy. Both results were on
>> integrated GPU only
>>
> Have you only disabled the nVidia GPU in devicetree.cb (that will only
> disable the PCIe interface on the CPU side) or have you also disabled the
> GPU power supply via the GFXCORE_ON_D signal? Since that signal is driven
> by the power management companion chip (Thinker-1), you probably have to
> talk to the EC to do that.
>

I don't know if Charlotte has added the ID of the dGPU to
src/drivers/lenovo/hybrid_graphics.c. Does the dGPU consume power after
hybrid_graphics.c disable the dGPU?

Regards
> Felix
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>

Regards,
Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Need advice on modifying mainboard dsdt file

[Iru Cai]

Hi,

I've just dumped a stock ACPI DSDT table of a Lenovo ThinkPad. I need to
update the device section of the machine. Currently the acpi/superio.asl
file of the mainboard is a line ``#include
``, in which I hope to modify a device
section to add the mouse hardware ID to it instead of using the compatible
PNP0F13.

What is the best way to modify the dsdt file so that I can use the new dsdt
without interfering other boards which is using ps2_controller.asl?

Thanks,
Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] EC problem in X200s?

[Iru Cai]

Hi,

Recently, I flashed libreboot to my X200s (with L9300 CPU). But it seems
that there are some EC problems in X200s, which I haven't found in a X200.

1. With a third party battery, when I put the X200s on dock, it'll shut
down.
2. With a third party battery, the battery will not charge, but it can
charge on a libreboot X200 or another X200s (with a single core Celeron
CPU, not tested on the same X200s) with factory firmware.
3. At last I bought a factory battery, the first two problems will not
appear. In these two days, I found that when I charge with a 90W adapter,
the CPU will get very hot and the laptop will shut down. It seems that
it'll not happen with a 65W adapter.

Iru

-- 
Please do not send me Microsoft Office/Apple iWork documents. Send
OpenDocument instead! http://fsf.org/campaigns/opendocument/
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Diassemble i946GZ ?

[Iru Cai]

It's in SerialICE project, not in coreboot project.


On 2016年10月17日 10:23, Antonius Riko wrote:

I can not see
D946GZIS

on my src/mainboard/intel where is it ?





-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Does anyone know about SMSC KBC1126?

[Iru Cai]

Hi,

I'm trying to work with some HP machines. I disassembled these machines and
saw they the EC chip SMSC KBC1126-NU. I read the backup firmware and can
see strings like `8051 RESET`, and I found if I modify certain part of the
firmware, the machine will fail to power with some LEDs blinking, so I know
the EC firmware is in the BIOS chip, and it's an 8051 program.

I searched about this chip, and some people say the EC chip also contains
program. I can't find anything about this chip, and coreboot wiki has
KBC1122 and I only found a 5-page product review on the Internet. I don't
know if there's anyone know about this EC. I want to know about:
- Where is the entry point of the EC firmware in the BIOS chip
- How this EC chip does the power management and keyboard control

Thanks,
Iru
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] anyone use coreboot on Lenovo T520?

[Iru Cai]

Hi Patrick,

On Wed, Sep 07, 2016 at 05:36:45PM +0200, Patrick Rudolph wrote:
> On Wed, 7 Sep 2016 21:15:05 +0800
> Iru Cai <mytbk920...@gmail.com> wrote:
> 
> Hi Iru,
> I've got a T520 with soldered pin header as in the referenced wiki page,
> and I've got a T420 where I had to use 10cm long wires to place the pin
> header near the RAM slots to make it accessible through the bottom flap.
>

I never solder pins on T420, and have no such problem. Maybe there's
something to do with my soldering skills.

> I've got no problems using both devices.
> 
> Can you give more information where the system hangs ?
> Does it hang in coreboot? Does it occur after hours running the system ?

The machine boots fine to Linux, but it can freeze after some time,
and I can't predict when this will happen.

> 
> Regards,
> Patrick
>

Regards,
Iru

> > Hi community,
> > 
> > I've had this problem for a long time, but I don't feel like to ask it
> > until some one ask me about this problem.
> > 
> > Lenovo T520 has a BIOS chip under the magnesium structure frame, and
> > it may have a WSON package, so I solder a pin connector at the `J100'
> > solder place. (https://www.coreboot.org/Board:lenovo/t520#Flashing)
> > However, I don't know whether it can cause problems. I flashed two
> > pieces of T520 mainboard (without nVIDIA GPU) before, and after it had
> > coreboot installed, the system could hang randomly, I don't know what
> > had happened. I hadn't tested it with the pin connector soldered and
> > factory firmwae.
> > 
> > So I hope some one with this laptop can report some status in using.
> > 
> > Regards,
> > Iru
> 


signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] anyone use coreboot on Lenovo T520?

[Iru Cai]

Hi community,

I've had this problem for a long time, but I don't feel like to ask it
until some one ask me about this problem.

Lenovo T520 has a BIOS chip under the magnesium structure frame, and
it may have a WSON package, so I solder a pin connector at the `J100'
solder place. (https://www.coreboot.org/Board:lenovo/t520#Flashing)
However, I don't know whether it can cause problems. I flashed two
pieces of T520 mainboard (without nVIDIA GPU) before, and after it had
coreboot installed, the system could hang randomly, I don't know what
had happened. I hadn't tested it with the pin connector soldered and
factory firmwae.

So I hope some one with this laptop can report some status in using.

Regards,
Iru


signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] 16GB dimm on Sandy/Ivy Bridge status

[Iru Cai]

Hi,

I'm tesing to see if the coreboot Sandy/Ivy MRC supports 16GB DIMMs. Here's
my result.

I'm using a MT16KTF2G64HZ-1G6A1[1]. My machine is Lenovo T420 with
i7-3630QM. With this module inserted (I've tested 16G+0 and 16G+8G), the
system can light up, but it'll then get crashed.
- with GRUB2 payload, it'll crash after the payload loads
- with SeaBIOS payload with proprietary VGABIOS, I can see the prompt, and
can boot to a GRUB or syslinux loader on my USB stick, but when I try to
boot a system, it get crashed. If I boot to Memtest86+ on my USB stick, the
system will crash when memtest starts to test the memory.

And another thing I can see is, the first boot can boot to payload, but the
second boot will fail. I think it's caused by the MRC cache.

I'm still wondering if Sandy/Ivy northbridge can support 16GB DIMMs. I'll
give a more detailed EHCI debug output later. According to [2], I think the
incompatibility is an MRC issue instead of hardware incompatibility.

[1]
https://www.micron.com/parts/modules/ddr3-sdram/mt16ktf2g64hz-1g6?pc={E1D8F1A9-3DFC-4BD2-8A1E-C26ED261EB0A}
[2]
http://www.intelligentmemory.com/fileadmin/download/compatibilitylist.pdf

Iru.
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] A talk about coreboot

[Iru Cai]

On Sun, Apr 10, 2016 at 8:53 PM, Stefan Tauner <stefan.tau...@gmx.at> wrote:

> On Sun, 10 Apr 2016 01:45:03 +0800
> Iru Cai <mytbk920...@gmail.com> wrote:
>
> > Hi community,
> >
> > I gave a talk about coreboot in my LUG yesterday, and here's my
> > slides.
> >
> > https://bdwm.net/attach/boards/Linux/M.1460223002.A/coreboot-talk.pdf
>
> Hi Iru,
>
> I'll do a very similar talk in two weeks. Can I please re-use some of
> your stuff under a CC BY-SA license?
> https://creativecommons.org/licenses/by-sa/4.0/
>
> Well, I wrote a CC license in my source file, but not in the slides.
https://bdwm.net/attach/boards/Linux/M.1460223002.A/coreboot%2dtalk.src.tar.gz


> --
> Kind regards/Mit freundlichen Grüßen, Stefan Tauner
>
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] A talk about coreboot

[Iru Cai]

Hi community,

I gave a talk about coreboot in my LUG yesterday, and here's my
slides.

https://bdwm.net/attach/boards/Linux/M.1460223002.A/coreboot-talk.pdf

Iru


signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] hyper_threading in CMOS/NVRAM seems useless in many CPU models

[Iru Cai]

Hi,

I just tried to disable hyper-threading in my machine, and I found the
hyper_threading setting in NVRAM is useless. I searched in the code and
found only a few number of CPU code has in its Makefile.inc `subdirs-y +=
../hyperthreading', which can read the hyper_threading NVRAM option and
enable/disable hyper-threading.

Iru
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] What is mrc.bin and system agent binary?

[Iru Cai]

Hi,

I've bought a Chromebook Pixel 2013 and want to reflash the
firmware. I saw in the config that I need a system agent binary.  I
looked into 3rdparty/blobs/nb/intel/sb/ and found three binary files,
and the default one in nb/intel/sb/kconfig is systemagent-r6.bin.  And
I read the google/link wiki and saw another word called mrc.bin.  Are
they the same thing? And can I use the coreboot native MRC code for
google/link?

Regards,
Iru


signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Is it possible to flash coreboot with proprietary vendor tools?

[Iru Cai]

Hi,

Can I use proprietary vendor tools like winflash or a vendor BIOS
update disk to flash coreboot? I don't think it possible but I can't
find a reason to explain, or it may be possible if I modify the ROM
format to fit those tools.

Iru Cai


signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] about Ivy Bridge CPU with QM67 PCH

[Iru Cai]

Hi,

On Sun, Oct 18, 2015 at 06:44:09PM +0200, Peter Stuge wrote:
> Hi,
> 
> Iru Cai wrote:
> > I've been testing the Lenovo T420 port recently, and now I can
> > install an Ivy Bridge processor and run fine on Linux(except some
> > thermal issues).
> 
> That's pretty nice I think.
> 
> 
> > However, the native graphics initialization doesn't work properly
> ..
> > I don't know if someone has tried using mixed generation of CPU and
> > chipset combination with coreboot before,
> 
> Probably not.
I finally found it's lvds_num_lanes in devicetree.cb that breaks
native graphics initilization, because SNB and IVB use different values.
And it has been solved in this upstream commit:

commit c48f5ef3cc623a4b1bccdbc9cb3e1d15505b7ad4
Author: Vladimir Serbinenko <phco...@gmail.com>
Date:   Sun Oct 11 02:05:55 2015 +0200

Kill lvds_num_lanes

Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.

Thank you Vladimir Serbinenko.

> 
> 
> > I have pushed the patch that makes coreboot support both SNB and
> > IVB processor for review:
> > http://review.coreboot.org/#/c/12087/
> 
> Thanks! There is a source code style issue - you used two spaces
> instead of one tab to indent - please fix that, but other than that
> the patch looks fine to me.
> 
> But the two files gma_{sandy,ivy}bridge_lvds.c are a bit of a mess -
> they need to be cleaned up and can quite easily be unified into a
> single file, without having it become the mess that the i915 kernel
> code is. The key is to have a good data model, and the data model
> seems clear to me from the existing code.
> 
> For fun (or pain), take a look at: git diff 758a41 7137c5
> (sandy..ivy)
> 
> 
> //Peter
> 
> -- 
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

Iru Cai


signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] about Ivy Bridge CPU with QM67 PCH

[Iru Cai]

Hi,

I've been testing the Lenovo T420 port recently, and now I can install an Ivy 
Bridge processor and run fine on Linux(except some thermal issues). However, 
the native graphics initialization doesn't work properly before Linux kernel 
boots. I can see the GRUB interface but it displays bad as if it's on a panel 
larger than the laptop panel. Then, Linux kernel boots and the graphics become 
good again. I read some of the i915 driver code of Linux, and saw some code 
about PCH, so I think this issue has something to do about the southbridge. I 
don't know if someone has tried using mixed generation of CPU and chipset 
combination with coreboot before, and I hope this issue can be resolved.

I have pushed the patch that makes coreboot support both SNB and IVB processor 
for review:
http://review.coreboot.org/#/c/12087/

Iru Cai


signature.asc
Description: PGP signature
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] About the USB issue on the Lenovo T420 port

[Iru Cai]

Hi,

I'm using the new Lenovo T420 port on gerrit[1] and found a bug about
USB(in my post on the gerrit page). And just now I found a work around on
this issue.

First I tested a USB disk on the buggy USB port before suspending the
system, it works fine. Then I unplugged the USB disk, suspended my system,
resume, and replugged the disk, the bug occurred. Then I unplugged the
disk, reload the ehci_pci module as follows:

rmmod ehci_pci
modprobe ehci-pci

The I plugged in the USB disk, it worked fine again.

I think the kernel message[2] gives some information about it, because it
gives two different port number on the USB device. But I know almost
nothing about USB, so I'm not sure what's happening.

[1] http://review.coreboot.org/#/c/11765/
[2] see the attached dmesg.log

Iru Cai
[   42.540979] cfg80211: Exceeded CRDA call max attempts. Not calling CRDA
[   54.182991] usb 1-1.2: new high-speed USB device number 5 using ehci-pci
[   54.367251] usb-storage 1-1.2:1.0: USB Mass Storage device detected
[   54.367474] scsi host6: usb-storage 1-1.2:1.0
[   54.367662] usbcore: registered new interface driver usb-storage
[   54.370123] usbcore: registered new interface driver uas
[   55.526164] scsi 6:0:0:0: Direct-Access JetFlash Transcend 32GB   1100 PQ: 0 ANSI: 6
[   55.528752] sd 6:0:0:0: [sdb] 62914560 512-byte logical blocks: (32.2 GB/30.0 GiB)
[   55.529861] sd 6:0:0:0: [sdb] Write Protect is off
[   55.529875] sd 6:0:0:0: [sdb] Mode Sense: 43 00 00 00
[   55.530955] sd 6:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[   55.539236]  sdb: sdb1
[   55.543397] sd 6:0:0:0: [sdb] Attached SCSI removable disk
[   60.603534] usb 1-1.2: USB disconnect, device number 5
[   60.606630] sd 6:0:0:0: [sdb] Synchronizing SCSI cache
[   60.606738] sd 6:0:0:0: [sdb] Synchronize Cache(10) failed: Result: hostbyte=0x01 driverbyte=0x00
[   60.682151] cfg80211: Exceeded CRDA call max attempts. Not calling CRDA
[   64.226309] cfg80211: Exceeded CRDA call max attempts. Not calling CRDA
[   64.592577] cfg80211: Exceeded CRDA call max attempts. Not calling CRDA
[   64.694718] cfg80211: Exceeded CRDA call max attempts. Not calling CRDA
[   66.063520] PM: Syncing filesystems ... done.
[   66.278789] PM: Preparing system for mem sleep
[   66.279386] Freezing user space processes ... (elapsed 0.001 seconds) done.
[   66.280708] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[   66.281906] PM: Entering mem sleep
[   66.281936] Suspending console(s) (use no_console_suspend to debug)
[   66.282217] wlp1s0: deauthenticating from 3c:46:d8:1a:19:62 by local choice (Reason: 3=DEAUTH_LEAVING)
[   66.315814] sd 0:0:0:0: [sda] Synchronizing SCSI cache
[   66.315987] sd 0:0:0:0: [sda] Stopping disk
[   66.316053] cfg80211: Exceeded CRDA call max attempts. Not calling CRDA
[   66.332021] e1000e: EEE TX LPI TIMER: 0011
[   66.785234] PM: suspend of devices complete after 502.950 msecs
[   66.805226] PM: late suspend of devices complete after 19.975 msecs
[   66.806565] ehci-pci :00:1d.0: System wakeup enabled by ACPI
[   66.806829] ehci-pci :00:1a.0: System wakeup enabled by ACPI
[   66.825299] PM: noirq suspend of devices complete after 20.061 msecs
[   66.825888] ACPI: Preparing to enter system sleep state S3
[   67.505180] ACPI : EC: EC stopped
[   67.505180] PM: Saving platform NVS memory
[   67.505181] Disabling non-boot CPUs ...
[   67.505211] intel_pstate CPU 1 exiting
[   67.506406] kvm: disabling virtualization on CPU1
[   67.506413] smpboot: CPU 1 is now offline
[   67.506682] intel_pstate CPU 2 exiting
[   67.508093] kvm: disabling virtualization on CPU2
[   67.508107] smpboot: CPU 2 is now offline
[   67.508859] intel_pstate CPU 3 exiting
[   67.510203] kvm: disabling virtualization on CPU3
[   67.510218] smpboot: CPU 3 is now offline
[   67.512248] ACPI: Low-level resume complete
[   67.512289] ACPI : EC: EC started
[   67.512290] PM: Restoring platform NVS memory
[   67.512604] Enabling non-boot CPUs ...
[   67.512644] x86: Booting SMP configuration:
[   67.512645] smpboot: Booting Node 0 Processor 1 APIC 0x1
[   67.523727] kvm: enabling virtualization on CPU1
[   67.525906]  cache: parent cpu1 should not be sleeping
[   67.526052] CPU1 is up
[   67.526075] smpboot: Booting Node 0 Processor 2 APIC 0x2
[   67.537147] kvm: enabling virtualization on CPU2
[   67.539310]  cache: parent cpu2 should not be sleeping
[   67.539448] CPU2 is up
[   67.539489] smpboot: Booting Node 0 Processor 3 APIC 0x3
[   67.550565] kvm: enabling virtualization on CPU3
[   67.552771]  cache: parent cpu3 should not be sleeping
[   67.552922] CPU3 is up
[   67.555854] ACPI: Waking up from system sleep state S3
[   68.067403] ehci-pci :00:1a.0: System wakeup disabled by ACPI
[   68.067470] ehci-pci :00:1d.0: System wakeup disabled by ACPI
[   68.067598] sdhci-pci :03:00.0: MMC controller base frequency changed to 50Mhz.
[   68.067690] PM: noirq resume of devices complete after

[coreboot] coreboot on Lenovo T420

[Iru Cai]

Hi,

I installed coreboot on my Lenovo ThinkPad T420 laptop today, and I'd like
to share some experience and hope some one can solve some issues on it.

First, I built the T420s port and flashed it to the T420 laptop.
Fortunately, the laptop could be brought up and boot to Linux. However,
several USB ports didn't function properly(except the one for EHCI debug)
because of the difference between T420s and T420 model. Now I've checked
and used the code from the result generated from autoport, and all the USB
ports work fine.

However, the devicetree.cb file generated from autoport does not work
properly. I use GRUB payload with native graphic init. When I use the T420s
devicetree.cb, it works fine, but with the autoport devicetree.cb, only the
backlight is on and nothing displays. At last I built a kernel for GRUB
payload, and the kernel handled the display properly, then I reflashed
another ROM with flashrom to unbrick my laptop.

So can some one give me some instruction on devicetree.cb file? And another
thing, how can I submit the code to the coreboot repository? Is symlinks to
another source files allowed in the source tree?

Iru Cai
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Has anyone ported coreboot to ThinkPad T420?

[Iru Cai]

Hi, community

I found Lenovo X220, T420s and T520 have coreboot support, but T420 is not
in the support list. I used the autoport tool in coreboot, and found some
differences(e.g. GPIO) between T420 and the supported models. I think it
should be easy to port it.

I've just disassembled a Lenovo ThinkPad T420, and found a Winbond 25Q64CV
flash after I moved the mainboard out. However, I couldn't read it with my
flash programmer. I don't know if the flash can be read if I try another
programmer or SOIC-8 clip.

Iru
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] build fails when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set

[Iru Cai]

Hi,

I was trying to build coreboot with the latest git code and build failed
when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set. Some of the error message
is:

$ make
CREATE build/mainboard/lenovo/x220/cbfs-file.c7KD3B.out (from
src/mainboard/lenovo/x220/cmos.default)
Created CBFS (capacity = 1046552 bytes)
E: Input file size (68464) greater than page size (65536).
GENgenerated/romstage.ld
LINK   cbfs/fallback/romstage.debug
OBJCOPYcbfs/fallback/romstage.elf
CBFS   coreboot.pre
CC northbridge/intel/sandybridge/gma_sandybridge_lvds.ramstage.o
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c: In function
'i915lightup_sandy':
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c:195:21: error:
'struct edid' has no member named 'hborder'
  right_border = edid.hborder;
 ^

After I searched the git log, I found this commit cause the error:
commit 7dbf9c6747ccdfa8b993d3843a22722742957611
Author: David Hendricks <dhend...@chromium.org>
Date:   Thu Jul 30 18:49:48 2015 -0700

edid: Use edid_mode struct to reduce redundancy

This replaces various timing mode parameters parameters with
an edid_mode struct within the edid struct.

I hope someone will fix the error soon.

Iru Cai
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] ectool misusage in autoport

[Iru Cai]

Hi,

I'm trying to use autoport to port coreboot to a machine. However, when I
look at the logs generated by:
./autoport --input_log=logs --make_logs --coreboot_dir=../..

I saw in logs/ectool.log:
../ectool/ectool: invalid option -- 'a'
usage: ../ectool/ectool [-vh?Vidq] [-w 0xaddr -z 0xdata]

So the autoport program doesn't make use of ectool, and it needs some
fixing.

Iru
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] memtest86+ test fails at 3070.7MB

[Iru Cai]

Hi,

I installed coreboot(4.1-315-gf58746b) on a ThinkPad X220, with factory VGA
option ROM and SeaBIOS 1.7.5 as payload. When I run memtest86+ on this
machine, it reports a fail at 3070.7MB. If I just install a 2GB memory
module, it passes the test. So what makes memtest86+ give a test failure?

Iru
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Is it possible to use an Ivy Bridge CPU in an Sandy Bridge laptop?

[Iru Cai]

Hi,

Ivy Bridge processor can be installed on a 6 series motherboard on desktop.
However, Intel didn't give official support for snb laptops to install an
ivb processor. Did anyone tried to insall an ivb processor into an snb
machine (I think ThinkPad T520 is a good choice.) to check whether coreboot
can support this?

Thanks,
Iru
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] How to check if DRAM init is OK?

[Iru Cai]

Hi,

I'm now porting coreboot to CubieTruck, a development board with an
Allwinner A20 SoC. I use Mr.Nuke's code[1] and Allwinner's user manual for
reference.However, when I modified the code and tested with the board, the
console gave only two lines of message and it get stuck. So I thought DRAM
init failed. I put some printks at bootblock_media.c, and found the bug
occurs at line 118[2], which showed the access of a certain memory space
caused the error. So I need to know how to check if the DRAM init works.

Thanks
Iru Cai

[1] https://github.com/mrnuke/coreboot/tree/cubie_mmc
[2]
https://github.com/mrnuke/coreboot/blob/cubie_mmc/src/cpu/allwinner/a10/bootblock_media.c#L118
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] coreboot for vexpress-v9 qemu failed

[Iru Cai]

Hi,

I am using QEMU from Arch Linux x86_64 official repo. I need to test my
built u-boot payload, so I tried to build a QEMU ARM coreboot image.
However, it failed to run and had the following output.

qemu: fatal: Trying to execute code outside RAM or ROM at 0xfffe

R00= R01=00011b70 R02= R03=
R04=00c51878 R05=0147 R06= R07=
R08= R09= R10= R11=
R12=0002 R13=000fffd8 R14= R15=fffe
PSR=60ff -ZC- T sys32
s00= s01= d00=
s02= s03= d01=
s04= s05= d02=
s06= s07= d03=
s08= s09= d04=
s10= s11= d05=
s12= s13= d06=
s14= s15= d07=
s16= s17= d08=
s18= s19= d09=
s20= s21= d10=
s22= s23= d11=
s24= s25= d12=
s26= s27= d13=
s28= s29= d14=
s30= s31= d15=
s32= s33= d16=
s34= s35= d17=
s36= s37= d18=
s38= s39= d19=
s40= s41= d20=
s42= s43= d21=
s44= s45= d22=
s46= s47= d23=
s48= s49= d24=
s50= s51= d25=
s52= s53= d26=
s54= s55= d27=
s56= s57= d28=
s58= s59= d29=
s60= s61= d30=
s62= s63= d31=
FPSCR: 

After I add '-S -s' option to QEMU, I found the problem is in
bootblock_simple.c, and the `main()' function in gdb is:

0x0192 in ?? ()
= 0x0192:08 b5push{r3, lr}
(gdb) disas $pc,+50
Dump of assembler code from 0x192 to 0x1c4:
= 0x0192:push{r3, lr}
   0x0194:bl0x1704
   0x0198:bl0x18c
   0x019c:bl0xd10
   0x01a0:bl0x634
   0x01a4:bl0x18e
   0x01a8:bl0x190
   0x01ac:ldmia.wsp!, {r3, lr}
   0x01b0:b.w0x159c
   0x01b4:push{r3, lr}
   0x01b6:mrc15, 0, r3, cr1, cr0, {0}
   0x01ba:lslsr2, r3, #29
   0x01bc:bpl.n0x1c4
   0x01be:bl0x2ac
   0x01c2:b.n0x1cc
End of assembler dump.
(gdb) si
0x0194 in ?? ()
= 0x0194:01 f0 b6 fabl0x1704
(gdb) b *0x198
Breakpoint 3 at 0x198
(gdb) c
Continuing.

Breakpoint 3, 0x0198 in ?? ()
= 0x0198:ff f7 f8 ffbl0x18c
(gdb) b *0x19c
Breakpoint 4 at 0x19c
(gdb) c
Continuing.

Breakpoint 4, 0x019c in ?? ()
= 0x019c:00 f0 b8 fdbl0xd10
(gdb) b *0x1a0
Breakpoint 5 at 0x1a0
(gdb) c
Continuing.
Remote connection closed

So there may be something wrong when setting up the console, however I'm
not so familiar with debugging the ROM so I don't know which function call
raise the problem.

Thanks,
Iru
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] On Intel Boot Guard

[Iru Cai]

Hi,

I've just seen a forum thread about removing the white list of ThinkPad
X240, so I think Boot Guard is not preventing modification of BIOS. Then I
read some article, which says what Boot Guard locks is the boot block, so I
think there's still some way to flash coreboot on a new Intel platform.
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] How can I load SeaBIOS from GRUB with native VGA+VGA option ROM

[Iru Cai]

I read previous config files from board status, and configured my Lenovo
ThinkPad X220 with CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT and
CONFIG_VGA_ROM_RUN. And according to:
http://www.coreboot.org/pipermail/coreboot/2014-July/078342.html

I added the bios.bin.elf to GRUB and vgabios.bin to CBFS. However, after I
chose SeaBIOS in GRUB, SeaBIOS was loaded and the screen became blank. I'm
not sure if there's something wrong with option ROM and SeaBIOS.
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Question on VGA BIOS extraction

[Iru Cai]

Hi,

I'm trying to build Coreboot for ThinkPad X220. I first backup the vendor
BIOS, then use UEFITool to extract a VBIOS. The romheader program detects
the ROM's PCI data structure and reports the device id is 8086:0106, but
the VGA controller's device id is 8086:0126. I extracted the video ROM from
a running X220 memory and use romheader to test it, the result is still
8086:0106. How could this happen?

Iru
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] GRUB2 is too big as a payload in ThinkPad X201

[Iru Cai]

I finally know what happened. I forgot to rip out the fonts, themes and
languages of the payload.


On Thu, Mar 26, 2015 at 3:10 PM, Zaolin zao...@das-labor.org wrote:

 Hi,

 simply fix this problems by increasing the cbfs size in menuconfig
 under the chipset section.

 Regards Zaolin
  Dear Iru,
 
 
  welcome to coreboot!
 
 
  Am Donnerstag, den 26.03.2015, 09:33 +0800 schrieb Iru Cai:
   I tried to use GRUB2 as a payload when building coreboot for ThinkPad
 X201,
   but it's too big to fit into the rom. The GRUB2 coreboot image without
   modules is 2.8M and 800K after compressing, it's still too big.
 
  building GRUB directly, I get a different result.
 
  $ git describe
  grub-2.02-beta2-372-g5974d4b
  $ ./autogen.sh
  $ ./configure --with-platform=coreboot --enable-boot-time
 --enable-cache-stats
  $ make
  $ edit Makefile
 
  Now adapt the rule `default_payload.elf`.
 
  default_payload.elf: grub-mkstandalone grub-mkimage
pkgdatadir=. ./grub-mkstandalone
 --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata
 ehci uhci ohci usb_keyboard usbms part_msdos xfs ext2 fat at_keyboard
 part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search
 configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot
 hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc
 linux16 gzio echo help' --fonts= --themes= --locales= -d grub-core/
 /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg
 
  Remove the modules you don’t need. With *my* ASRock E350M1 setup, I
  don’t need `pata`, `usbms`, `xfs`, `fat`, `at_keyboard`, `part_gpt` and
  `usbserial_usbdebug`. I then add `boottime` and `cacheinfo`.
 
  $ make default_payload.elf
 
  The file is now 578K big and in CBFS the compressed size is a little
  over 200 KB.
 
  $ build/cbfstool build/coreboot.rom print
  […]
  fallback/payload   0x5c400payload
  205851
  […]
 
  […]
 
 
  Thanks,
 
  Paul
 
 
  PS: I’d be great if you could just send plain text messages with no HTML
  parts to mailing lists.
  --
  coreboot mailing list: coreboot@coreboot.org
  http://www.coreboot.org/mailman/listinfo/coreboot


-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] GRUB2 is too big as a payload in ThinkPad X201

[Iru Cai]

I tried to use GRUB2 as a payload when building coreboot for ThinkPad X201,
but it's too big to fit into the rom. The GRUB2 coreboot image without
modules is 2.8M and 800K after compressing, it's still too big.

I think FILO and u-boot are good alternatives but not so user-friendly and
documented as GRUB2, so it's time to find a way to slim down GRUB2 as a
coreboot payload.
-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot