[coreboot] Re: Universal Payload - RFC and Invitation from Universal Payload community

payload. Happy to see your early feedback and this would be helpful for our early design process. Thanks, Subrata -Original Message- From: Peter Stuge Sent: Thursday, November 5, 2020 4:54 AM To: coreboot Cc: Banik, Subrata ; Zimmer, Vincent ; Ma, Maurice ; Sripathi, Srinivas

[coreboot] Universal Payload - RFC and Invitation from Universal Payload community

HI All, coreboot is a modular design with hardware initialization stage followed by a payload to boot OS https://doc.coreboot.org/payloads.html There is a new initiative to standardize the bootloader to payload interface. The initiative is called Universal Payload project and details can be

[coreboot] Re: Sandybridge-M help request in setting up LVDS panel.

HI Jose, Some input inline. Thanks, Subrata -Original Message- From: Jose Trujillo [mailto:ce.au...@protonmail.com] Sent: Tuesday, December 3, 2019 7:44 PM To: Banik, Subrata Cc: Nico Huber ; coreboot ; Patrick Georgi Subject: RE: [coreboot] Sandybridge-M help request in setting up

[coreboot] Re: Sandybridge-M help request in setting up LVDS panel.

HI Jorge, Some inputs inline. Thanks, Subrata -Original Message- From: Nico Huber [mailto:nic...@gmx.de] Sent: Tuesday, December 3, 2019 3:34 AM To: Jose Trujillo ; coreboot Cc: Banik, Subrata ; Patrick Georgi Subject: Re: [coreboot] Sandybridge-M help request in setting up LVDS

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

Great Youness. I guess you got the point it might be ucode. Sent from my iPhone > On 18-May-2018, at 11:23 PM, Youness Alaoui > wrote: > > coreboot : -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

ntel point of view. SKL won't be compatible with KBL FSP. Please don’t try to use KBL FSP and mix match with SKL Coreboot. No one tested that combination. Thanks, Subrata -Original Message- From: Piotr Król [mailto:piotr.k...@3mdeb.com] Sent: Thursday, May 17, 2018 9:38 PM To: Ba

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

-BEGIN PGP SIGNED MESSAGE- > Hash: SHA512 > > > > On 05/17/2018 06:20 PM, Banik, Subrata wrote: > > Hi Subrata, > >>>> FSP2.0, I'm following Librem Purism options since they seem to >>>> boot the same SoC. They use KabyLake FSP obtained by

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

believe timeout count somehow not meeting the max core running time. Thanks, Subrata -Original Message- From: Piotr Król [mailto:piotr.k...@3mdeb.com] Sent: Thursday, May 17, 2018 5:18 PM To: Banik, Subrata <subrata.ba...@intel.com> Cc: coreboot@coreboot.org Subject: Exception on S

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

[mailto:piotr.k...@3mdeb.com] Sent: Thursday, May 17, 2018 7:09 PM To: Banik, Subrata <subrata.ba...@intel.com> Cc: coreboot@coreboot.org Subject: Re: Exception on Skylake after enabling ACPI timer emulation -BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 05/17/2018 02:11 PM, Banik, S

Re: [coreboot] Exception on Skylake after enabling ACPI timer emulation

Please find my answer inline. Thanks, Subrata -Original Message- From: Piotr Król [mailto:piotr.k...@3mdeb.com] Sent: Thursday, May 17, 2018 5:38 PM To: Banik, Subrata <subrata.ba...@intel.com> Cc: coreboot@coreboot.org Subject: Re: Exception on Skylake after enabling ACPI

Re: [coreboot] What does *intelblocks* mean?

r...@google.com] Sent: Monday, June 5, 2017 9:11 PM To: Paul Menzel <paulepan...@users.sourceforge.net> Cc: Coreboot <coreboot@coreboot.org>; Banik, Subrata <subrata.ba...@intel.com> Subject: Re: [coreboot] What does *intelblocks* mean? On Mon, Jun 5, 2017 at 2:48 AM, Paul Menzel &l