Re: [coreboot] coreboot 4.4 release coming soon
Le vendredi 22 avril 2016 à 15:36 +0200, Paul Kocialkowski a écrit : > With those patches applied, the display is mangled on depthcharge as seen > on: http://download.paulk.fr/coreboot/nyan_big/nyan_big-display.jpg This was reported as https://ticket.coreboot.org/issues/50 and fixed by https:// review.coreboot.org/#/c/14564/ It would be nice to include this before the release! -- Paul Kocialkowski, low-level free software developer on embedded devices Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/ signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot 4.4 release coming soon
Here is a status report for the chromebooks I'm using: * veyron_speedy Boots fine with today's HEAD on a standard use case. However, my particular use case requires https://review.coreboot.org/#/c/14472/ which is trivial. * nyan_big Building with CHROMEOS requires https://review.coreboot.org/#/c/14474/ otherwise it hangs at bootblock. Merging the libpayload config before the release would also be nice: https://rev iew.coreboot.org/#/c/14472/ With those patches applied, the display is mangled on depthcharge as seen on: ht tp://download.paulk.fr/coreboot/nyan_big/nyan_big-display.jpg A boot log is attached to this email. It would be useful if someone else could try and let me know whether they can duplicate the issue. I'm unsure the issue comes from coreboot, depthcharge or my modifications to depthcharge and vboot. The repositories I'm using are: http://git.code.paulk.fr/gitweb/?p=coreboot.git;a=summary http://git.code.paulk.fr/gitweb/?p=depthcharge.git;a=summary http://git.code.paulk.fr/gitweb/?p=vboot.git;a=summary with branch libreboot-next Cheers, -- Paul Kocialkowski, low-level free software developer on embedded devices Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/coreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 bootblock starting... SF: Detected W25Q32DW with sector size 0x1000, total 0x40 CBFS @ 2 size e CBFS: 'Master Header Locator' located CBFS at [2:10) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 6a52 Ungating power partition 0. Power gate toggle request accepted. Ungated power partition 0. Ungating power partition 15. Ungated power partition 15. Ungating power partition 14. Power gate toggle request accepted. Ungated power partition 14. coreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 romstage starting... Exception handlers installed. get_sdram_config: RAMCODE=4 Initializing SDRAM of type 2 with 792000KHz sdram_size_mb: Total SDRAM (MB): 4096 LPAE Translation tables are @ 4000 Mapping address range [0x:0x8000) as uncached Mapping address range [0x4000:0x4010) as writeback Mapping address range [0x8000:0x) as writeback Mapping address range [0x9000:0x9020) as uncached Setting address range [0x:0x0010) as unmapped CBMEM: IMD: root @ fdfff000 254 entries. IMD: root @ fdffec00 62 entries. SF: Detected W25Q32DW with sector size 0x1000, total 0x40 CBFS @ 2 size e CBFS: 'Master Header Locator' located CBFS at [2:10) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 6b40 size ac26 oreboot-4.3-808-gcd77f2f-dirty Fri Apr 22 09:12:53 UTC 2016 ramstage starting... sdram_size_mb: Total SDRAM (MB): 4096 SF: Detected W25Q32DW with sector size 0x1000, total 0x40 FMAP: Found "FLASH" version 1.1 at 10. FMAP: base = 0 size = 40 #areas = 21 FMAP: area RO_VPD found @ 1f (65536 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 2f8000 (32768 bytes) WARNING: RW_VPD is uninitialized or empty. Exception handlers installed. BS: BS_PRE_DEVICE times (us): entry 1 run 0 exit 0 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 1 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 10761 usecs done BS: BS_DEV_ENUMERATE times (us): entry 1 run 32806 exit 0 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 Setting resources... Root Device assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 50080 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (us): entry 1 run 2609 exit 1 Initializing devices... Root Device init ... USB controller @ 7d00 set up with UTMI+ PHY USB controller @ 7d008000 set up with UTMI+ PHY SF: Detected W25Q32DW with sector size 0x1000, total 0x40 FMAP: area RW_ELOG found @ 27c000 (16384 bytes) ELOG: FLASH @0x80218440 [SPI 0x0027c000] ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024 ELOG: Event(17) added with size 13 out: cmd=0x87: 03 32 87 00 00 00 04 00 00 40 00 00 in-header: 03 d5 00 00 04 00 00 00 in-data: 04 20 00 00 out: cmd=0x17: 03 9c 17 00 01 00 14 00 00 00 00 00 04 2e 21 80 05 00 00 00 b1 b0 82 d4 7d 89 20 80 in-header: 03
Re: [coreboot] coreboot 4.4 release coming soon
Lenovo: - t400 - tested by CaptainCoward - boot - x201 - broken - doesn't boot - x220 - works @Martin: Can you create a rc1 tag for this? Everybody would against test the same revision. -- Alexander Couzens mail: lyn...@fe80.eu jabber: lyn...@fe80.eu mobile: +4915123277221 gpg: 390D CF78 8BF9 AA50 4F8F F1E2 C29E 9DA6 A0DF 8604 pgpOWw2kLbmR_.pgp Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot 4.4 release coming soon
On Wed, Apr 20, 2016 at 10:21 AM Jonathan Neuschäferwrote: > > I can get coreboot to boot in QEMU up to the "payload not loaded" > message with a few patches: > - I patched QEMU to not trap unaligned memory accesses > we're supposed to handle these traps, so something is broken. I would only trust spike however. > - I patched coreboot to use the HTIF console instead of a 8250 UART >memory-mapped at 0x3f8. > I suspect htis means the qemu or qemu target is still out of date, but who knows. >- Both the write_msr(tohost, ...) interface and the memory-mapped > HTIF at 0xF000 work. > good. > - I patched QEMU to dump characters written to the HTIF console, >because I couldn't figure out how to use it properly. > > Coreboot fails to boot Linux (configured vmlinux as an ELF payload, > because I couldn't find a compressed kernel): > > CBFS: Locating 'fallback/payload' > CBFS: Found @ offset cbc0 size 136043 > Loading segment from rom address 0x0002ccf8 > code (compression=1) > New segment dstaddr 0x0 memsize 0x35abe0 srcaddr 0x2cd30 filesize > 0x13600b > Loading segment from rom address 0x0002cd14 > Entry Point 0x8000 > SELF Payload doesn't target RAM: > Failed Segment: 0x0, 3517408 bytes >0. 0020-01fdafff: RAM >1. 01fdb000-01ffefff: CONFIGURATION TABLES >2. 01fff000-021f: RAM > Payload not loaded. > > we still only do uncompressed kernels. There are other problems with riscv right now, so I'm holding off doing anything until they are done redoing parts of the architecture spec. ron -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot 4.4 release coming soon
On Thu, Apr 14, 2016 at 04:46:06PM -0600, Martin Roth wrote: > Hi Everyone, > We're planning on doing the coreboot 4.4 release in the next week or so. > > We'd like to request some help with testing platforms both ahead of > the release and when the release actually happens. If you have a > board in the coreboot tree, please try doing a build to help us verify > what's working and to let us know about anything that isn't working. I did a few tests with coreboot 4.3-774-g7fae59b on virtual platforms, because I don't have any hardware supported by coreboot. QEMU 2.5.0, QEMU x86 i440fx/piix4 mainboard --- SeaBIOS/Linux boots fine, but cbmem fails with "Could not open /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq: No such file or directory". I did all x86 tests with Debian's kernel 3.16. QEMU 2.5.0, QEMU x86 q35/ich9 mainboard --- SeaBIOS/Linux boots fine, but cbmem fails with "Could not open /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq: No such file or directory". For some reason QEMU periodically generates NMIs: - In Linux this is printed every 30 seconds: [ 36.836053] Uhhuh. NMI received for unknown reason 30 on CPU 0. [ 36.836053] Do you have a strange power saving mode enabled? [ 36.836053] Dazed and confused, but trying to continue - SeaBIOS prints handle_02 - Coreinfo logs the NMI and dies. - If I first boot Linux and then reboot into coreinfo, the NMIs do not occur (maybe Linux disables them on reboot). QEMU riscv (v2.5.0-9-gb0cf38d + a few patches) -- In short: It doesn't work. I can get coreboot to boot in QEMU up to the "payload not loaded" message with a few patches: - I patched QEMU to not trap unaligned memory accesses - I patched coreboot to use the HTIF console instead of a 8250 UART memory-mapped at 0x3f8. - Both the write_msr(tohost, ...) interface and the memory-mapped HTIF at 0xF000 work. - I patched QEMU to dump characters written to the HTIF console, because I couldn't figure out how to use it properly. Coreboot fails to boot Linux (configured vmlinux as an ELF payload, because I couldn't find a compressed kernel): CBFS: Locating 'fallback/payload' CBFS: Found @ offset cbc0 size 136043 Loading segment from rom address 0x0002ccf8 code (compression=1) New segment dstaddr 0x0 memsize 0x35abe0 srcaddr 0x2cd30 filesize 0x13600b Loading segment from rom address 0x0002cd14 Entry Point 0x8000 SELF Payload doesn't target RAM: Failed Segment: 0x0, 3517408 bytes 0. 0020-01fdafff: RAM 1. 01fdb000-01ffefff: CONFIGURATION TABLES 2. 01fff000-021f: RAM Payload not loaded. Jonathan # # Automatically generated file; DO NOT EDIT. # coreboot configuration # # # General setup # CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" # CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set CONFIG_CCACHE=y # CONFIG_FMD_GENPARSER is not set # CONFIG_SCONFIG_GENPARSER is not set # CONFIG_USE_OPTION_TABLE is not set # CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_EARLY_CBMEM_INIT=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set # CONFIG_RELOCATABLE_MODULES is not set # CONFIG_RELOCATABLE_RAMSTAGE is not set CONFIG_FLASHMAP_OFFSET=0 CONFIG_BOOTBLOCK_SIMPLE=y # CONFIG_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_CUSTOM=y CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set # CONFIG_UPDATE_IMAGE is not set # CONFIG_GENERIC_GPIO_LIB is not set # CONFIG_BOARD_ID_AUTO is not set # CONFIG_BOARD_ID_MANUAL is not set # CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ARTECGROUP is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_AZZA is not set # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set # CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_ESD is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set #
Re: [coreboot] coreboot 4.4 release coming soon
Hi, I verified the mainboard Intel camelbackmountain_fsp with commit 831d65d0ba68be630e3c323e24e2be071456a9e8. I didn't see issue to boot to Fedora 21 and Windows 7, so it should be good for the upcoming release. Thanks, York -Original Message- From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Martin Roth Sent: Thursday, April 14, 2016 3:46 PM To: coreboot <coreboot@coreboot.org> Subject: [coreboot] coreboot 4.4 release coming soon Hi Everyone, We're planning on doing the coreboot 4.4 release in the next week or so. We'd like to request some help with testing platforms both ahead of the release and when the release actually happens. If you have a board in the coreboot tree, please try doing a build to help us verify what's working and to let us know about anything that isn't working. - If your board is working, please either submit a board-status report or even just post a response to this email saying what board you tested and which commit id you tested on. - If there's a problem with your board, filing a bug would be great, but an email describing the problem along with build and/or boot logs would be very helpful as well. If anyone has features that they would like to get in before the next release, please respond to this email or contact me directly. Martin -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot 4.4 release coming soon
Hey Martin. I have tested the mainboard siemens/mc_tcu3 with commit-ID b3ee03c404e0a26dc338a26f7ce01ddb8dafaaec and haven't found any issues. So consider this board as working for the upcoming release. Werner -Ursprüngliche Nachricht- Von: coreboot [mailto:coreboot-boun...@coreboot.org] Im Auftrag von Martin Roth Gesendet: Freitag, 15. April 2016 00:46 An: coreboot Betreff: [coreboot] coreboot 4.4 release coming soon Hi Everyone, We're planning on doing the coreboot 4.4 release in the next week or so. We'd like to request some help with testing platforms both ahead of the release and when the release actually happens. If you have a board in the coreboot tree, please try doing a build to help us verify what's working and to let us know about anything that isn't working. - If your board is working, please either submit a board-status report or even just post a response to this email saying what board you tested and which commit id you tested on. - If there's a problem with your board, filing a bug would be great, but an email describing the problem along with build and/or boot logs would be very helpful as well. If anyone has features that they would like to get in before the next release, please respond to this email or contact me directly. Martin -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot 4.4 release coming soon
Hi Everyone, We're planning on doing the coreboot 4.4 release in the next week or so. We'd like to request some help with testing platforms both ahead of the release and when the release actually happens. If you have a board in the coreboot tree, please try doing a build to help us verify what's working and to let us know about anything that isn't working. - If your board is working, please either submit a board-status report or even just post a response to this email saying what board you tested and which commit id you tested on. - If there's a problem with your board, filing a bug would be great, but an email describing the problem along with build and/or boot logs would be very helpful as well. If anyone has features that they would like to get in before the next release, please respond to this email or contact me directly. Martin -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot