> Do i need to flush cache if event and command rings are located in "normal"
> memory?
All Intel chipsets I know of support full cache snooping for the
integrated XHCI controller, so you shouldn't need any cache
management. Or are you trying to use an external (e.g. PCIe) XHCI
controller? In that
Hello *,
Sorry for delay, but i have to understand a lot things before answering (:
On 23/11/2016 14:25, Nico Huber wrote:
Hi,
On 23.11.2016 11:09, Pitrolle Jean-Jacques wrote:
Hello *,
I try to integrate coreboot *libpayload usb stack* in a custom binary
for x86.
I already succeed integration
Hi,
On 23.11.2016 11:09, Pitrolle Jean-Jacques wrote:
> Hello *,
> I try to integrate coreboot *libpayload usb stack* in a custom binary
> for x86.
> I already succeed integration of *ehci* for *qemu* and *core 2 duo*
> platforms.
>
> But things seems to be not so easy for *xhci*.
> When I try to
Hello *,
I try to integrate coreboot *libpayload usb stack* in a custom binary
for x86.
I already succeed integration of *ehci* for *qemu* and *core 2 duo*
platforms.
But things seems to be not so easy for *xhci*.
When I try to run coreboot master branch (with hash 8bf3f7a) on qemu
(version 2
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