Re: [coreboot] Please upload board status Asus AM1I-A

Dear Gergely, dear Elisenda, Welcome to coreboot and thank you for making and using the port for the Asus AM1I-A. Could one of you, please upload the current status to the board status repository? See the file `README` in `util/board_status/`. Please make sure, that you build from a non-dirty c

Re: [coreboot] QEMU x86_64 Q35 Automated Test Failure [master]

Dear Timothy, Am Samstag, den 10.02.2018, 18:32 -0600 schrieb REACTS: > The QEMU x86_64 Q35 fails verification for branch master as of commit > 1b64ae1119fc7891b043d5d29bf93859ef9dbfa1 > > The following tests failed: > BOOT_FAILURE > > Commits since last successful test: > 1b64ae1 soc/intel/ca

Re: [coreboot] Please upload board status Asus AM1I-A

Dear Paul, Sure, I will be happy to do it :-) Best Regards, Eli On 12/02/2018 9:47, Paul Menzel wrote: Dear Gergely, dear Elisenda, Welcome to coreboot and thank you for making and using the port for the Asus AM1I-A. Could one of you, please upload the current status to the board status r

Re: [coreboot] QEMU x86_64 Q35 Automated Test Failure [master]

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Disabled for now. There might be a disk space issue affecting this particular emulation target, looking into it. Sorry for the noise! On 02/12/2018 02:55 AM, Paul Menzel wrote: > Dear Timothy, > > > Am Samstag, den 10.02.2018, 18:32 -0600 schrieb

Re: [coreboot] Asus AM1I-A

Hi, taking a look at the diffs, I can't see any major difference. CONFIG_USE_BLOBS is y by default so setting it to y is not really useful. The only notable difference is that you used COM1 for console output instead of COM2 (which is the port soldered on-board). However, this does not seem to exp

Re: [coreboot] Asus AM1I-A

Hi Gergely, Sorry, I didn´t know the PCI IDs are APU depending. I´m using an Athlon 5350. Yes, the differences are minor. Only UART used and TTYS0_BASE address. Thank you for clarifying the memory requirement. I didn´t see it in the manual :-( . Maybe you can change the defaults for CONFIG

[coreboot] [RFC] Fix undefined behavior with left shifts in whole code base

Dear coreboot folks, TLDR; If coreboot wants to *make use of the undefined baviour sanitizer (UBSAN)* a solution needs to be found for left shift errors like in `1 << 31`, where the sign bit is ignored. The proposal is to adapt the code accordingly, that means `1U << 31`, although it’s not so pre