On Tue, Jan 14, 2020 at 5:49 PM Rafael Send
wrote:
>
>> Ok now I'm a bit confused. Can you elaborate on what some of your steps
> do?
>
1. Make an image of 16M in coreboot for your supported device
2. Set VSCC table to new chip (I found this not really necessary, ive seen
no PCH problems by
I am really curious how will it go. Please do post updates here. Since I was
thinking about doing the same just to fit freedos and space invaders on the
chip^^
May I ask which board is it?
Greets,
On January 14, 2020 1:18:09 AM UTC, Rafael Send
wrote:
>Hi there-
>I'd like to increase the
On Tue, Jan 14, 2020 at 10:32 AM Nico Huber wrote:
>
>
> The IFD also contains a small table about flash chips (e.g. to know the
> erase opcode / block size). I'm not sure if you need to adapt it or
> if the PCH would fall back to automatic discovery via SFDP. Might also
> depend on the PCH
>
> I did this exact thing while porting heads to a new motherboard, as the
> 4mb SPI was too small. Heres the steps, and they work.
Ok now I'm a bit confused. Can you elaborate on what some of your steps do?
- When you set chip size to 16MB but use the stock descriptor, you've
basically got a
re-sending to coreboot list due to a problem with my gmail subscription.
On Tue, Jan 14, 2020 at 10:32 AM Nico Huber wrote:
>
>
> The IFD also contains a small table about flash chips (e.g. to know the
> erase opcode / block size). I'm not sure if you need to adapt it or
> if the PCH would fall
Hi Rafael,
On 14.01.20 02:18, Rafael Send wrote:
> *2)* Modify fmap - currently looks like this:
>
> ...
> and it should become:
>
> FLASH@0xff80 0x100 {<- new chip size
you should also lower the offset to 0xff00. The flash is (assumed)
to be mapped right below 4GiB. So it should
Wow, thank you for all that info, even though I'm not going to replace anything
anytime soon. Since we're talking tech stuff, one thing I can share is
https://github.com/plaidml/plaidml deep learning library. Some months ago I
couldn't get it to work on Linux/AMD, but last week I've tried again
Hi all,
I using intel denvertonNS Soc setting register lpc decode/enable com A and
comB, but coreboot no console message on lpc.
I check hard strap pin is setting LPC Decode Select .
Best Regards,
Jason
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