[coreboot] Fwd: coreboot Kconfig missing deps on x201 board

Hi list, unfortunately Vladimir who probably is a right person to talk about this issue did not responded yet, so I am reposting my issue for a wider audience: both master and classic-2014.10 are not able to fulfill config dependencies when this particular board is selected: warning:

Re: [coreboot] Interrupt mapping with NetBSD

On Sat, Jun 27, 2015 at 4:28 PM, Jonathan A. Kollasch jakll...@kollasch.net wrote: On Sat, Jun 27, 2015 at 04:09:08PM +0300, Andrey Korolyov wrote: Hello, can anyone please provide a solid pointer for a 'patch' mentioned in http://www.coreboot.org/NetBSD#Interrupt_routing? It looks like

[coreboot] Interrupt mapping with NetBSD

Hello, can anyone please provide a solid pointer for a 'patch' mentioned in http://www.coreboot.org/NetBSD#Interrupt_routing? It looks like that the even recent MPBIOS code in NetBSD kernel is not able to place all interrupts correctly if coreboot is used with SeaBIOS payload, my 82577 does not

Re: [coreboot] Interrupt mapping with NetBSD

On Sat, Jun 27, 2015 at 4:58 PM, Andrey Korolyov and...@xdel.ru wrote: On Sat, Jun 27, 2015 at 4:28 PM, Jonathan A. Kollasch jakll...@kollasch.net wrote: On Sat, Jun 27, 2015 at 04:09:08PM +0300, Andrey Korolyov wrote: Hello, can anyone please provide a solid pointer for a 'patch' mentioned

[coreboot] i855GM on laptop - possible or not?

Hello, I am trying to estimate amount of effort to make an old military Getac to work with coreboot (currently it runs Insyde with computrace-style code). All currently supported boards, lanner/em8510 and digitallogic/adl855pc are desktops, which means that I should play with EC support almost

Re: [coreboot] i855GM on laptop - possible or not?

On Mon, Aug 3, 2015 at 4:43 PM, Stefan Reinauer stefan.reina...@coreboot.org wrote: Hi Andrey, * Andrey Korolyov and...@xdel.ru [150802 22:22]: I am trying to estimate amount of effort to make an old military Getac to work with coreboot (currently it runs Insyde with computrace-style code

[coreboot] romcc issue with loop execution?

Hello, during initial bootstrap of an ancient Geode board I found that the romstage hangs at src/northbridge/amd/lx/raminit.c: 750 volatile unsigned long *ptr; >>> 751 for (i = 0; i < 5; i++) { 752 ptr = (void *)i; 753 *ptr =

Re: [coreboot] Compile coreboot 4.3 for Pc Engines Alix2d3

On Mon, Mar 7, 2016 at 2:19 AM, Reto Rayen wrote: > Hi guys > > > > I tried now with the latest coreboot 4.3 to run the coreboot bios on a > Alix2d3. But it always hangs after: «* DRAM Controller init done.». After > this i do not see any further Output. Does anyone of you

[coreboot] Offtopic - tapping TxFP packages with flat cables?

Hi, probably several people in the list met the same struggle to tap 0.5mm pitched packages (almost all SIOs and at least all H8/300 chips) - how it could be done without using micromanipulator or sticking flat cable with an equal pitch size on side of a chip? While it is possible to solder a

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

> The chipset in the (QC version of the) W510 is actually exactly the same as > in the X201 and T410s: Ibex Peak. > But CPUs we are looking at *are* actually different - scale-down could mean an exposure of a previously unaccounted design issue which actually prevented 32nm CPU 'upgrade' to work

Re: [coreboot] 8 GB DIMMs on Nehalem (Arrandale)

> Not sure if I interpret "within an entire family" correctly, but the > online specs for the 820QM are clearly wrong Yes, this statement is very blurry - I thought about artificial memory limitations like ones in C2000 Atom server series - there are almost identical models (C2530 and C2550 for

Re: [coreboot] Offtopic - tapping TxFP packages with flat cables?

> > Buy another chip, make a breakout board, remove onboard chip, connect > probes to breakout board, connect breakout board to mainboard. > Thanks, but this is a pretty time-consuming method if I need to tap four consecutive legs out of one hundred. Also BBs adding extra crosstalk which could

Re: [coreboot] Nehalem not booting with two ram sticks

On Tue, Nov 22, 2016 at 3:35 PM, Federico Amedeo Izzo wrote: > Hello, > > I have a problem with my ThinkPad X201 (nehalem) > > I have two sticks of Samsung 4GB 2Rx8 PC3-10600S (1333MHz) > When i use only one of them in one of the two slots, the computer boots > fine, >

Re: [coreboot] power controller/serial port mux

> With Schuko plug this ethernet controlled power strip is pretty nice > (they also have a USB-controlled variant) > http://energenie.com/item.aspx?id=7557=en > I use controllable APC rack outlet for this purpose, they cost almost nothing, like <5$/socket for used APC AP7957 from ebay. --

[coreboot] Out-of spec EC control codes

Hi, while doing LPC examination for keyboard actions on Getac laptop few weeks ago, I noticed that the controlling sequence for backlight step has been put outside of an ACPI spec for no visible reason (therefore it is not possible to control backlight using unmodified ectool, for example).

Re: [coreboot] x86: best approach to debug consumer hardware?

On Sun, Jul 9, 2017 at 2:56 AM, Andrey Korolyov <and...@xdel.ru> wrote: >> >> I'd expect the clockgen to be the culprit too. But this C-state number >> could be a typo and also be the reason for your trouble (though, I'd >> wonder why it works on the T60). This numb

Re: [coreboot] x86: best approach to debug consumer hardware?

On Thu, Jul 6, 2017 at 8:47 PM, Zoran Stojsavljevic wrote: >> The simplest and most obvious explanation turned out to be true, the >> register is encoded as multiples of 16MiB. > > You say (in other words) the following: Coreboot prepares the whole > populated 32

Re: [coreboot] x86: best approach to debug consumer hardware?

> From git logs it looks like configuring the clockgen was needed for the > x60/t60 port for deeper c-states to work. I'd try to dump the clockgen > configuration on smbus with block operations ('i2cdump #smbus 0x69 s') > and configure it using block write operations either in romstage (look > at

Re: [coreboot] x86: best approach to debug consumer hardware?

> > I'd expect the clockgen to be the culprit too. But this C-state number > could be a typo and also be the reason for your trouble (though, I'd > wonder why it works on the T60). This number is used to map ACPI C-state > semantics to the states presented in _CST. ACPI knows three C states and >

Re: [coreboot] x86: best approach to debug consumer hardware?

On Thu, Jul 6, 2017 at 8:20 AM, Zoran Stojsavljevic wrote: > OK, both Andrjusas, > > I am a bit ignorant, and I read beginning of the Coreboot log: > > DIMM 0 side 0 = 1024 MB > DIMM 0 side 1 = 1024 MB > DIMM 2 side 0 = 1024 MB > DIMM 2 side 1 = 1024 MB > tRFC = 43

[coreboot] x86: best approach to debug consumer hardware?

Hi, since I`ve got em100 few days ago, I decided to test it against one of my x86 devices and try to put coreboot on it at once. The selection was Z61m (T2400 CD/i945/82801). After fixing few things in i945 code borrowed from t60, I noticed severe problem when I tried to use SMP kernel, because

Re: [coreboot] x86: best approach to debug consumer hardware?

On Thu, Jul 6, 2017 at 12:27 AM, Nico Huber wrote: > I'd start with examining the coreboot console log. Are there resource > conflicts? Are all APs initialized? Was the microcode updated for all > of them? etc... If you don't have it already, you can grab the log from > your

Re: [coreboot] x86: best approach to debug consumer hardware?

> [1] Platform T2400/i945 -> > http://ark.intel.com/products/27235/Intel-Core-Duo-Processor-T2400-2M-Cache-1_83-GHz-667-MHz-FSB > ... Am I correct? Yup. > [2] What is GEODE in this context? 500 Mhz i486AMD Geode processor (Single > HW threaded, one core, no HT)? Just a remark about how I got

Re: [coreboot] EHCI debug that supports both Linux and Windows as a host PC

On Fri, Aug 4, 2017 at 3:14 PM, Аладышев Константин wrote: > What is the easiest and most stable way to do debug through EHCI USB port > instead of COM port? Is there any EHCI dongles on market that supports both > Linux and Windows as a host PC? > The answer varies

Re: [coreboot] EHCI debug that supports both Linux and Windows as a host PC

On Fri, Aug 4, 2017 at 4:21 PM, Аладышев Константин wrote: > Does a windows driver (for host PC where I want to see coreboot log) exist > for this solution with BeagleBone? If you are asking about bbb connectivity, there is a 'real' ethernet PHY on chip opposed to RPI where

Re: [coreboot] FYI: Reverse Engineering x86 Processor Microcode

> In this paper, we reverse engineer the microcode semantics > and inner workings of its update mechanism of conventional > COTS CPUs on the example of AMD’s K8 and > K10 microarchitectures. > Still wondering what was engineering reasons for these families behind such a practice as non-verified

Re: [coreboot] Recommendation for Flashing Clips / mass order

On Wed, Oct 18, 2017 at 3:35 PM, Peter Stuge wrote: > [799] via coreboot wrote: >> Do you have any recommendations if it makes sense to invest a bit >> more budget and buy a more expensive clip or will the quality be >> the same? >> >> The Pomona 5250 Clip: >>

Re: [coreboot] ast2400 / ast2500

> 4. Using same firmware on x86 and bmc means, what ever infra we develop for > board bring up and ops (as coreboot payload) works on both. > 5. Same thing for secure booting. > While I borrow not much expertise there, these points are applicable at this moment only if you are planning to run

Re: [coreboot] ACPI error booting Windows

On Thu, Apr 26, 2018 at 1:59 AM, Alex Feinman wrote: > I've built a Coreboot image (from the HEAD) for my custom Kaby Lake board. > The build uses Chrome EC and is based on kblrvp3 mainboard configuration. > Linux runs fine, but when I attempt to install Windows 10 (or

[coreboot] Re: Intel Atom C2000 SOC - Do they lack Intel ME?

> investigating a bit with intelmetool and mecleaner non of them could > found any sign for an ME-region in this board.. so i asking myself if > there is no ME/SPS on the intel C2000 socs, what would make them a DAMN > SEXY platform to port coreboot too. > I believe that the Intel FSP (firmware

[coreboot] Re: Extended IvyBridge CPU configuration

> > Do these crashes/freezes look like > https://ticket.coreboot.org/issues/121? Sorry for potential thread hijack, did anyone observed vendor's clock generator setup on these models? I remember seeing exactly the same behavior with z61t when I borrowed clock generator setup from neighbor model,