Re: [coreboot] Using USB keyboard in payloads

2012-11-19 Thread Nico Huber
I'm unable to get the USB keyboard to work in payloads. I'm using it with libpayload, and configured libpayload to enable the USB_HID, USB_OHCI, USB_EHCI, USB_UHCI, USB_XHCI drivers. I call usb_initialize() in the early part of my payload. Calls to usbhid_havechar() just return 0. When

Re: [coreboot] libpayload: Missing inclusion of `libpayload-config.h`

2013-03-27 Thread Nico Huber
Hello Paul, Am 27.03.2013 14:04, schrieb Paul Menzel: Dear coreboot folks, using latest master commit 3cc0d1eb3f611cb7bf0e45d8ccdb0c84f54f54dc Author: David Hendricks dhend...@chromium.org Date: Tue Mar 26 16:28:21 2013 -0700 exynos5250:

Re: [coreboot] libpayload: Missing inclusion of `libpayload-config.h`

2013-03-28 Thread Nico Huber
Dear Paul, Am 28.03.2013 12:37, schrieb Paul Menzel: Am Mittwoch, den 27.03.2013, 20:49 +0100 schrieb Nico Huber: Am 27.03.2013 14:04, schrieb Paul Menzel: Dear coreboot folks, using latest master commit 3cc0d1eb3f611cb7bf0e45d8ccdb0c84f54f54dc Author: David Hendricks

[coreboot] Ivy Bridge desktop support

2013-03-30 Thread Nico Huber
Dear coreboot folks, I'm looking forward to write a port for my Ivy Bridge desktop system based on this board: Intel DH77EB (codenamed Eb Lake, [1]). It comes with the H77 platform controller hub (PCH) and a Winbond W83677HG super I/O chip (build by Nuvoton as NCT6775F, [2]). I'm using it with a

Re: [coreboot] Ivy Bridge desktop support

2013-04-02 Thread Nico Huber
Hello Paul, Am 02.04.2013 11:12, schrieb Paul Menzel: Am Sonntag, den 31.03.2013, 21:10 +0200 schrieb Paul Menzel: Am Samstag, den 30.03.2013, 19:57 +0100 schrieb Nico Huber: I'm looking forward to write a port for my Ivy Bridge desktop system based on this board: Intel DH77EB (codenamed

Re: [coreboot] Trouble with coreboot for Roda RK9

2013-06-25 Thread Nico Huber
Am 25.06.2013 14:07, schrieb Dmitry Bagryanskiy: Hello Dmitry, welcome to the coreboot mailing list. Could you please help me to solve some problems? Laptop: Roda RK9 Socket: mPGA479M The problem is that when loading coreboot, Unsupported FSB clock is written in the debug and the circuit

Re: [coreboot] Trouble with coreboot for Roda RK9

2013-06-26 Thread Nico Huber
Am 25.06.2013 23:08, schrieb Dmitry Bagryanskiy: Hello Dmitry, My processor type is Intel Core 2 Duo P8400, socket mFCPGA479M IIRC, I've seen at least one RK9 with this CPU running coreboot. Looking through your log files, I didn't find anything suspicious. I'll try to check if current upstream

Re: [coreboot] Who sells the Roda RK9 ?

2013-07-02 Thread Nico Huber
likely not what you want, being a 6kg ruggedized notebook. ps: I did the same about the Getac P470 with the same results: nobody seems to sell it. I'd wonder if it's still sold. Nico Thank in advance, ms [1] http://roda-mildef.com/products/rugged-notebooks/rk9/ -- M. Sc. Nico Huber

Re: [coreboot] Trouble with coreboot for Roda RK9

2013-07-02 Thread Nico Huber
coreboot checkout or even a fresh checkout if you did any changes. Nico -- M. Sc. Nico Huber Berater, SINA-Softwareentwicklung Public Sector secunet Security Networks AG Tel.: +49-201-5454-3635, Fax: +49-201-5454-1325 E-Mail: nico.hu...@secunet.com Mergenthalerallee 77, 65760 Eschborn

Re: [coreboot] Trouble with coreboot for Roda RK9

2014-02-13 Thread Nico Huber
on this, but if you like to bisect the problem: I guess, commit 11a7db3 should be a working starting point. Kind regards, Nico -- M. Sc. Nico Huber Berater, SINA-Softwareentwicklung Public Sector secunet Security Networks AG Tel.: +49-201-5454-3635, Fax: +49-201-5454-1325 E-Mail: nico.hu

Re: [coreboot] Trouble with coreboot for Roda RK9 (SOLVED)

2014-02-14 Thread Nico Huber
are doing. Current code sets this to 0x000c0601, bits 16, 17 are reserved and bit 20 should IIRC only help with addresses from 0x610 to 0x61f. Nico -- M. Sc. Nico Huber Berater, SINA-Softwareentwicklung Public Sector secunet Security Networks AG Tel.: +49-201-5454-3635, Fax: +49-201-5454-1325 E-Mail

Re: [coreboot] Trouble with coreboot for Roda RK9 (SOLVED)

2014-02-14 Thread Nico Huber
* ports. Instead there are dedicated bits for enabling decode of serial port ranges. Consult southbridge documentation. There are only dedicated settings for two COM ports. Looks like Dmitry wants to enable a 3rd and 4th port. Nico -- M. Sc. Nico Huber Berater, SINA-Softwareentwicklung Public

Re: [coreboot] Trouble with coreboot for Roda RK9 15 and 17

2014-02-18 Thread Nico Huber
Bagryanskiy. -- M. Sc. Nico Huber Berater, SINA-Softwareentwicklung Public Sector secunet Security Networks AG Tel.: +49-201-5454-3635, Fax: +49-201-5454-1325 E-Mail: nico.hu...@secunet.com Mergenthalerallee 77, 65760 Eschborn, Deutschland www.secunet.com

Re: [coreboot] Bug in your code

2014-04-18 Thread Nico Huber
On 18.04.2014 16:49, ron minnich wrote: Can somebody give me a sanity check? I can't see the error with the macro. I won't say too much here -- just take a look. I'm not convinced the code is wrong. Well, I'm convinced :P Have a closer look at the placement of the space. It was next to the

Re: [coreboot] high-pitched whine on x60/t60

2014-07-22 Thread Nico Huber
Hi folks, I haven't followed the previous discussion on this matter, so one question: Is this a coreboot issue? If this noise doesn't occur with the vendor firmware, has anybody checked if coreboot uses the same power management timing settings? (e.g. C4-TIMING_CNT, see [1], there might be more

Re: [coreboot] Coreboot FILO payload build fails when USB support enabled

2014-10-12 Thread Nico Huber
Hello Vipin, Can you please suggest a solution and let me know why CONFIG_USB is removed from my .config The prefix for libpayload's configurations options changed to CONFIG_LP_, lately. The last commit for FILO (60d45fc) tried to fix it, but seems to have missed some options. So CONFIG_USB is

Re: [coreboot] Coreboot FILO payload build fails when USB support enabled

2014-10-12 Thread Nico Huber
On 12.10.2014 18:21, Vipin Gahlaut wrote: Logs for the problem I am getting repeatedly at run time change on port 1 fullspeed device first get_descriptor(DT_DEV) failed set_address failed That's exactly what I observed on a kontron/986lcd-m (i945) with low- speed devices connected to the

Re: [coreboot] [coreboot-gerrit] Patch merged into coreboot/master: 8414d3c xcompile: always use -march=i686

2014-10-12 Thread Nico Huber
Hi folks, something seems wrong with this one: On 25.08.2014 23:33, ger...@coreboot.org wrote: the following patch was just integrated into master: commit 8414d3c0b407d9afc6a2446dba3ca358da2c7bb6 Author: Aaron Durbin adur...@chromium.org Date: Thu Oct 10 12:44:11 2013 -0500

Re: [coreboot] [coreboot-gerrit] Patch merged into coreboot/master: 8414d3c xcompile: always use -march=i686

2014-10-12 Thread Nico Huber
On 12.10.2014 22:45, Peter Stuge wrote: Nico Huber wrote: something seems wrong with this one: On 25.08.2014 23:33, ger...@coreboot.org wrote: the following patch was just integrated into master: commit 8414d3c0b407d9afc6a2446dba3ca358da2c7bb6 Author: Aaron Durbin adur...@chromium.org Date

[coreboot] Prague meeting: Work on USB debug

2014-10-13 Thread Nico Huber
Hi folks, I had first success with my pomona clip, today. Sadly, the mobo does not have any UART, so I'll finally have to switch to something more advanced. I've a high-speed ftdi usb adapter board that can be used as USB debug device, but this will need some code changes along with some

Re: [coreboot] Prague meeting: Work on USB debug

2014-10-14 Thread Nico Huber
On 14. Oktober 2014 01:26:37 MESZ, Peter Stuge pe...@stuge.se wrote: Nico Huber wrote: I had first success with my pomona clip, today. Sadly, the mobo does not have any UART, What board is it? A Haswell ThinkPad (T440s). so I'll finally have to switch to something more advanced. Is LPC

[coreboot] From wildcat linking to exploring new languages

2015-08-21 Thread Nico Huber
the disclaimer: Supporting the upstreaming of this code may result in further development in Ada (currently I only have simple device drivers in mind). I hereby wash my hands of any damage that may arise from that :P Nico -- M. Sc. Nico Huber Senior Berater SINA-Softwareentwicklung Netzwerk- Client

Re: [coreboot] SPD binaries in coreboot

2015-10-23 Thread Nico Huber
On 23.10.2015 18:32, Martin Roth wrote: >> So, is there a third option that I'm missing? Other opinions? The third option would be a plain text format which is easy to parse but still covers the spec well. > > I'd say that we should store the SPDs as binaries - these are easy to > use

Re: [coreboot] SPD binaries in coreboot

2015-10-23 Thread Nico Huber
Hi all, On 23.10.2015 17:23, Patrick Georgi wrote: > I see essentially two ways out of this, before we can start reducing > duplication across the tree in that area: > [...] Neither of your options tackles the real problem. That is: We have interfaces that use binary SPD data. It's just stupid.

Re: [coreboot] SPD binaries in coreboot

2015-10-23 Thread Nico Huber
On 24.10.2015 00:37, Alex G. wrote: > On 10/23/2015 01:59 PM, Nico Huber wrote: >> Thanks for the support. One remark: I would really prefer serializing >> during runtime > > Why waste runtime cycles (and code space) doing something you can > already do at build time? I

Re: [coreboot] GM45 S3 resume issues

2015-11-12 Thread Nico Huber
On 12.11.2015 04:37, Patrick 'P. J.' McDermott wrote: > On 2015-11-11 16:50, Nico Huber wrote: >> Hi, >> >> On 11.11.2015 00:49, Patrick 'P. J.' McDermott wrote: >>> I've been looking into S3 resume on GM45 mainboards, which often fails >>> in rather in

Re: [coreboot] GM45 S3 resume issues

2015-11-12 Thread Nico Huber
Hi, had a look at your logs: On 11.11.2015 00:49, Patrick 'P. J.' McDermott wrote: > These systems fail to resume in one of the following ways: > > * S3 resume (indicated by the SLP_TYP bit) is detected, SLP_TYP is > cleared, DRAM receive-enable calibration fails with a timing >

Re: [coreboot] GM45 S3 resume issues

2015-11-11 Thread Nico Huber
Hi, On 11.11.2015 00:49, Patrick 'P. J.' McDermott wrote: > I've been looking into S3 resume on GM45 mainboards, which often fails > in rather interesting ways. Well, the S3 support wasn't really tested during GM45 development. Maybe it's just plainly broken. My development system at work

Re: [coreboot] Dell Dimension 8300 reboots when grub2 cbfs module is loaded

2015-11-03 Thread Nico Huber
Hi Andrei, your patch looks good generally, but the check is off by one. It's obvious, we want to have sane checking there. Reading from a random address can cause trouble and 0x is not the only offending address. On x86, the cbfs is mapped right below the 4GiB line. Current machines

Re: [coreboot] From wildcat linking to exploring new languages

2015-08-28 Thread Nico Huber
and such, and of course our own products where the code stems from). We have discussed the licensing and will push this under GPLv2 + later if there are no reasonable concerns. Nico -- M. Sc. Nico Huber Senior Berater SINA-Softwareentwicklung Netzwerk- Client-Sicherheit / Network Client Security

Re: [coreboot] From wildcat linking to exploring new languages

2015-08-28 Thread Nico Huber
and such, and of course our own products where the code stems from). We have discussed the licensing and will push this under GPLv2 + later if there are no reasonable concerns. Nico -- M. Sc. Nico Huber Senior Berater SINA-Softwareentwicklung Netzwerk- Client-Sicherheit / Network Client Security

Re: [coreboot] From wildcat linking to exploring new languages

2015-08-28 Thread Nico Huber
was that libpayload resides in it's own repository. But having simple device drivers in it's own place seems to be a good idea, for me. Anyway, I'll push it next week (I guess) when the code got cleared. Nico ron On Fri, Aug 28, 2015 at 4:55 AM Nico Huber nico.hu...@secunet.com wrote: Am 21.08.2015

Re: [coreboot] From wildcat linking to exploring new languages

2015-08-28 Thread Nico Huber
Am 28.08.2015 17:51, schrieb Patrick Georgi: 2015-08-28 17:35 GMT+02:00 Nico Huber nico.hu...@secunet.com: I don't know if the real problem was that libpayload resides in it's own repository. libpayload still shares a repo with coreboot. There were ideas to separate them, but that never

Re: [coreboot] From wildcat linking to exploring new languages

2015-08-30 Thread Nico Huber
On 29.08.2015 14:09, Peter Stuge wrote: ron minnich wrote: and I still think it belongs in the tree. No way. This is a library of device drivers. It has no place whatsoever as a subdirectory lost somewhere in the already too big coreboot repository. libsparkhw needs to live in its own

Re: [coreboot] From wildcat linking to exploring new languages

2015-08-30 Thread Nico Huber
On 29.08.2015 21:58, ron minnich wrote: If people feel strongly enough about this then we can do an external repo for now. Either way around, we would have to learn how to best integrate SPARK code in coreboot. There would still be some steps to go from linking with an adalib, to SPARK beeing a

Re: [coreboot] Change in coreboot[master]: coreboot_table: don't add CMOS checksum twice.

2015-09-09 Thread Nico Huber
Am 16.04.2015 15:12, schrieb gerrit code review: > From Nico Huber <nic...@gmx.de>: > > Nico Huber has posted comments on this change. > > Change subject: coreboot_table: don't add CMOS checksum twice. > ..

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

2016-06-07 Thread Nico Huber
On 06.06.2016 23:40, Kyösti Mälkki wrote: > On Mon, Jun 6, 2016 at 10:36 PM, ron minnich wrote: >> I'm getting the sense here that reasonably modern CPUs can easily handle the >> 2G hole. From what I've seen, it would not cause trouble for older CPUs >> because they're most

Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

2016-06-07 Thread Nico Huber
Hello Naveed, On 07.06.2016 07:21, Naveed Ghori wrote: > But I should still see 4GB without any patch. Right? no, I'm afraid not. > Windows only see 1.92GB as “Installed Memory (RAM)” in Control Panel->System. This is correct as the 4GiB address space is not only used for RAM but shared with

Re: [coreboot] Discussion about dynamic PCI MMIO size on x86

2016-06-08 Thread Nico Huber
On 07.06.2016 16:40, Patrick Rudolph wrote: > On 2016-06-06 09:58 PM, ron minnich wrote: >> On Mon, Jun 6, 2016 at 12:52 PM Patrick Rudolph >> wrote: >> >>> To summarize: >>> The easy way is to use 2G. >>> The preferred way would be to mimic mrc behaviour and reboot after >>>

Re: [coreboot] Windows only seeing 2GB of 4G (Seabios

2016-06-08 Thread Nico Huber
On 08.06.2016 04:26, Naveed Ghori wrote: > Thanks Nico, > What options should I be looking to tune? 3Gig should be fine as that > is what I have seen in another product. > This depends heavily on the used hardware platform. I don't think all of them have an option in coreboot. But it might be

Re: [coreboot] RFC: coding style: "standard" defines

2016-02-04 Thread Nico Huber
On 04.02.2016 22:25, Patrick Georgi via coreboot wrote: > 2016-02-04 22:22 GMT+01:00 Martin Roth : >> I don't think we need redefinitions of TRUE/FALSE > We have no canonical definitions for TRUE/FALSE right now. > Contributions that use them (for whatever reason) tend to bring

Re: [coreboot] RFC: coding style: "standard" defines

2016-02-08 Thread Nico Huber
On 08.02.2016 12:10, Patrick Georgi via coreboot wrote: > 2016-02-04 10:35 GMT+01:00 Patrick Georgi : >> during the review of some commits that are in the process of being >> upstreamed from Chrome OS, people noticed that chipset drivers like to >> define their own TRUE/FALSE

Re: [coreboot] RFC: coding style: "standard" defines

2016-02-04 Thread Nico Huber
On 04.02.2016 10:35, Patrick Georgi via coreboot wrote: > I think we should seek uniformity here: decide on some style, > recommend it, clean up the tree to match, and help people stay > consistent through lint tests. That's a good idea. > 2. BIT16 vs BIT(16) vs (1 << 16) vs 0x1 > I don't

Re: [coreboot] Regarding offset adjustment for building coreboot.

2016-04-08 Thread Nico Huber
dd [payloads/external/uefi/UEFIPAYLOAD.fd, 886346 bytes (865 >> KB)@0x0]; too big? > This is indicates a 865K image. How is that supposed to fit? you also stripped: fallback/payload 0x1b140payload 769955 I guess he means that a fresh build with a bigger (865KiB instead of 7

Re: [coreboot] Regarding offset adjustment for building coreboot.

2016-04-08 Thread Nico Huber
don't know how to change the offsets. Some might not be chosen arbitrarily at all. But maybe there is another simple option: Did you already try to increase the size of your CBFS (CONFIG_CBFS_SIZE)? It may be as large as the "bios" partition of your flash chip. Hope that helps, Nico --

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

2016-05-01 Thread Nico Huber
On 01.05.2016 21:40, Daniel Kulesz wrote: > Hi again, > > I did some more experiments with the vendor BIOS and made the following > observations: > > - disabling "cpu power management" makes the idle consumption raise to 12,8W Is this 12.8W compared to 7.5W (i.e. with lowest backlight)? > -

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

2016-05-01 Thread Nico Huber
On 01.05.2016 15:30, Daniel Kulesz wrote: > Hi Nico, > >> On 01.05.2016 12:26, Daniel Kulesz via coreboot wrote: >>> Coreboot with idle=poll: 15,8W >>> Coreboot running "stress": 37,2W >> well, this is what I would expect from the specs. >> >>> Vendor BIOS with idle=poll: 15W >>> Vendor BIOS with

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

2016-05-01 Thread Nico Huber
Hi Daniel, On 01.05.2016 12:26, Daniel Kulesz via coreboot wrote: > Coreboot with idle=poll: 15,8W > Coreboot running "stress": 37,2W well, this is what I would expect from the specs. > Vendor BIOS with idle=poll: 15W > Vendor BIOS with intel_pstate=disabled: 10W > Vendor BIOS running "stress":

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

2016-05-01 Thread Nico Huber
Hi Daniel, first thing: We never got to the deepest processor sleep states (C3, C4) when we originally ported coreboot for the GM45 chipset. But we didn't see a difference in power consumption back then on the Roda/RK9. On 01.05.2016 00:55, Daniel Kulesz via coreboot wrote: > No tweaking with

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

2016-05-02 Thread Nico Huber
Hi Daniel, On 03.05.2016 00:47, Daniel Kulesz via coreboot wrote: > Hi all, > > On Mon, 2 May 2016 13:16:15 +0200 > Nico Huber <nico.hu...@secunet.com> wrote: >> Regarding C3/C4 support, AFAIK, we implemented it fully but it just >> didn't work on the system

Re: [coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS

2016-05-02 Thread Nico Huber
x02, 300, { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x20, 0 } }, for C3 or { /* acpi C3 / cpu C4 */ 3, 0x02, 300, { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 } }, for C4. You can not have all of them, as ACPI

Re: [coreboot] w83627 uart port is not workable with coreboot in linux

2016-07-25 Thread Nico Huber
Hi Cheng, On 25.07.2016 04:33, cheng yichen wrote: > Hi all > > After i follow kontron/ktqm77 setting. I can't solve the issue. > I try to change iqr(for com1) to 5 or 6. but system can't print linux > message and minicom is not workable. Can you confirm that you see the full coreboot log on

Re: [coreboot] MMIO UART driver on OS

2016-07-31 Thread Nico Huber
Hi, On 31.07.2016 17:07, Zheng Bao wrote: > Hi, All, > > I want to add support MMIO UART support on OS. > > I checked the file pnp_uart.asl. > > For IO UART, a device with EisaId("PNP0501") is added into DSDT, the windows > can detect the COM port in device manager. > > I am wondering if

Re: [coreboot] FS2 for anyone who can use it

2016-08-10 Thread Nico Huber
On 10.08.2016 10:35, ron minnich wrote: > ah, no, those are not it. Sorry. I'll get you some pictures. Maybe [1] helps. It's my best FS2 shot for something coreboot related. Nico [1] http://web.archive.org/web/20080915062711/http://www.fs2.com/ > > ron > > > > On Wed, Aug 10, 2016 at 12:42

Re: [coreboot] w83627 uart port is not workable with coreboot in linux

2016-07-22 Thread Nico Huber
Hi Cheng, On 22.07.2016 12:14, cheng yichen wrote: > Hi all > > My platform is braswell SOC with W83627dhg superIO. In post stage I can get > debug message over w83627 uart1(3f8/irq4). but after boot to linux, uart > port is not woarkable. I test the function by minicom but I can't receive > and

Re: [coreboot] PECI temperature in lm-sensors

2017-01-23 Thread Nico Huber
On 23.01.2017 15:17, Аладышев Константин wrote: > Does someone have any experience with enabling PECI monitoring on nuvoton > SuperIOs ? > > I'm trying to enable it on board with Haswell+Lynxpoint CPU and NCT6776 > SuperIO. > > But all I see in lm-sensors output for now is zero temperature for

Re: [coreboot] Compiling coreboot with libgfxinit

2017-01-24 Thread Nico Huber
Hi Mihail, On 24.01.2017 11:35, Mihail Tommonen wrote: > Hello Everyone, > > My intention is to get libgfxinit to work with Lenovo X230, but first > I'm trying to get it compiled for KONTRON KTQM77 as its seems to be > only board atm that has feature enabled in configs. > > Unfortunately I get

Re: [coreboot] Does the 62xx Series Opteron work *securely* without microcode?

2017-01-26 Thread Nico Huber
On 26.01.2017 12:41, Sam Kuper wrote: > On 25/01/2017, ron minnich wrote: >> If you have a machine with microcode updates, you >> should load the updates. I have never understood the objections to >> microcode blobs. If you accept the microcode that's on the machine already,

Re: [coreboot] Proposal for new "Commenting" wiki text (was: [RFC] Deciding on style for multi-line comments)

2017-01-28 Thread Nico Huber
Hi folks, sorry to revive this old, stale topic. I got stalled by a request to ensure the comment style with a script. Now, that I had a look at checkpatch.pl, I don't think this could be done easily without risking many false positives. So I'm again asking to commit my proposal below. I've

Re: [coreboot] Is Xeon E5 supported?

2017-02-19 Thread Nico Huber
Hi Zheng, On 19.02.2017 13:24, Zheng Bao wrote: > Hi, All, > > We are evaluating a resolution, which requires more than four x8 PCIE lane. > > We assume Intel Xeon E5 can meet this requirement. > > > I am not quite familar with Intel platform. I am wondering if coreboot > supports Xeon E5.

Re: [coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building

2017-02-22 Thread Nico Huber
On 22.02.2017 08:12, Zoran Stojsavljevic wrote: > Hello to community, > > I finally, after 3 days of additional very hard struggle, found out why I > have (while I am in the last stage of building CBFS) nonsense while > building APL-I Coreboot coreboot.rom?! > > Please, read carefully this

Re: [coreboot] Dont filter supported CPUs on a mainboard by the CPUID

2017-02-23 Thread Nico Huber
On 23.02.2017 00:07, i1w5d7gf38...@tutanota.com wrote: > There is a Filter to stop booting when the CPUID is not in a list of > supported CPUs. This filter does not make sense in the real world usage. It's not a filter. It's a measure to know which code to run for which CPU. Please dig a little

Re: [coreboot] T520 2630QM 16GB DIMM

2017-02-23 Thread Nico Huber
On 23.02.2017 01:33, i1w5d7gf38...@tutanota.com wrote: > It would be really great if you could test out a Core i7-3840QM in the > G2 socket of the Thinkpad T520. Its the best ivy bridge with 45W TDP and > the Core i7-3840QM officialy support 32GB of RAM. Only with 8 ranks of 4GiB. That would be

Re: [coreboot] Saving truncated preram CBMEM messages

2017-02-12 Thread Nico Huber
On 12.02.2017 00:34, Paul Menzel wrote: > Dear Nico, > > > Am Sonntag, den 08.01.2017, 15:23 +0100 schrieb Nico Huber: >> On 08.01.2017 14:38, Paul Menzel via coreboot wrote: > >>> looking at the coreboot CBMEM console messages board status repository, >>>

Re: [coreboot] Add coreboot storage driver

2017-02-14 Thread Nico Huber
On 14.02.2017 18:56, ron minnich wrote: > At what point is ramstage a kernel? I think at the point we add file > systems or preemptive scheduling. We're getting dangerously close. If we > really start to cross that boundary, it's time to rethink the ramstage in > my view. It's not a good

Re: [coreboot] Add coreboot storage driver

2017-02-13 Thread Nico Huber
On 13.02.2017 08:19, Andrey Petrov wrote: > For example Apollolake is struggling to finish firmware boot with all > the whistles and bells (vboot, tpm and our friendly, ever-vigilant TXE) > under one second. Can you provide exhaustive figures, which part of this system's boot process takes how

Re: [coreboot] !! Resource didn't fit !! / Porting coreboot to the Supermicro X9SPU-F mainboard

2017-01-15 Thread Nico Huber
Hi Nicolai, On 15.01.2017 15:28, Renze Nicolai wrote: > Hello everyone, > > A small update: The serial port (finally) works! (apparently a kconfig > entry was needed for the superio code to actually enable the serial > port when it is enabled in code) > > However the actual problem still

Re: [coreboot] Using as default external monitor for booting in x230

2017-01-15 Thread Nico Huber
Hi, On 15.01.2017 01:12, Car.cuevas via coreboot wrote: > Hi, > > well actually, I will have to use Seabios as payload, since I may be > needing sometimes to boot to the windows which came pre-installed, but > 99% of times I am using Debian. And actually, my problem is about > using as default

[coreboot] Proposal for new "Commenting" wiki text (was: [RFC] Deciding on style for multi-line comments)

2016-09-04 Thread Nico Huber
Hi folks, I think we kind of agreed that the wiki text about "Commenting" should change. So here is my proposal, feel free to edit, add something or just ack or complain about it. > == Commenting == > > Comments are good, but there is also a danger of over-commenting. NEVER > try to explain HOW

Re: [coreboot] Proposal for new "Commenting" wiki text (was: [RFC] Deciding on style for multi-line comments)

2016-09-07 Thread Nico Huber
On 04.09.2016 21:36, Martin Roth wrote: > Hey Nico, > Thanks for writing that up and not just letting this drop with no > resolution and action. > > To anyone just coming in on the discussion, here's what we're talking about > changing: > https://www.coreboot.org/Coding_Style#Commenting > > >

Re: [coreboot] Proposal for new "Commenting" wiki text

2016-09-07 Thread Nico Huber
ay 'increment i', but as the author, I >> think it's >> helpful." >> 4) I think this would be the only "the author has the final say" >> policy - what >> happens when someone rewrites the comment in a following patch? Who >> is the author? >>

Re: [coreboot] Proposal for new "Commenting" wiki text (was: [RFC] Deciding on style for multi-line comments)

2016-09-07 Thread Nico Huber
On 06.09.2016 00:04, Vadim Bendebury wrote: > On Sun, Sep 4, 2016 at 7:42 AM, Nico Huber <nic...@gmx.de> wrote: > >> Hi folks, >> >> I think we kind of agreed that the wiki text about "Commenting" should >> change. So here is my proposal, f

Re: [coreboot] anyone use coreboot on Lenovo T520?

2016-09-08 Thread Nico Huber
Hi Iru, On 08.09.2016 13:25, Iru Cai wrote: > Hi Patrick, > > On Wed, Sep 07, 2016 at 05:36:45PM +0200, Patrick Rudolph wrote: >> On Wed, 7 Sep 2016 21:15:05 +0800 >> Iru Cai wrote: >> >> Hi Iru, >> I've got a T520 with soldered pin header as in the referenced wiki page,

Re: [coreboot] Getting an WXGA+ LED MVA panel to work on T400: "G141C1-L01"

2016-09-25 Thread Nico Huber
Hi Merlin, On 24.09.2016 21:25, Merlin Büge wrote: > Hello everyone! > > > This is my first post to this mailing list :) > welcome to coreboot ;) I didn't have the time for a closer look at your logs. But there is one thing coreboot does definitely wrong: The clock configuration. You can see it

Re: [coreboot] [RFC] Deciding on style for multi-line comments

2016-08-26 Thread Nico Huber
On 24.08.2016 09:08, Paul Menzel via coreboot wrote: > The coding style currently demands the following style of multi-line > comments [1]. That's not true. > >> The preferred style for long (multi-line) comments is: See, it just declares what is _preferred_. Nico > > [1]

Re: [coreboot] [RFC] Deciding on style for multi-line comments

2016-08-26 Thread Nico Huber
On 26.08.2016 17:56, Vadim Bendebury wrote: > I actually tend to agree with Julius that it does not make sense to waste 4 > lines for a two line comment. So, ideally the tool should be enforcing the > verbose style for comments longer than say 2 lines. Well, I too prefer the concise style for

Re: [coreboot] grub as payload: Where to put the grub.cfg?

2016-11-09 Thread Nico Huber
Hi Philipp, On 09.11.2016 09:46, Philipp Stanner wrote: > Hi, > > I'm currently busy making cb+grub running. While I can boot successfully > (qemu) using the grub-shell I of course want to automatize this process. > > But how and where do I have to put the grub.cfg file? The wiki doesn't >

Re: [coreboot] Patch: support for the Lenovo Thinkpad W520

2016-11-06 Thread Nico Huber
On 06.11.2016 15:21, Kyösti Mälkki wrote: > On Sun, Nov 6, 2016 at 10:33 AM, Charlotte Plusplus < > pluspluscharlo...@gmail.com> wrote: > >> Hello >> >> Also, can I please ask for some help on USBDEBUG? I have a FT232R >> cable and enabled CONFIG_USBDEBUG_DONGLE_FTDI_FT232H. But I receive >>

Re: [coreboot] Patch: support for the Lenovo Thinkpad W520

2016-11-06 Thread Nico Huber
Hi, On 06.11.2016 11:25, Patrick Rudolph wrote: > Am 06.11.2016 um 09:33 schrieb Charlotte Plusplus: >> Also, in romstage I am not sure of : >> /* Disable unused devices (board specific) */ >> RCBA32(FD) = 0x1ee51fe3; > You can dump the value stock lenovo bios sets at boot using

Re: [coreboot] It appears the build process still uses unverified http wget sources

2016-11-06 Thread Nico Huber
On 06.11.2016 22:44, taii...@gmx.com wrote: > It is 2016 not 2001 and MITM's are a regular thing so this is a serious > issue. Yes, YOU haven't fixed that yet. -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] It appears the build process still uses unverified http wget sources

2016-11-06 Thread Nico Huber
rge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2; > > MAKE_ARCHIVE="https://mirrors.kernel.org/gnu/make/make-${MAKE_VERSION}.tar.bz2; > > > On 11/06/2016 05:02 PM, Nico Huber wrote: > >> On 06.11.2016 22:44, taii...@gmx.com wrote: >>> It is 2016 not 2001 and

Re: [coreboot] grub as payload: Where to put the grub.cfg?

2016-11-09 Thread Nico Huber
hell to start an OS from an > external drive - in an emergency for example, correct? You can also load SeaBIOS from GRUB, I suppose. Nico > > Am 09.11.2016 um 10:19 schrieb Nico Huber: >> Hi Philipp, >> >> On 09.11.2016 09:46, Philipp Stanner wrote: >>> Hi, >>

Re: [coreboot] Patch: support for the Lenovo Thinkpad W520

2016-11-09 Thread Nico Huber
On 07.11.2016 20:20, Charlotte Plusplus wrote: > On 11/6/16, Patrick Rudolph wrote: >> Am 06.11.2016 um 09:33 schrieb Charlotte Plusplus: >>> I am new to coreboot. I could try to add the missing power management >>> states. But can I please ask for pointers and suggestions?

Re: [coreboot] More details about ram issues

2016-11-11 Thread Nico Huber
Hi Charlotte, On 11.11.2016 08:14, Charlotte Plusplus wrote: > So I did many more tests today (more than 6h, and flashing around 30 > times), with SPD settings hardcoded into raminit, and without the mrc cache > interfering. thanks for the analysis and summing this up. > > TLDR: coreboot tries

Re: [coreboot] Attempt to porting coreboot to Gigabyte ga-945gcm-s2l

2016-10-10 Thread Nico Huber
Hi Arthur, On 09.10.2016 18:50, Arthur Heymans wrote: > Hi > > I'm trying to port coreboot to the gigabyte ga-945gcm-s2l, which has a > 945gc northbridge, a ich7 southbridge and a ite it8718f sio. I'm trying > all this with a 1067fsb cpu, so in that last aspect there is no > precedent in

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Nico Huber
Hi Rick, from your messages on IRC, I guess you almost got it. You have to select SOUTHBRIDGE_INTEL_I82801GX in your mainboard's Kconfig. Just do a `git grep select\ SOUTHBRIDGE_INTEL_I82801GX` and you'll find where it's set for other boards. The correct files should then be added by Makefiles.

Re: [coreboot] southbridge/intel/i82801gx/i82801gx.h

2016-10-15 Thread Nico Huber
Hi, On 15.10.2016 13:26, Antonius Riko wrote: > I closed the patch > > //#include > //#include > //#include > > and I got error : > > bianchi@ubuntu:~/coreboot$ make > GENgenerated/bootblock.ld > CP bootblock/arch/x86/bootblock.ld > LINK

Re: [coreboot] Virtualization Support X220

2016-10-22 Thread Nico Huber
On 22.10.2016 09:15, Philipp Stanner wrote: > Is it possible to activate virtualization in the CPU somewhere? Yes, look under "Chipset" in the configuration, it's "Enable VMX for virtualization" (CONFIG_ENABLE_VMX). Nico -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Noob-questions

2016-10-20 Thread Nico Huber
Hi Philipp, On 20.10.2016 16:50, Philipp Stanner wrote: > Hi cb-community, > > as everyone who owns a computer can subscribe to the list and there is > no coreboot-forum, I presume that I'm allowed to ask a few primitive > questions about the topic :) sure. > > 1. Coreboot+Payload are only

[coreboot] Rettungsboot

2016-11-26 Thread Nico Huber
Hey coreboot folks, here's something that's bugging me for a long time: Our lack of an out- of-the-box booting experience. All our payloads that don't implement legacy boot facilities (i.e. BIOS, UEFI), only work in the usual case, to boot an installed OS that's con- figured to work with that

Re: [coreboot] xHCI support for x86

2016-11-23 Thread Nico Huber
Hi, On 23.11.2016 11:09, Pitrolle Jean-Jacques wrote: > Hello *, > I try to integrate coreboot *libpayload usb stack* in a custom binary > for x86. > I already succeed integration of *ehci* for *qemu* and *core 2 duo* > platforms. > > But things seems to be not so easy for *xhci*. > When I try

Re: [coreboot] native video init question

2016-11-24 Thread Nico Huber
Hi, On 20.11.2016 21:29, ron minnich wrote: > I also wonder if you could use the code Nico put in for the graphics init. > I have no idea if it's possible, Nico could tell us. But that code looks > really thorough and might work better. I suppose, it (libgfxinit) would just work (if you get it

Re: [coreboot] Rettungsboot

2016-11-28 Thread Nico Huber
On 28.11.2016 22:38, ron minnich wrote: > I'm also ok with text protobufs. My only request is that we do not use > binary blobs or XML. Interesting, I think almost everyone would agree to never use XML for anything ;) I've been looking at protobufs, the text-representation looks nice. I like it

Re: [coreboot] Rettungsboot

2016-11-28 Thread Nico Huber
On 28.11.2016 20:26, David Hendricks via coreboot wrote: > On Sun, Nov 27, 2016 at 8:28 PM, ron minnich wrote: > >> yeah, david and nico both make very good points. I like the idea of JSON >> file, and further we're working on a Go program >> on the u-root project that would

Re: [coreboot] [RFC] Setting C99 by default

2016-11-28 Thread Nico Huber
On 27.11.2016 23:07, Paul Menzel via coreboot wrote: > Dear coreboot folks, > > > Using GCC 4.9.2 coreboot fails to build for certain boards, whose code > uses ‘for’ loop initial declarations. > > ``` > $ gcc --version > gcc (Debian 4.9.2-10) 4.9.2 > […] > $ make # lenovo/x60 with native

Re: [coreboot] [RFC] Explicitly use C11

2016-11-28 Thread Nico Huber
On 29.11.2016 00:23, Alexander Couzens wrote: > I like the idea of using C11. I would be looking forward to that. Nico -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Rettungsboot

2016-11-26 Thread Nico Huber
On 26.11.2016 19:18, Igor Skochinsky wrote: > Hello Nico, > > Saturday, November 26, 2016, 6:42:40 PM, you wrote: > > NH> Hey coreboot folks, > NH> here's something that's bugging me for a long time: Our lack of an out- > NH> of-the-box booting experience. > > NH> All our payloads that don't

Re: [coreboot] native video init question

2016-11-16 Thread Nico Huber
On 16.11.2016 06:08, Charlotte Plusplus wrote: > Hello > > On Tue, Nov 15, 2016 at 6:46 PM, Nico Huber <nic...@gmx.de> wrote: > >> I've seen a garbled image, too, lately. When I built with native >> raminit by chance but with a completely different gfx init cod

Re: [coreboot] X220 Wifi Suspend

2016-11-18 Thread Nico Huber
Hi, On 18.11.2016 18:08, Tyler Cipriani wrote: > I recently flashed my Lenovo ThinkPad X220 with Coreboot and a SeaBIOS > payload. I made an attempt to document the whole process[0]. > > Initially, everything seemed to work fine. I was able to boot to SeaBIOS > which handed off to a Debian

Re: [coreboot] More details about ram issues

2016-11-12 Thread Nico Huber
On 12.11.2016 05:00, Charlotte Plusplus wrote: > Hello > > On Fri, Nov 11, 2016 at 5:37 PM, Nico Huber <nic...@gmx.de> wrote: > >>> The W520 does only have 1.5V DDR voltage. If it's stable with vendor >>> bios, it's not a DDR voltage problem at all. >

  1   2   3   4   5   6   >