Re: [coreboot] Baytrail FSP Gold3

Yes, it requires a couple of coreboot updates. Basically the changes is in UPD_DATA_REGION structure to add some elements to configure platform via FSP. Which platform are you working on, is it a memory-down or memory module. Sincerely, York -Original Message- From: coreboot

Re: [coreboot] Baytrail FSP Gold3

: Wednesday, November 05, 2014 8:09 AM To: coreboot@coreboot.org Cc: Yang, York Subject: Re: [coreboot] Baytrail FSP Gold3 York, We have BayleyBay and our own Baytrail I B3 based system. Both of them have memory module, no memory-down. Are there any code examples for updating the UPD_DATA_REGION

Re: [coreboot] Can I upstream an UEFI payload binary for MinnowMax board project

. I will share this with inside our team. Thanks, York -Original Message- From: Patrick Georgi [mailto:patr...@georgi-clan.de] Sent: Wednesday, February 04, 2015 6:22 AM To: Yang, York Cc: coreboot@coreboot.org Subject: Re: [coreboot] Can I upstream an UEFI payload binary for MinnowMax

Re: [coreboot] Can I upstream an UEFI payload binary for MinnowMax board project

another solution and make it happen as soon as possible. Github is a very good suggestion. Thank you very much Patrick. York -Original Message- From: Patrick Georgi [mailto:patr...@georgi-clan.de] Sent: Wednesday, February 04, 2015 11:55 AM To: Yang, York Cc: coreboot@coreboot.org

[coreboot] Can I upstream an UEFI payload binary for MinnowMax board project

Hello, Can I upstream an UEFI payload binary for MinnowMax board project? The reason is we want to reduce the effort that coreboot user spends to build one. UEFI payload contains two component, 1) is EDK2 infrastructure in tianocore.org, and 2) coreboot library and package in

Re: [coreboot] No video output with Bay Trail

Did you use the latest code and Baytrail Gold3 FSP? I can see VGA output on Intel Bayley Bay board just selecting platform right and enable configure defaults for Intel FSP and gives all binary (FSP, VBIOS, microcode) correct path. Do you have serial debug message dump? It can help to

Re: [coreboot] Gerrit access rules

That's great. Is reviewers also capable of merging a patch to master? Or requires some role else? Thanks, York -Original Message- From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Patrick Georgi via coreboot Sent: Thursday, April 16, 2015 9:46 AM To:

Re: [coreboot] coreboot 4.4 release coming soon

Hi, I verified the mainboard Intel camelbackmountain_fsp with commit 831d65d0ba68be630e3c323e24e2be071456a9e8. I didn't see issue to boot to Fedora 21 and Windows 7, so it should be good for the upcoming release. Thanks, York -Original Message- From: coreboot

Re: [coreboot] coreboot convention update

Just want to confirm, will whole event happen in Google SF office? Thanks, York From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of ron minnich Sent: Tuesday, April 19, 2016 10:29 AM To: coreboot Subject: [coreboot] coreboot convention update The coreboot

Re: [coreboot] Bring up Intel Camelback Mountain Board with coreboot+FSP failed

The CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER need to be set in order to find the microcode from cbfs. Thanks, York From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Zoran Stojsavljevic Sent: Monday, July 04, 2016 2:33 PM To: Zeh, Werner Cc: 詹皓鈞

Re: [coreboot] SMI handler for fsp_broadwell_de

Fsp_broadwell_de do not implement the SMI support, but you may refer to soc/Broadwell as both are Intel architecture chipset. The SMI support can be done purely in coreboot, but need to touch FSP. / YoRK From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Watzlavick, Robert L

Re: [coreboot] [Broadwell-DE] camelbackmountain_fsp project hang 7a/95

>From the log, it looks like hang in FSP. What version of FSP did you use. >Are you using U-0 stepping CPU? You may want to enable the "Configure defaults for the Intel FSP package" in menuconfig\Mainboard menu. / YoRK From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of