[coreboot] Failed flash, flashrom emergency help needed on ICH7

2009-05-06 Thread Ali Nadalizadeh
I tried the latest svn version (6 May 09) of flashrom and unlike older
versions
didn't get a warning on my chipset. flashrom reads my chip successfully and
outputs a fine Phoenix bios. After writing a new image into the chip
I found that writer is not fully functional and reading the chip again
results in an image that is neither original one nor the new image.
then I tried erase functionality and it resulted in some 0xFF and some
unchanged bytes
in the chip. Currently writing either images doesn't change the chip
and it remains in mostly 0xFF bytes.

Here are the flashrom detection info :

a...@velocity:~/tmp/f$ sudo ./flashrom/flashrom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset Intel ICH7M, enabling flash write... OK.
Found chip SST SST25VF080B (1024 KB) at physical address 0xfff0.
No operations were specified.

verbose output at http://coreboot.pastebin.com/m604f01b6

history of my commands : http://coreboot.pastebin.com/m5c3c2372

Original Rom : http://filebin.ca/mhtqhm/mybios.rom

lspci -vv output attached.

I try to keep my Lenovo 3000 up and running and waiting for helps. :)

I'm also online on #coreboot as nadalizadeh

Thanks
Ali Nadalizadeh
00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 
945GT Express Memory Controller Hub (rev 03)
Subsystem: Lenovo Device 2082
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast TAbort- TAbort- 
MAbort+ SERR- PERR- INTx-
Latency: 0
Capabilities: access denied
Kernel driver in use: agpgart-intel
Kernel modules: intel-agp

00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 
943/940GML Express Integrated Graphics Controller (rev 03)
Subsystem: Lenovo Device 2083
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast TAbort- TAbort- 
MAbort- SERR- PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 16
Region 0: Memory at d810 (32-bit, non-prefetchable) [size=512K]
Region 1: I/O ports at 1800 [size=8]
Region 2: Memory at c000 (32-bit, prefetchable) [size=256M]
Region 3: Memory at d820 (32-bit, non-prefetchable) [size=256K]
Capabilities: access denied
Kernel modules: intelfb

00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML 
Express Integrated Graphics Controller (rev 03)
Subsystem: Lenovo Device 2083
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast TAbort- TAbort- 
MAbort- SERR- PERR- INTx-
Latency: 0
Region 0: Memory at d818 (32-bit, non-prefetchable) [size=512K]
Capabilities: access denied

00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition 
Audio Controller (rev 02)
Subsystem: Lenovo Device 2085
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR+ FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast TAbort- TAbort- 
MAbort- SERR- PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 22
Region 0: Memory at d824 (64-bit, non-prefetchable) [size=16K]
Capabilities: access denied
Kernel driver in use: HDA Intel
Kernel modules: snd-hda-intel

00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 
(rev 02)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast TAbort- TAbort- 
MAbort- SERR- PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Bus: primary=00, secondary=02, subordinate=03, sec-latency=0
I/O behind bridge: 2000-2fff
Memory behind bridge: d400-d5ff
Prefetchable memory behind bridge: d000-d1ff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast TAbort- TAbort- 
MAbort+ SERR- PERR-
BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: access denied
Kernel driver in use: pcieport-driver
Kernel modules: shpchp

00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 3 
(rev 02)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast TAbort- TAbort- 
MAbort- SERR- PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Bus: primary=00, secondary=04, subordinate=05, sec-latency=0

Re: [coreboot] Failed flash, flashrom emergency help needed on ICH7

2009-05-06 Thread Rudolf Marek
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

Hmm I checked the orig bios image for any special handling and there is none.
Even it seems that EC has its own flash somewhere else. (this is good)

Perhaps there are some locks in chip itself? Any expert here on that?
Can we read the status reg from the chip? The WP# of the chip seems just to
enable/disable modifications to the to the BP bits.

I suspect the part flashing does not work well. There seems to  be no obstacles
elsewhere.

Can you post here lspci -xxx

Rudolf

-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iEYEARECAAYFAkoB6iQACgkQ3J9wPJqZRNUwgACfZkN1B45fPlmQ0jV0NdMtOvVC
0P4AoIA6tVBC/XzOdleoBL7amNpRpIHJ
=RWFH
-END PGP SIGNATURE-

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Re: [coreboot] Failed flash, flashrom emergency help needed on ICH7

2009-05-06 Thread Ali Nadalizadeh
lspci -xxx output attached

On Thu, May 7, 2009 at 12:21 AM, Rudolf Marek r.ma...@assembler.cz wrote:

 -BEGIN PGP SIGNED MESSAGE-
 Hash: SHA1

 Hmm I checked the orig bios image for any special handling and there is
 none.
 Even it seems that EC has its own flash somewhere else. (this is good)

 Perhaps there are some locks in chip itself? Any expert here on that?
 Can we read the status reg from the chip? The WP# of the chip seems just to
 enable/disable modifications to the to the BP bits.

 I suspect the part flashing does not work well. There seems to  be no
 obstacles
 elsewhere.

 Can you post here lspci -xxx

 Rudolf

 -BEGIN PGP SIGNATURE-
 Version: GnuPG v1.4.9 (GNU/Linux)
 Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

 iEYEARECAAYFAkoB6iQACgkQ3J9wPJqZRNUwgACfZkN1B45fPlmQ0jV0NdMtOvVC
 0P4AoIA6tVBC/XzOdleoBL7amNpRpIHJ
 =RWFH
 -END PGP SIGNATURE-



--
Ali Nadalizadeh
00:00.0 Host bridge: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 
945GT Express Memory Controller Hub (rev 03)
00: 86 80 a0 27 06 01 90 20 03 00 00 06 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 82 20
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 
943/940GML Express Integrated Graphics Controller (rev 03)
00: 86 80 a2 27 07 00 90 00 03 00 00 03 00 00 80 00
10: 00 00 10 d8 01 18 00 00 08 00 00 c0 00 00 20 d8
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 83 20
30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00

00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML 
Express Integrated Graphics Controller (rev 03)
00: 86 80 a6 27 07 00 90 00 03 00 80 03 00 00 80 00
10: 00 00 18 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 83 20
30: 00 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00

00:1b.0 Audio device: Intel Corporation 82801G (ICH7 Family) High Definition 
Audio Controller (rev 02)
00: 86 80 d8 27 06 01 10 00 02 00 03 04 10 00 00 00
10: 04 00 24 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 85 20
30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00

00:1c.0 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 1 
(rev 02)
00: 86 80 d0 27 07 04 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 02 03 00 20 20 00 20
20: 00 d4 f0 d5 01 d0 f1 d1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 04 00

00:1c.2 PCI bridge: Intel Corporation 82801G (ICH7 Family) PCI Express Port 3 
(rev 02)
00: 86 80 d4 27 07 05 10 00 02 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 04 05 00 30 30 00 20
20: 00 d6 f0 d7 01 d2 f1 d3 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 03 03 04 00

00:1d.0 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI 
Controller #1 (rev 02)
00: 86 80 c8 27 05 00 80 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 18 00 00 00 00 00 00 00 00 00 00 aa 17 8a 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 05 01 00 00

00:1d.1 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI 
Controller #2 (rev 02)
00: 86 80 c9 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 18 00 00 00 00 00 00 00 00 00 00 aa 17 8b 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00

00:1d.2 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI 
Controller #3 (rev 02)
00: 86 80 ca 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 61 18 00 00 00 00 00 00 00 00 00 00 aa 17 8c 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 03 03 00 00

00:1d.3 USB Controller: Intel Corporation 82801G (ICH7 Family) USB UHCI 
Controller #4 (rev 02)
00: 86 80 cb 27 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 81 18 00 00 00 00 00 00 00 00 00 00 aa 17 8d 20
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 04 00 00

00:1d.7 USB Controller: Intel Corporation 82801G (ICH7 Family) USB2 EHCI 
Controller (rev 02)
00: 86 80 cc 27 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 40 44 d8 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 8e 20
30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 00 00

00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev e2)
00: 86 80 48 24 07 01 10 00 e2 01 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 0a 0a 20 40 40 80 22
20: 00 d8 00 d8 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00

00:1f.0 ISA bridge: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge 
(rev 02)
00: 86 80 b9 27 07 01 10 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 90 20
30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00

00:1f.1 IDE interface: Intel Corporation 82801G (ICH7 

Re: [coreboot] Failed flash, flashrom emergency help needed on ICH7

2009-05-06 Thread Peter Stuge
Ali Nadalizadeh wrote:
 I'm also online on #coreboot as nadalizadeh

Some analysis after Ali worked with Carl-Daniel and me to debug this.

The chip needs a write enable command to set it's write enable latch
before each erase or write command.

flashrom sends this as a separate command, but for software sequenced
ICH SPI that doesn't work, it needs to go into the ICH PREOP register
and not be sent as an individual command.

Because this fails when trying to send an erase command, chip erase
aborts. Ignoring that write enable error allows the erase to
continue, and succeed.

This chip doesn't support writes of more than one byte at a time
using the 02 command, but the flashrom ICH SPI driver (and maybe
others) assumes that all chips support more data in one go. Many do.

Ali had to go, and we have to rest a little, right now the machine is
running AAI programming, writing two bytes at a time.

If that doesn't work either, the next step is to try the 02 byte
program command but actually send only a single byte at a time.
(force maxdata=1 somewhere suitable)

More updates this afternoon. I think it'll work in the end.


//Peter

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