Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
Hi Kyösti, I will try to boot again with 6276+6238 with the current build and I will inform the result. Regards, - Eli On 03/05/18 20:07, Kyösti Mälkki wrote: > On Thu, May 3, 2018 at 8:57 PM, Elisenda Cuadros wrote: >> Finally I acquired another 6276 CPU (it was the fastest and cheapest >> option). >> >> It works perfect. >> > Maybe not related, but KGPE-D16 was affected by a regression [1] on > SMP init. That was present on master from Aug 2017 to Apr 2018. > > [1] https://review.coreboot.org/c/coreboot/+/25874 > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
On Thu, May 3, 2018 at 8:57 PM, Elisenda Cuadros wrote: > Finally I acquired another 6276 CPU (it was the fastest and cheapest > option). > > It works perfect. > Maybe not related, but KGPE-D16 was affected by a regression [1] on SMP init. That was present on master from Aug 2017 to Apr 2018. [1] https://review.coreboot.org/c/coreboot/+/25874 -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
Finally I acquired another 6276 CPU (it was the fastest and cheapest option). It works perfect. If I can try (in the future) another different 16-core CPU, I will report the result. Thank you for you kind support. Regards, - Eli On 11/04/18 21:30, Timothy Pearson wrote: > This may be a general coreboot limitation at the moment. The > compatibility sections for mixed CPUs in the BKDG are more concerned > with total power delivery and proper P-state setup than anything else. > > If I recall correctly, coreboot assumes both CPUs have the same core > count when setting up APICs and such. There are a number of places that > would need to be modified to remove this assumption; it's a leftover > from the original K8 code and would take some significant work to fix. > This also needs to be verified as I am going from memory here from a > couple of years ago. > > On 04/11/2018 02:12 PM, Elisenda Cuadros wrote: > > Thank you for your reply Timothy. > > > Vendor Bios doesn't print any special message regarding this. > > > In fact it shows a total of 28 cores (16+12). > > > I thought mixing CPUs from same families was supported. > > > Regards, > > > - Eli > > > On 11/04/18 20:44, Timothy Pearson wrote: > >> I don't know if coreboot has support for differing CPUs in the same > >> mainboard; it's not something I can recall testing at any point. > >> > >> The failure is occurring far before memory initialization, in CAR, in > >> core setup. I'd guess it has something to do with the two CPUs you > have > >> installed having different core counts. > >> > >> Does the vendor BIOS print a message about the core count being limited > >> on one of the CPUs for compatibility reasons? > >> > >> On 04/11/2018 12:57 PM, Elisenda Cuadros wrote: > >>> Hello, > >> > >>> After testing the board for some weeks I bought another CPU (6276). I > >>> installed this into CPU1 slot and a 6238 in CPU2. > >> > >>> I checked that both CPUs are shining and also the memory (Micron > >>> MT18JSF25672PDZ-1G4F1DD, populated in A2/C2/E2/G2 slots). > >> > >>> The problem is that Coreboot seems to hang at the beginning. I attach > >>> console.log. > >> > >>> I reinstalled all the devices twice, checked the vendor manual, > docs in > >>> coreboot.org, messages in mailing list, but I don't know what is > causing > >>> the problem. > >> > >>> Last test I've done is booting with vendor bios, and it boots without > >>> problem. > >> > >>> Any ideas? > >> > >>> Thank you for your help. > >> > >>> Regards, > >> > >>> - Eli > >> > >> > >> > >> > >> > >> > > > > > signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 That should work, yes. It's the very early init code that is getting confused with the differing core counts, likely related to APIC setup or similar. On 04/11/2018 03:26 PM, taii...@gmx.com wrote: > But it would be possible to have two CPU's with the same core count but > differing frequencies? > > Thanks > - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJaznCJAAoJEK+E3vEXDOFbfqsH+wegvs3Zu2ZNrM+W54LFXB7U qVv4eAomKhPsf2UY5XzwhxVqzDn81PFI3HbMolfOwhNu/MfYeJIX7uxSdbMFReSH 3DF2808zOVaPQ5GdK3+dtNz7csM9pSTJUAIXPuDmRRYczrbDGEGYIP2OhMku+12x b8X2iUVRDk0C9s/Rou+p9dEgJiH/xAf47X8L4BHzf8jna2IrY6WJgJiUvK2wxVx+ fahO6au24/yRsNfsdaG7Ax+1GXQF7imlcL7z1zM0JxQjt1OHExjClW/klaNEshjc Wn+ebc77Blw6+klh7PdSkzs5nIQ3kCIoQuP9KvR0zbiWdmYKzj5NPk2awKAUTbg= =P/vl -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
But it would be possible to have two CPU's with the same core count but differing frequencies? Thanks 0xDF372A17.asc Description: application/pgp-keys -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 This may be a general coreboot limitation at the moment. The compatibility sections for mixed CPUs in the BKDG are more concerned with total power delivery and proper P-state setup than anything else. If I recall correctly, coreboot assumes both CPUs have the same core count when setting up APICs and such. There are a number of places that would need to be modified to remove this assumption; it's a leftover from the original K8 code and would take some significant work to fix. This also needs to be verified as I am going from memory here from a couple of years ago. On 04/11/2018 02:12 PM, Elisenda Cuadros wrote: > Thank you for your reply Timothy. > > Vendor Bios doesn't print any special message regarding this. > > In fact it shows a total of 28 cores (16+12). > > I thought mixing CPUs from same families was supported. > > Regards, > > - Eli > > On 11/04/18 20:44, Timothy Pearson wrote: >> I don't know if coreboot has support for differing CPUs in the same >> mainboard; it's not something I can recall testing at any point. >> >> The failure is occurring far before memory initialization, in CAR, in >> core setup. I'd guess it has something to do with the two CPUs you have >> installed having different core counts. >> >> Does the vendor BIOS print a message about the core count being limited >> on one of the CPUs for compatibility reasons? >> >> On 04/11/2018 12:57 PM, Elisenda Cuadros wrote: >>> Hello, >> >>> After testing the board for some weeks I bought another CPU (6276). I >>> installed this into CPU1 slot and a 6238 in CPU2. >> >>> I checked that both CPUs are shining and also the memory (Micron >>> MT18JSF25672PDZ-1G4F1DD, populated in A2/C2/E2/G2 slots). >> >>> The problem is that Coreboot seems to hang at the beginning. I attach >>> console.log. >> >>> I reinstalled all the devices twice, checked the vendor manual, docs in >>> coreboot.org, messages in mailing list, but I don't know what is causing >>> the problem. >> >>> Last test I've done is booting with vendor bios, and it boots without >>> problem. >> >>> Any ideas? >> >>> Thank you for your help. >> >>> Regards, >> >>> - Eli >> >> >> >> >> >> > > - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJazmI3AAoJEK+E3vEXDOFbYtoH+wTs7rFYkkAq4niZcqSGEqaW KMuhAUf3G5a86mcmpnhnJNCstFfDrc1+nWBMyF8xVmp6M/sV1mE869W2ppxHWbiD iuK1jO16zNQGPOddDvLQuVNgn57qGC5D5HEstljNkfcOi2svQkbPF+Fzno46SF/2 skGkg3PPfi5kIYQNWPBWYUUI7gUEg5s5bnQ7lnqNxi4V8hBZaVS8zVjUzHn6RYEs RpSLepk2iynwBcG5hGsKAPYvsE4WQZcWOz4talVnGVdv6m05KmPxh6MfIMvhnNji ShGUDjPkLAsk80qDT5ZN4VBImEhcGG6Yg1297HiOI0cklRXhvufVKaG2vufb0XA= =WGT+ -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
Thank you for your reply Timothy. Vendor Bios doesn't print any special message regarding this. In fact it shows a total of 28 cores (16+12). I thought mixing CPUs from same families was supported. Regards, - Eli On 11/04/18 20:44, Timothy Pearson wrote: > I don't know if coreboot has support for differing CPUs in the same > mainboard; it's not something I can recall testing at any point. > > The failure is occurring far before memory initialization, in CAR, in > core setup. I'd guess it has something to do with the two CPUs you have > installed having different core counts. > > Does the vendor BIOS print a message about the core count being limited > on one of the CPUs for compatibility reasons? > > On 04/11/2018 12:57 PM, Elisenda Cuadros wrote: > > Hello, > > > After testing the board for some weeks I bought another CPU (6276). I > > installed this into CPU1 slot and a 6238 in CPU2. > > > I checked that both CPUs are shining and also the memory (Micron > > MT18JSF25672PDZ-1G4F1DD, populated in A2/C2/E2/G2 slots). > > > The problem is that Coreboot seems to hang at the beginning. I attach > > console.log. > > > I reinstalled all the devices twice, checked the vendor manual, docs in > > coreboot.org, messages in mailing list, but I don't know what is causing > > the problem. > > > Last test I've done is booting with vendor bios, and it boots without > > problem. > > > Any ideas? > > > Thank you for your help. > > > Regards, > > > - Eli > > > > > > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] KGPE-D16 / Problem booting with two CPUs
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 I don't know if coreboot has support for differing CPUs in the same mainboard; it's not something I can recall testing at any point. The failure is occurring far before memory initialization, in CAR, in core setup. I'd guess it has something to do with the two CPUs you have installed having different core counts. Does the vendor BIOS print a message about the core count being limited on one of the CPUs for compatibility reasons? On 04/11/2018 12:57 PM, Elisenda Cuadros wrote: > Hello, > > After testing the board for some weeks I bought another CPU (6276). I > installed this into CPU1 slot and a 6238 in CPU2. > > I checked that both CPUs are shining and also the memory (Micron > MT18JSF25672PDZ-1G4F1DD, populated in A2/C2/E2/G2 slots). > > The problem is that Coreboot seems to hang at the beginning. I attach > console.log. > > I reinstalled all the devices twice, checked the vendor manual, docs in > coreboot.org, messages in mailing list, but I don't know what is causing > the problem. > > Last test I've done is booting with vendor bios, and it boots without > problem. > > Any ideas? > > Thank you for your help. > > Regards, > > - Eli > > > > - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) https://www.raptorengineering.com -BEGIN PGP SIGNATURE- Version: GnuPG v1 iQEcBAEBAgAGBQJazleSAAoJEK+E3vEXDOFbrFcH/i6xBhUGli6lYBXFM4d29CW7 UH6Z1Ksr2bD5jNfoKd1bmLx61w0KdG6Fyt/AmFr4dNXmAxTzuudw1ZZxauZe21Sk neJfuoMtctq/YQTaliMhPawO+6vARiVdNUYaMmDZO6cf4h9252WdpBU99JCJsbhC BkcIApR+0resb6iO2XpbPelnMA4yjitpgonXqKbVI6OvdYz5b3NViytCKcHunyzc 7H/GzpS93K1hWs7kLdNCJ7J7M0BtUSh2pGu/uaqr1ZSXWZgwBeQGESMG7etpT1Ju LP+e8C9dm0iLiTS8FIond8WUu4Q4bt7ebAqohrNQoMRpYlmyHWgEVSzecddqMJM= =ke+3 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] KGPE-D16 / Problem booting with two CPUs
Hello, After testing the board for some weeks I bought another CPU (6276). I installed this into CPU1 slot and a 6238 in CPU2. I checked that both CPUs are shining and also the memory (Micron MT18JSF25672PDZ-1G4F1DD, populated in A2/C2/E2/G2 slots). The problem is that Coreboot seems to hang at the beginning. I attach console.log. I reinstalled all the devices twice, checked the vendor manual, docs in coreboot.org, messages in mailing list, but I don't know what is causing the problem. Last test I've done is booting with vendor bios, and it boots without problem. Any ideas? Thank you for your help. Regards, - Eli coreboot-4.7-542-g39e1ab1d25-dirty Sun Mar 18 10:53:23 UTC 2018 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d40,000cd2ac] bsp_apicid = 00 cpu_init_detectedx = sb700 reset flags: CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 75400 size 318c CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 78600 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 done Enter amd_ht_init AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 Forcing HT links to isochronous mode due to enabled IOMMU CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 Exit amd_ht_init amd_ht_fixup amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1) cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 0316 F3xDC: 05475632 Prep FID/VID Node:01 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f17 F3xD8: 0316 F3xDC: 05475632 Prep FID/VID Node:02 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1a F3xD8: 0316 F3xDC: 05475632 Prep FID/VID Node:03 F3x80: e20be281 F3x84: 01e200e2 F3xD4: c3312f1a F3xD8: 0316 F3xDC: 05475632 setup_remote_node: 01 done Start node 01 done. setup_remote_node: 02 done Start node 02 done. setup_remote_node: 03 done Start node 03 done. core0 started: 01 02 coreboot-4.7-542-g39e1ab1d25-dirty Sun Mar 18 10:53:23 UTC 2018 romstage starting... Initial stack pointer: 000dffb8 CPU APICID 00 start flag set BSP Family_Model: 00600f12 *sysinfo range: [000c2d40,000cd2ac] bsp_apicid = 00 cpu_init_detectedx = sb700 reset flags: CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'microcode_amd.bin' CBFS: Found @ offset 75400 size 318c CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'microcode_amd_fam15h.bin' CBFS: Found @ offset 78600 size 1ec4 [microcode] patch id to apply = 0x0600063d [microcode] updated to patch id = 0x0600063d success cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 done Enter amd_ht_init AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2 AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3 CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 Forcing HT links to isochronous mode due to enabled IOMMU CBFS: 'Master Header Locator' located CBFS at [e00200:c0) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2c100 size dc4 Exit amd_ht_init amd_ht_fixup amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1) amd_ht_fixup: node 2 (internal node ID 0): disab
