Re: [coreboot] Need help implementing romstage CBMEM

2017-08-31 Thread Keith Hui 
Oops, I've attached the boot log of a previous failed attempt. This
boot log should be the correct one.

On Thu, Aug 31, 2017 at 1:29 PM, Keith Hui  wrote:
> On Wed, Aug 30, 2017 at 6:49 PM, Kyösti Mälkki  
> wrote:
>> On Wed, Aug 30, 2017 at 11:39 PM, Keith Hui  wrote:
>>> Hi guys,
>>>
>>> I'm still hard at work over the venerable (even "almighty" at the
>>> time) 440BX and Slot 1 boards.
>>>
>>> [1] https://review.coreboot.org/c/20977/
>>>
>>> And now I'm stuck and thoroughly confused.
>>>
>>> My current state is:
>>> 1. cbmem_initialize_empty() failed to even start allocating the root
>>> CBMEM entry. No indication why. I tried tracing the code path in the
>>> sources and still could not find out where exactly it failed. With
>>> enough fiddling I did get it to complain the way Aaron expected [1].
>>
>> Please update your work in gerrit, showing all the actual code changes
>> you try to boot with. This includes changes under mainboard/.
>>
>>> 2. Using the common Intel CPU cache_as_ram.inc, I can get through
>>> mainboard romstage and memory init. If I just return a fixed
>>> CONFIG_TOPMEM in setup_stack_and_mtrrs() like what was done in
>>> cpu/intel/nehalem, it got past the point of POST_PREPARE_RAMSTAGE and
>>> then nothing.
>>
>> All that setup_stack_and_mtrrs() is not really required for
>> EARLY_CBMEM_INIT, leave all that as followup work. Use unmodified
>> car/romstage_legacy.c and car/cache_as_ram.inc with that
>> DCACHE_RAM_BASE fixed.
>>
>> Disable CBMEM console and timestamps for the time being, as those eat
>> a lot of your CAR allocation. Those may have smashed your stack in CAR
>> to the extent of breaking raminit.
>>
>>> 3. Porting the postcar frame assembly from
>>> cpu/intel/car/cache_as_ram_ht.inc results in a failure somewhere
>>> before loading ramstage and after
>>
>> Push your modified source to gerrit if you want comments on that.
>>
>>> 4. If I try to run this build under QEMU, it fails with "Trying to
>>> execute code outside RAM or ROM at 0x000a" in 440BX RAM init code
>>> after dumping the "before" northbridge config, so I can't correctly
>>> debug it this way either.
>>
>> Just forget about using QEMU for the task at hand.
>>
>> Kyösti
>
> Thanks for the tips Kyösti. Nothing like hearing it from the source. :)
>
> I've updated gerrit again following your tips. This update actually
> boots! Boot log attached.
>
> For cache_as_ram.inc I just dropped CacheBase/CacheSize and have it
> use the Kconfig settings directly. I also increased the CAR size to
> 8k.
>
> Q1: Would this qualify as cbmem in romstage?
>
> Set up stack and MTRRs in cpu/intel/slot_1
> cbmem_top() and associated top of RAM calculations go to nb/intel/i440bx.
>
> Q2: Are these the right places for these codes?
> All Slot 1 boards currently in tree use 440BX and much of them seem
> unmaintained. I only have 3 of them (-LS, P3B-F, -DS) and I don't have
> a second matching P3 CPU to test the DS. So I want to see if I can
> initialize CBMEM in cpu/intel/slot_1, lest work wasted with all those
> other boards getting dropped past 4.8?
coreboot-4.6-1081-g23acd5db2d-dirty Thu Aug 31 00:53:14 UTC 2017 romstage 
starting...

DIMM 0: 50
00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2c 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 af 
40: 25 7f 7f 7f 00 00 00 00 41 4d 50 4a 42 36 33 53 
50: 2d 36 38 4b 58 33 2d 45 42 49 00 00 00 01 00 00 
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
DIMM 1: 51
00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2c 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 af 
40: 7f 7f 7f 25 00 00 00 00 41 4d 50 4a 42 36 33 53 
50: 2d 36 38 4b 58 33 2d 45 42 41 00 00 00 01 00 00 
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
DIMM 2: 52
00: 80 08 04 0c 0a 02 40 00 01 70 54

Re: [coreboot] Need help implementing romstage CBMEM

2017-08-31 Thread Keith Hui 
On Wed, Aug 30, 2017 at 6:49 PM, Kyösti Mälkki  wrote:
> On Wed, Aug 30, 2017 at 11:39 PM, Keith Hui  wrote:
>> Hi guys,
>>
>> I'm still hard at work over the venerable (even "almighty" at the
>> time) 440BX and Slot 1 boards.
>>
>> [1] https://review.coreboot.org/c/20977/
>>
>> And now I'm stuck and thoroughly confused.
>>
>> My current state is:
>> 1. cbmem_initialize_empty() failed to even start allocating the root
>> CBMEM entry. No indication why. I tried tracing the code path in the
>> sources and still could not find out where exactly it failed. With
>> enough fiddling I did get it to complain the way Aaron expected [1].
>
> Please update your work in gerrit, showing all the actual code changes
> you try to boot with. This includes changes under mainboard/.
>
>> 2. Using the common Intel CPU cache_as_ram.inc, I can get through
>> mainboard romstage and memory init. If I just return a fixed
>> CONFIG_TOPMEM in setup_stack_and_mtrrs() like what was done in
>> cpu/intel/nehalem, it got past the point of POST_PREPARE_RAMSTAGE and
>> then nothing.
>
> All that setup_stack_and_mtrrs() is not really required for
> EARLY_CBMEM_INIT, leave all that as followup work. Use unmodified
> car/romstage_legacy.c and car/cache_as_ram.inc with that
> DCACHE_RAM_BASE fixed.
>
> Disable CBMEM console and timestamps for the time being, as those eat
> a lot of your CAR allocation. Those may have smashed your stack in CAR
> to the extent of breaking raminit.
>
>> 3. Porting the postcar frame assembly from
>> cpu/intel/car/cache_as_ram_ht.inc results in a failure somewhere
>> before loading ramstage and after
>
> Push your modified source to gerrit if you want comments on that.
>
>> 4. If I try to run this build under QEMU, it fails with "Trying to
>> execute code outside RAM or ROM at 0x000a" in 440BX RAM init code
>> after dumping the "before" northbridge config, so I can't correctly
>> debug it this way either.
>
> Just forget about using QEMU for the task at hand.
>
> Kyösti

Thanks for the tips Kyösti. Nothing like hearing it from the source. :)

I've updated gerrit again following your tips. This update actually
boots! Boot log attached.

For cache_as_ram.inc I just dropped CacheBase/CacheSize and have it
use the Kconfig settings directly. I also increased the CAR size to
8k.

Q1: Would this qualify as cbmem in romstage?

Set up stack and MTRRs in cpu/intel/slot_1
cbmem_top() and associated top of RAM calculations go to nb/intel/i440bx.

Q2: Are these the right places for these codes?
All Slot 1 boards currently in tree use 440BX and much of them seem
unmaintained. I only have 3 of them (-LS, P3B-F, -DS) and I don't have
a second matching P3 CPU to test the DS. So I want to see if I can
initialize CBMEM in cpu/intel/slot_1, lest work wasted with all those
other boards getting dropped past 4.8?
coreboot-4.6-1081-g23acd5db2d-dirty Thu Aug 31 00:53:14 UTC 2017 romstage 
starting...

DIMM 0: 50
00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2c 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 af 
40: 25 7f 7f 7f 00 00 00 00 41 4d 50 4a 42 36 33 53 
50: 2d 36 38 4b 58 33 2d 45 42 49 00 00 00 01 00 00 
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
DIMM 1: 51
00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2c 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 af 
40: 7f 7f 7f 25 00 00 00 00 41 4d 50 4a 42 36 33 53 
50: 2d 36 38 4b 58 33 2d 45 42 41 00 00 00 01 00 00 
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
DIMM 2: 52
00: 80 08 04 0c 0a 02 40 00 01 70 54 00 80 08 00 01 
10: 8f 04 06 01 01 00 0e 75 54 00 00 0f 0e 0f 2d 20 
20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00 
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 69 
40: 00 43 41 54 32 32 00 00 00 00 00 00 00 00 00 00 
50: 00 08 00 00 00 00 00 00 00 00 00

Re: [coreboot] Need help implementing romstage CBMEM

2017-08-30 Thread Kyösti Mälkki 
On Wed, Aug 30, 2017 at 11:39 PM, Keith Hui  wrote:
> Hi guys,
>
> I'm still hard at work over the venerable (even "almighty" at the
> time) 440BX and Slot 1 boards.
>
> [1] https://review.coreboot.org/c/20977/
>
> And now I'm stuck and thoroughly confused.
>
> My current state is:
> 1. cbmem_initialize_empty() failed to even start allocating the root
> CBMEM entry. No indication why. I tried tracing the code path in the
> sources and still could not find out where exactly it failed. With
> enough fiddling I did get it to complain the way Aaron expected [1].

Please update your work in gerrit, showing all the actual code changes
you try to boot with. This includes changes under mainboard/.

> 2. Using the common Intel CPU cache_as_ram.inc, I can get through
> mainboard romstage and memory init. If I just return a fixed
> CONFIG_TOPMEM in setup_stack_and_mtrrs() like what was done in
> cpu/intel/nehalem, it got past the point of POST_PREPARE_RAMSTAGE and
> then nothing.

All that setup_stack_and_mtrrs() is not really required for
EARLY_CBMEM_INIT, leave all that as followup work. Use unmodified
car/romstage_legacy.c and car/cache_as_ram.inc with that
DCACHE_RAM_BASE fixed.

Disable CBMEM console and timestamps for the time being, as those eat
a lot of your CAR allocation. Those may have smashed your stack in CAR
to the extent of breaking raminit.

> 3. Porting the postcar frame assembly from
> cpu/intel/car/cache_as_ram_ht.inc results in a failure somewhere
> before loading ramstage and after

Push your modified source to gerrit if you want comments on that.

> 4. If I try to run this build under QEMU, it fails with "Trying to
> execute code outside RAM or ROM at 0x000a" in 440BX RAM init code
> after dumping the "before" northbridge config, so I can't correctly
> debug it this way either.

Just forget about using QEMU for the task at hand.

Kyösti

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[coreboot] Need help implementing romstage CBMEM

2017-08-30 Thread Keith Hui 
Hi guys,

I'm still hard at work over the venerable (even "almighty" at the
time) 440BX and Slot 1 boards.

[1] https://review.coreboot.org/c/20977/

And now I'm stuck and thoroughly confused.

My current state is:
1. cbmem_initialize_empty() failed to even start allocating the root
CBMEM entry. No indication why. I tried tracing the code path in the
sources and still could not find out where exactly it failed. With
enough fiddling I did get it to complain the way Aaron expected [1].
2. Using the common Intel CPU cache_as_ram.inc, I can get through
mainboard romstage and memory init. If I just return a fixed
CONFIG_TOPMEM in setup_stack_and_mtrrs() like what was done in
cpu/intel/nehalem, it got past the point of POST_PREPARE_RAMSTAGE and
then nothing.
3. Porting the postcar frame assembly from
cpu/intel/car/cache_as_ram_ht.inc results in a failure somewhere
before loading ramstage and after
4. If I try to run this build under QEMU, it fails with "Trying to
execute code outside RAM or ROM at 0x000a" in 440BX RAM init code
after dumping the "before" northbridge config, so I can't correctly
debug it this way either.

I think there's still not clear enough description on how this dynamic
CBMEM allocation works. Below is my take and I'll stand readily to be
corrected:

1. Reset vector -> protected mode -> southbridge bootblock init for
ROM -> bootblock walks CBFS to find romstage.
2. CAR setup in cpu/intel/car/cache_as_ram.inc
3. romstage_main() -> sets up a stack guard ->
mainboard_romstage_entry() -> check for overunning of said stack guard
4. romstage calls cbmem_initialize_empty()
5. Somewhere along the cbmem_initialize() path cbmem_top() is called
to find out where top of RAM is. It is supposed to allocate memory so
that it grows down from here.
6. setup_stack_and_mtrrs() -> allocates a 20KB postcar stack on CBMEM
and adds MTRR settings as appropriate. These gets pushed onto the
postcar stack in order of popping:

maximum number of supported variable MTRRs <- bottom of stack
number of actual used MTRRs
MTRR 0 base, low 32 bits
MTRR 0 base, high 32 bits
MTRR 0 mask, low 32 bits
MTRR 0 mask, high 32 bits
...

And this stack should be in RAM, supposedly in an area allocated within CBMEM.

7. This postcar stack pointer is returned via romstage_main(). It gets
loaded into %esp, effectively switching the code into a RAM stack with
all the MTRRs info on it.
8. Tear down CAR.
9. Wipes all the MTRRs.
10. MTRR values are popped off the stack and loaded into the variable MTRRs.
11. Now the CPU should be at the top of the allocated RAM stack and
can move on to load the ramstage.

The sources say for step 5 "the number of entries depends on the size
between down-aligned (by 4k) version and the actual top of memory. I
thought cbmem_top() should return the actual bytes of available memory
and is already aligned and I'd end up with room for zero entries? And
if I just return the actual top of memory cbmem_top() for use a the
romstage stack, would it not overwrite the cbmem area?

Also how much room is there to consolidate the CAR setup and teardown
code and/or move more of it into C?

All the Slot 1 CPUs are in the P6 family and have 16KB L1 data cache
that is 4-way set associative. Can I use a full 16K range for CAR or I
can only use 4K (16K/4) of it? cache_as_ram.inc use a fixed MTRR that
tops out at address 0xD while cache_as_ram_ht.inc uses variable
MTRR 0 for this range. Variable MTRR 1 is used in both to cache the
ROM. But when I tried to port the latter approach over the code dies
doing it. Some Slot 1 CPUs have a very complicated L2 enable code
which is better left where it is so I'd like to limit myself to L1
cache at this stage.

Sorry if I am not making sense, because this is not making sense to me
either, so any help is appreciated.

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Re: [coreboot] Need help implementing romstage CBMEM

2017-08-21 Thread Keith Hui 
Hi All,

I got some assistance from Aaron via gerrit [1] and he had me try some
changes. He also asked for my .config which is attached here.

However, the key parts are:
CONFIG_DCACHE_RAM_BASE=0xcf000
CONFIG_DCACHE_RAM_SIZE=0x01000

This is not consistent with the hard coded assumption cpu/intel/car/romstage.c:
#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000

There is not enough CAR for the entire romstage stack.

Reverting to romstage_legacy and just initializing cbmem directly
there isn't taking me far either, at least I see the ramstage copy of
get_top_of_ram() get run.

Next I am going to try "modern" romstage again with an increased
CONFIG_DCACHE_RAM_SIZE, but I want to get as much info out as soon as
I can for tips.

[1] https://review.coreboot.org/20977

On Sat, Aug 12, 2017 at 10:44 PM, Keith Hui  wrote:
> Hi all,
>
> After reading the code for more recent Intel northbridges I think I
> have an idea on what needs to be added, so here is my attempt to bring
> 440BX to coreboot 4.7 standards:
>
> https://review.coreboot.org/20977
>
> The problem is it could not boot. The console log is attached.
>
> In short, I think I have the top of RAM value correct, but it could
> not find a place for the payload to load and the boot process is
> stuck.
>
> What am I missing?
>
> By the way, I think an unintended update for my two earlier patches
> were also pushed along with this change. How to I get them sorted out?
> [1] [2]
>
> Thanks
> Keith
>
> [1] https://review.coreboot.org/c/20868/
> [2] https://review.coreboot.org/c/20952/


.config
Description: Binary data
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[coreboot] Need help implementing romstage CBMEM

2017-08-13 Thread Keith Hui 
Hi all,

After reading the code for more recent Intel northbridges I think I
have an idea on what needs to be added, so here is my attempt to bring
440BX to coreboot 4.7 standards:

https://review.coreboot.org/20977

The problem is it could not boot. The console log is attached.

In short, I think I have the top of RAM value correct, but it could
not find a place for the payload to load and the boot process is
stuck.

What am I missing?

By the way, I think an unintended update for my two earlier patches
were also pushed along with this change. How to I get them sorted out?
[1] [2]

Thanks
Keith

[1] https://review.coreboot.org/c/20868/
[2] https://review.coreboot.org/c/20952/
coreboot-4.6-1057-gc1def2a24f-dirty Sat Aug 12 02:47:42 UTC 2017 romstage start.
get_top_of_ram() = 3000
CBFS: 'Master Header Locator' located CBFS at [100:3)
CBFS: Locating 'fallback/ramstage'   
CBFS: Found @ offset 19800 size 967d


coreboot-4.6-1057-gc1def2a24f-dirty Sat Aug 12 02:47:42 UTC 2017 ramstage start.
get_top_of_ram() = 3000
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: : enabled 1 
PCI: 00:00.0: enabled 1 
PCI: 00:01.0: enabled 1 
PCI: 00:04.0: enabled 1 
PNP: 03f0.0: enabled 1  
PNP: 03f0.1: enabled 1  
PNP: 03f0.2: enabled 1  
PNP: 03f0.3: enabled 1  
PNP: 03f0.5: enabled 1  
PNP: 03f0.7: enabled 1  
PNP: 03f0.8: enabled 1  
PNP: 03f0.a: enabled 1  
PCI: 00:04.1: enabled 1 
PCI: 00:04.2: enabled 1 
PCI: 00:04.3: enabled 1 
PCI: 00:06.0: enabled 1 
Compare with tree...
Root Device: enabled 1  
 CPU_CLUSTER: 0: enabled 1  
  APIC: 00: enabled 1   
 DOMAIN: : enabled 1
  PCI: 00:00.0: enabled 1   
  PCI: 00:01.0: enabled 1   
  PCI: 00:04.0: enabled 1   
   PNP: 03f0.0: enabled 1   
   PNP: 03f0.1: enabled 1   
   PNP: 03f0.2: enabled 1   
   PNP: 03f0.3: enabled 1   
   PNP: 03f0.5: enabled 1   
   PNP: 03f0.7: enabled 1   
   PNP: 03f0.8: enabled 1   
   PNP: 03f0.a: enabled 1   
  PCI: 00:04.1: enabled 1   
  PCI: 00:04.2: enabled 1   
  PCI: 00:04.3: enabled 1   
  PCI: 00:06.0: enabled 1   
Root Device scanning... 
root_dev_scan_bus for Root Device   
CPU_CLUSTER: 0 enabled  
DOMAIN:  enabled
DOMAIN:  scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/7190] ops
PCI: 00:00.0 [8086/7190] enabled
PCI: 00:01.0 [8086/7191] enabled
PCI: 00:04.0 [8086/7110] bus ops