On Sun, Apr 25, 2010 at 01:45:19PM +0200, Peter Stuge wrote:
xdrudis wrote:
They might just use a watchdog:
Ok. I'm rereading the link Gigabyte gave me,
Please read the US Patent.
I wasn't aware. I hadn't read your mail when I wrote mine. I started
to read it, but your summary was
On Sat, Apr 24, 2010 at 08:26:45PM +0200, Patrick Georgi wrote:
Am 24.04.2010 19:43, schrieb xdrudis:
They might just use a watchdog:
- BIOS 1 sets a flag
- BIOS 1 configures the watchdog to trigger when it's not touched within
2 seconds (or whatever). watchdog would reboot the system then
xdrudis wrote:
They might just use a watchdog:
Ok. I'm rereading the link Gigabyte gave me,
Please read the US Patent.
//Peter
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Thank you for your work on Dual BIOS.
What I don't understand is how is this supposed to work.
From what you say and what I asked sales cotact staff at gigabyte (no
very useful insights) , there are two bios roms. One has the ability
to check the other and run it only if it detects it's ok. If
Am 24.04.2010 19:43, schrieb xdrudis:
What I don't understand is how is this supposed to work.
From what you say and what I asked sales cotact staff at gigabyte (no
very useful insights) , there are two bios roms. One has the ability
to check the other and run it only if it detects it's ok.
Patrick Georgi wrote:
I'd be really amazed if they'd add another chip (that actually costs
money) and then only implement an incomplete protection scheme with it.
Yes it's surprising, but Gigabyte does add another flash device. They
also appear to rely on security by obscurity.
I'm trying
On 4/24/10 8:26 PM, Patrick Georgi wrote:
They might just use a watchdog:
- BIOS 1 sets a flag
- BIOS 1 configures the watchdog to trigger when it's not touched within
2 seconds (or whatever). watchdog would reboot the system then
- BIOS 1 jumps in BIOS 2
- BIOS 2 does whatever it needs to
Vadim Girlin wrote:
Please, post any info you have that can help me.
This has been discussed a few times before.
Gigabyte holds a patent for this technology. See
http://www.mail-archive.com/linuxb...@linuxbios.org/msg05929.html
for the link.
The patent describes how the DualBIOS scheme works.
On 04/12/2010 05:58 PM, Andriy Gapon wrote:
on 09/04/2010 19:52 Vadim Girlin said the following:
Here is code fragment I mentioned - some bit is set then reset:
(Not sure now that this code runs at all)
Vadim,
cool work!
BTW:
http://www.rom.by/forum/Gigabyte_DualBIOS
:-)
I've seen
On 04/12/2010 05:58 PM, Andriy Gapon wrote:
on 09/04/2010 19:52 Vadim Girlin said the following:
Here is code fragment I mentioned - some bit is set then reset:
(Not sure now that this code runs at all)
Vadim,
cool work!
BTW:
http://www.rom.by/forum/Gigabyte_DualBIOS
:-)
I've seen
on 09/04/2010 19:52 Vadim Girlin said the following:
Here is code fragment I mentioned - some bit is set then reset:
(Not sure now that this code runs at all)
Vadim,
cool work!
BTW:
http://www.rom.by/forum/Gigabyte_DualBIOS
:-)
--
Andriy Gapon
--
coreboot mailing list:
Hi Vadim,
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
techniques.
On 09.04.2010 08:12, Vadim Girlin wrote:
I'm going to try coreboot on Gigabyte GA-MA770-UD3.
It's AMD 770 (RX780 / SB700).
My
On 09.04.2010 14:35, Andriy Gapon wrote:
on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following:
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
BTW:
on 09/04/2010 15:42 Carl-Daniel Hailfinger said the following:
On 09.04.2010 14:35, Andriy Gapon wrote:
on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following:
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following:
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
BTW:
http://www.flashrom.org/pipermail/flashrom/2009-September/000542.html
Doesn't look like anybody showed
On 04/09/2010 04:18 PM, Carl-Daniel Hailfinger wrote:
Hi Vadim,
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
techniques.
On 09.04.2010 08:12, Vadim Girlin wrote:
I'm going to try coreboot on
That could be very helpful for me. This register (LDN 7 reg EF) seems to
be very interesting. Bit 0 is chip select, but also bits 2,4,5,6 are
used in bios code. Bit 6 probably is some watchdog setting - setting it
on with resetting other bits causes reboot in ~ a second.
Hm the LDN 7 EF is not
On 04/09/2010 07:56 PM, Rudolf Marek wrote:
That could be very helpful for me. This register (LDN 7 reg EF) seems to
be very interesting. Bit 0 is chip select, but also bits 2,4,5,6 are
used in bios code. Bit 6 probably is some watchdog setting - setting it
on with resetting other bits causes
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