Hello Antony,
On 11.08.2018 12:55, Antony AbeePrakash X V wrote:
> Coreboot FSP Performance Data
> ID: 950 - 951: 8118676370 - 2354813461 --> 4433ms (TS_FSP_MEMORY_INIT_START
> - TS_FSP_MEMORY_INIT_END)
> ID: 952 - 953: 10675414728 - 8905813067 --> 1361ms
> (TS_FSP_TEMP_RAM_EXIT_START - TS_FS
On 08/11/2018 03:44 AM, Matt DeVillier wrote:
> or outputting the boot console to a non-existent serial port (which can slow
> everything down).
Yeah ditto, and it could also be a high log level or other debug
features enabled that you don't need like the EHCI debug
console...probably a combinati
e FSP source ?
Please advice.
Thanks
From: Matt DeVillier [mailto:matt.devill...@gmail.com]
Sent: Saturday, August 11, 2018 1:15 PM
To: Antony AbeePrakash X V
Cc: coreboot
Subject: Re: [coreboot] Reducing the boot time
assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run the
e FSP source ?
Please advice.
Thanks
From: Matt DeVillier [mailto:matt.devill...@gmail.com]
Sent: Saturday, August 11, 2018 1:15 PM
To: Antony AbeePrakash X V
Cc: coreboot
Subject: Re: [coreboot] Reducing the boot time
assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run t
assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run
the cbmem utility and see how long each stage/section of coreboot is taking
(up to the point of handing off control to the payload). 30s to boot
sounds like either you're not caching the RAM training data (MRC cache) and
the
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