Re: [coreboot] Reducing the boot time

2018-08-14 Thread Nico Huber 
Hello Antony,

On 11.08.2018 12:55, Antony AbeePrakash X V wrote:
> Coreboot FSP Performance Data
> ID: 950 - 951: 8118676370 - 2354813461 --> 4433ms   (TS_FSP_MEMORY_INIT_START 
> - TS_FSP_MEMORY_INIT_END)
> ID: 952 - 953: 10675414728 - 8905813067 --> 1361ms  
> (TS_FSP_TEMP_RAM_EXIT_START - TS_FSP_TEMP_RAM_EXIT_END)
> ID: 954 - 955: 11761158519 - 10934089420 --> 636ms   
> (TS_FSP_SILICON_INIT_START - TS_FSP_SILICON_INIT_END)
> ID: 956 - 957: 19265617974 - 19265559282 --> 0ms   
> (TS_FSP_BEFORE_ENUMERATE - TS_FSP_AFTER_ENUMERATE)

given that Google uses the same SoC for Chromebooks, I would expect
about ten times faster numbers.

What FSP binary do you use? There is one in Intel's FSP GitHub repo[1].
Maybe try that one if you haven't already. I know there are also bina-
ries with additional debugging enabled; that might slow things down.

> 
> Can we reduce the above mentioned time taken by modifying the FSP source ? 
> Please advice.

Questions about the FSP source are better directed towards Intel. They
do not want this community to know the source.

Nico

[1] https://github.com/IntelFsp/FSP/tree/ApolloLake

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Re: [coreboot] Reducing the boot time

2018-08-11 Thread taii...@gmx.com 
On 08/11/2018 03:44 AM, Matt DeVillier wrote:
> or outputting the boot console to a non-existent serial port (which can slow 
> everything down).

Yeah ditto, and it could also be a high log level or other debug
features enabled that you don't need like the EHCI debug
console...probably a combination of things.

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Re: [coreboot] Reducing the boot time

2018-08-11 Thread Antony AbeePrakash X V 
Hi,

Thanks for your feedback.

We enabled ENABLE_FSP_FAST_BOOT and MRC cache Training data in FSP using binary 
configuration tool. Also we reduced the console log level to 0.

Now the boot time is reduced to 23 secs for initial boot and 11 secs for 
upcoming power cycles.

Is this a normal behavior ?

Also from the console logs we found the following:

Coreboot FSP Performance Data
ID: 950 - 951: 8118676370 - 2354813461 --> 4433ms   (TS_FSP_MEMORY_INIT_START - 
TS_FSP_MEMORY_INIT_END)
ID: 952 - 953: 10675414728 - 8905813067 --> 1361ms  (TS_FSP_TEMP_RAM_EXIT_START 
- TS_FSP_TEMP_RAM_EXIT_END)
ID: 954 - 955: 11761158519 - 10934089420 --> 636ms   (TS_FSP_SILICON_INIT_START 
- TS_FSP_SILICON_INIT_END)
ID: 956 - 957: 19265617974 - 19265559282 --> 0ms   (TS_FSP_BEFORE_ENUMERATE 
- TS_FSP_AFTER_ENUMERATE)

Can we reduce the above mentioned time taken by modifying the FSP source ? 
Please advice.

Thanks

From: Matt DeVillier [mailto:matt.devill...@gmail.com]
Sent: Saturday, August 11, 2018 1:15 PM
To: Antony AbeePrakash X V 
Cc: coreboot 
Subject: Re: [coreboot] Reducing the boot time

assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run the 
cbmem utility and see how long each stage/section of coreboot is taking (up to 
the point of handing off control to the payload).  30s to boot sounds like 
either you're not caching the RAM training data (MRC cache) and therefore 
redoing RAM training each time, or outputting the boot console to a 
non-existent serial port (which can slow everything down).  Whatever it is, 
looking at the timestamps will go a long way towards identifying the issue

On Sat, Aug 11, 2018 at 2:13 AM Antony AbeePrakash X V 
mailto:antonyabee.prakas...@lnttechservices.com>>
 wrote:
Hi,

We have developed a coreboot image for Apollo lake custom board. The time taken 
for boot up is around 30 seconds.
We would like to reduce the boot time as much as possible.

Following codes are removed:


  1.  Non-intel Apollolake specific codes in below folders

 *   Arch
 *   Soc
 *   Mainboard
 *   Vendorcode



  1.  Splash screen loading
  2.  SPI support – other than our custom board SPI.

Also we have disabled the COMPRESS_RAMSTAGE. Still we are not able to reduce 
the boot time.

Please suggest the methods to reduce the boot time.
Thanks & Regards,
Antony


L&T Technology Services Ltd

www.LntTechservices.com<http://www.lnttechservices.com/>

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Re: [coreboot] Reducing the boot time

2018-08-11 Thread Antony AbeePrakash X V 
Hi,

Thanks for your feedback.

We enabled ENABLE_FSP_FAST_BOOT and MRC cache Training data in FSP using binary 
configuration tool. Also we reduced the console log level to 0.

Now the boot time is reduced to 23 secs for initial boot and 11 secs for 
upcoming power cycles.

Is this a normal behavior ?

Also from the console logs we found the following:

Coreboot FSP Performance Data
ID: 950 - 951: 8118676370 - 2354813461 --> 4433ms   (TS_FSP_MEMORY_INIT_START - 
TS_FSP_MEMORY_INIT_END)
ID: 952 - 953: 10675414728 - 8905813067 --> 1361ms  (TS_FSP_TEMP_RAM_EXIT_START 
- TS_FSP_TEMP_RAM_EXIT_END)
ID: 954 - 955: 11761158519 - 10934089420 --> 636ms   (TS_FSP_SILICON_INIT_START 
- TS_FSP_SILICON_INIT_END)
ID: 956 - 957: 19265617974 - 19265559282 --> 0ms   (TS_FSP_BEFORE_ENUMERATE 
- TS_FSP_AFTER_ENUMERATE)

Can we reduce the above mentioned time taken by modifying the FSP source ? 
Please advice.

Thanks


From: Matt DeVillier [mailto:matt.devill...@gmail.com]
Sent: Saturday, August 11, 2018 1:15 PM
To: Antony AbeePrakash X V 
Cc: coreboot 
Subject: Re: [coreboot] Reducing the boot time

assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run the 
cbmem utility and see how long each stage/section of coreboot is taking (up to 
the point of handing off control to the payload).  30s to boot sounds like 
either you're not caching the RAM training data (MRC cache) and therefore 
redoing RAM training each time, or outputting the boot console to a 
non-existent serial port (which can slow everything down).  Whatever it is, 
looking at the timestamps will go a long way towards identifying the issue

On Sat, Aug 11, 2018 at 2:13 AM Antony AbeePrakash X V 
mailto:antonyabee.prakas...@lnttechservices.com>>
 wrote:
Hi,

We have developed a coreboot image for Apollo lake custom board. The time taken 
for boot up is around 30 seconds.
We would like to reduce the boot time as much as possible.

Following codes are removed:


  1.  Non-intel Apollolake specific codes in below folders

 *   Arch
 *   Soc
 *   Mainboard
 *   Vendorcode



  1.  Splash screen loading
  2.  SPI support – other than our custom board SPI.

Also we have disabled the COMPRESS_RAMSTAGE. Still we are not able to reduce 
the boot time.

Please suggest the methods to reduce the boot time.
Thanks & Regards,
Antony


L&T Technology Services Ltd

www.LntTechservices.com<http://www.lnttechservices.com/>

This Email may contain confidential or privileged information for the intended 
recipient (s). If you are not the intended recipient, please do not use or 
disseminate the information, notify the sender and delete it from your system.
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www.LntTechservices.com<http://www.lnttechservices.com/>

This Email may contain confidential or privileged information for the intended 
recipient (s). If you are not the intended recipient, please do not use or 
disseminate the information, notify the sender and delete it from your system.
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Re: [coreboot] Reducing the boot time

2018-08-11 Thread Matt DeVillier 
assuming you've built with CONFIG_COLLECT_TIMESTAMPS=y, you can build/run
the cbmem utility and see how long each stage/section of coreboot is taking
(up to the point of handing off control to the payload).  30s to boot
sounds like either you're not caching the RAM training data (MRC cache) and
therefore redoing RAM training each time, or outputting the boot console to
a non-existent serial port (which can slow everything down).  Whatever it
is, looking at the timestamps will go a long way towards identifying the
issue

On Sat, Aug 11, 2018 at 2:13 AM Antony AbeePrakash X V <
antonyabee.prakas...@lnttechservices.com> wrote:

> Hi,
>
>
>
> We have developed a coreboot image for Apollo lake custom board. The time
> taken for boot up is around 30 seconds.
>
> We would like to reduce the boot time as much as possible.
>
>
>
> Following codes are removed:
>
>
>
>1. Non-intel Apollolake specific codes in below folders
>   1. Arch
>   2. Soc
>   3. Mainboard
>   4. Vendorcode
>
>
>
>1. Splash screen loading
>2. SPI support – other than our custom board SPI.
>
>
>
> Also we have disabled the COMPRESS_RAMSTAGE. Still we are not able to
> reduce the boot time.
>
>
>
> Please suggest the methods to reduce the boot time.
>
> Thanks & Regards,
>
> Antony
>
>
>
> *L&T Technology Services Ltd*
>
> www.LntTechservices.com 
>
> This Email may contain confidential or privileged information for the
> intended recipient (s). If you are not the intended recipient, please do
> not use or disseminate the information, notify the sender and delete it
> from your system.
> --
> coreboot mailing list: coreboot@coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
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