AMDs new instructions for parallelism and support för side-channel attacks?

[Joachim Strömbergson]

Aloha!

I just saw om EE Times that AMD will start to extend their x86 CPUs with 
instructions to support/help developers take advantage of the increasing 
(potential) parallelism in their processors. First out are two 
instructions that allows the developer to get info about instruction 
completion as well as cache misses.


Considering the article by . about analysis of protection mechanism 
against cache based timing attacks for AES [1] one could assume that 
these instructions should be useful for writing side-channel resistant 
implementations


But, do you think that the opppsite is also possible, that these 
instructions might be a possible source for information leackage and 
vector for side-channel attacks, at least local, inter process attacks? 
I get a weird goodie-badie feeling when reading about these instructions...



[1] Johannes Blömer and Volker Krummel. Analysis of countermeasures 
against access driven cache attacks on AES

http://eprint.iacr.org/2007/282.pdf

--
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.

Kryptoblog - IT-säkerhet på svenska
http://www.strombergson.com/kryptoblog


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John Young and Cryptome

[Steven M. Bellovin]

http://www.radaronline.com/from-the-magazine/2007/08/cryptome_john_young_radar_anthony_haden_guest_1.php


--Steve Bellovin, http://www.cs.columbia.edu/~smb

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Re: Fwd: Potential SHA 1 Hack Using Distributed Computing - Near Miss(es) May be Good Enough

[Paul Hoffman]

At 11:00 PM -0700 8/13/07, Aram Perez wrote:

Anyone know more about this?


I have the same question. I could not find any description of *why* 
they think that finding near-misses is going to help the research. 
It's not clear if they are taking their own path, or trying to 
improve Wang's path, or what.


--Paul Hoffman, Director
--VPN Consortium

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