Hovav Shacham wrote:
On Aug 24, 2008, at 5:20 AM, Peter Gutmann wrote:
Speaking of CPU-specific optimisations, I've seen a few algorithm
proposals
from the last few years that assume that an algorithm can be scaled
linearly
in the number of CPU cores, treating a multicore CPU as some kind
Brian Gladman wrote:
But a fully byte oriented implementation runs at about 140 cycles/byte
and here the S-Box substitution step is a significant bottleneck.
...
It is also possible that the PPERM instruction could be used to speed up
the Galois field calculations to produce the S-Box
Eric Young wrote:
Eric Young wrote:
I've not looked at it enough yet, but currently I'm doing an AES round
in about 140 cycles a block (call it 13 per round plus overhead) on a
AMD64, (220e6 bytes/sec on a 2ghz cpu) using normal instructions.
Urk, correction, I forgot I've recently upgraded
Hello Peter Gutmann.
I'm working on a contribution to the SHA-3 process, and I've been
using exactly the sort of abstraction that you describe -- counting
one computation of a hash compression function as a unit of work
which could be computed concurrently by some sort of parallel
Peter Gutmann wrote:
Is there some feature of multicore CPUs that I'm missing, or is it a case of
cryptographers abstracting a bit too much away? And if it's the latter,
should someone tell them that multicore CPUs don't actually work that way?
I can't speak to the former issue, but I seem
On Aug 24, 2008, at 5:20 AM, Peter Gutmann wrote:
Speaking of CPU-specific optimisations, I've seen a few algorithm
proposals
from the last few years that assume that an algorithm can be scaled
linearly
in the number of CPU cores, treating a multicore CPU as some kind
of SIMD
engine with
Paul Crowley wrote:
http://www.ddj.com/hpc-high-performance-computing/201803067
In the above Dr Dobb's article from a little over a year ago, AMD
Senior Fellow Leendert vanDoorn states the Advanced Encryption
Standard (AES) algorithm gets a factor of 5 performance improvement by
using the
Speaking of CPU-specific optimisations, I've seen a few algorithm proposals
from the last few years that assume that an algorithm can be scaled linearly
in the number of CPU cores, treating a multicore CPU as some kind of SIMD
engine with all cores operating in lock-step, or at least engaging in
Eric Young wrote:
I've not looked at it enough yet, but currently I'm doing an AES round
in about 140 cycles a block (call it 13 per round plus overhead) on a
AMD64, (220e6 bytes/sec on a 2ghz cpu) using normal instructions.
Urk, correction, I forgot I've recently upgraded from a 2ghz machine
http://www.ddj.com/hpc-high-performance-computing/201803067
In the above Dr Dobb's article from a little over a year ago, AMD Senior
Fellow Leendert vanDoorn states the Advanced Encryption Standard (AES)
algorithm gets a factor of 5 performance improvement by using the new
SSE5 extension.
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