free entertainment!

[juan]

here's a guy called craig wright, also known as 'satoshi nakamoto'  (LMAO!!!)

https://www.youtube.com/watch?v=MXMCzhwm554

the points he makes are quite interesting : his and the 
bloomberg-journo-asshole's criticism of the lightning network is that LN 
users(nodes) would be 'unlicensed money transmitters' and so would be doing 
'illegal money laundering'.

'satoshi nakamoto' then rants against even more people who are 'redesigning' 
bitcoin to be 'illegal', that is have some privacy built in.  "I'm going to 
shut them down with SV". "We are going to take legal action" et cetera. No 
doubt that the guy is Real Libertarian.

It should be mentioned that  wright or 'satoshi nakamoto'(LMAO!!!) used to be a 
buddy of roger ver's but ver has finally disowned him. 

Re: of elephants and men

[Steve Kinney]

On 11/14/18 11:03 PM, Alfie John wrote:
> Hey Zenaan,
> 
> Are your posts always off topic to Cypherpunks? Maybe other people disagree 
> with me, but I somehow feel your purpose here is to make users unsubscribe 樂

Aw shucks.  Zenaan didn't make me unsubscribe.  He did make me create a
spam filter rule, and all his posts and replies land in their very own
folder - just in case the "stopped clock twice daily" effect produces
any real surprises.

Years later, still waiting

:o)





signature.asc
Description: OpenPGP digital signature

Re: of elephants and men

[Alfie John]

Hey Zenaan,

Are your posts always off topic to Cypherpunks? Maybe other people disagree 
with me, but I somehow feel your purpose here is to make users unsubscribe 樂

Alfie

Sent from my iPhone

> On 15 Nov 2018, at 10:29 am, Zenaan Harkness  wrote:
> 
> The younger generations today need rescuing, frankly.
> 
> In the Absence of Fathers: A Story of Elephants and Men
> http://thesestonewalls.com/gordon-macrae/in-the-absence-of-fathers-a-story-of-elephants-and-men/
> 
> The Delinquents - CBS News
> https://www.cbsnews.com/news/the-delinquents/
> 
> 
> [PDF] The effect of mature elephant bull introductions on ranging
> patterns ...
> https://koedoe.co.za/index.php/koedoe/article/download/115/117
> … this abnormal behaviour was corrected by introducing older bulls
> and culling certain problem elephants…
> 
> 
> Elephants Run To Greeting A New Rescued Baby Elephant
> https://www.youtube.com/watch?v=H_D4qqciraI
> 
> Blind elephant dances to the music of Bach on the piano
> https://scroll.in/video/887112/watch-this-video-of-a-blind-elephant-swaying-to-classical-music-on-the-piano-will-move-you
> 
> 
> Cheers
> Zen

Eyes open:: Trump warns Antifa re Tucker. Poland rising. Life imitating memes imitating ovens - no tears for Cali ovens of [PEACE]

[Zenaan Harkness]

Trump warns Antifa.

See below for the world's largest "far right" nationalist marches in
Poland - 200,000+ people.


The ultimate wood-gassification oven has wiped out much of
 Hol-ly-Wood, wel-come to Black-mail-Wood.

Da Jooish media includes le 'Ollywood as most already know, and God's
been firin' up de ovens already.

'E is an impatient, angry God!

Da hebes be smutifying dis realm, undermining family and all values
and collecting all de sheckels in computer numbers ... very big
numbers.  Enslaving numbers.  Not good!  Must do something!

Numbers that shouldn't even be possible - Oy Vey already‼

And no, dis one's not daily stormer...

Life's oven imitating le meme imitating le thoughts of le many…

Plagues I tell you, PLAGUES! Always tha plagues?!?!?!


 From the Stars to Ashes: (((HollyWood))) Celebrities Affected by
 Californian Wildfire Ovens
 
https://sputniknews.com/photo/201811141069791761-california-wildfires-celebrities/



Trump knows de score - Antifa only allowed to protest at the calm
watching of le nationalisté patriots who are, till now, self
restraining due to "Justice" 'just us' dept of Jewish protectionism
(American D.O.J.):

 Antifa better hope ‘other side’ doesn’t mobilize – Trump
 https://www.rt.com/usa/444012-antifa-other-side-mobilize-trump/

 Trump Tells Antifa They’d Better Hope the Opposition Doesn’t
 Mobilize – They’re Going to be Much More Violent
 
https://dailystormer.name/trump-tells-antifa-theyd-better-hope-the-opposition-doesnt-mobilize-theyre-going-to-be-much-more-violent/

   Trump: “These people, like the Antifa — they better hope that the
   opposition to Antifa decides not to mobilize. Because if they do,
   they’re much tougher. Much stronger. Potentially much more
   violent. And Antifa’s going to be in big trouble. But so far they
   haven’t done that and that’s a good thing,”

   … When asked specifically about the recent mob outside of Fox News
   host Tucker Carlson’s house, the president said, “I spoke to
   Tucker — I think Tucker’s a great guy — and I think it’s terrible.
   They were actually trying to break down [Tucker’s] door.”

   … “[Antifa] better hope that the other side doesn’t mobilize,”
   Trump concluded, “Because if you look, the other side, it’s the
   military. It’s the police. It’s a lot of very strong, a lot of
   very tough people. Tougher than them. And smarter than them.”

   “They’re sitting back and watching and they’re getting angrier and
   angrier,” Trump said of the Antifa opposition.

 …not even in California will they have the ability to bring charges
 against people who defended themselves against masked attackers
 without federal assistance.

 Remove Rosenstein’s power to act unilaterally to illegally imprison
 enemies of Jews, and you’ve solved the Antifa problem in a matter of
 hours.

 If it wasn’t for Rosenstein, an entire army of right-wingers would
 have been there to protect Tucker’s wife from these fed-kikes in a
 matter of minutes. It would have been like a five-minute version of
 the Spanish civil war in a rich DC suburb. …


[Indeed!]



UK Whites beginning to self organise - peacefully:

 Birmingham: 400 Strong Vigilante Mob Begins Street Patrols After
 Machete Attack
 
https://dailystormer.name/birmingham-400-strong-vigilante-mob-begins-street-patrols-after-machete-attack-video/

   … Things do not begin because of socially isolated individuals
   with radical ideologies taking self-nullifying actions. They begin
   because of socially connected individuals who share physical space
   organizing around a non-ideological problem and forming legal
   organizations.

   It just so happens that these are white people, and their problem
   is black and Arab criminal gangs. They probably didn’t think about
   that the way we think about those things. Sometimes, you just
   accidentally create a white organization for racial conflict.



(((Those whom we may not criticize))): keep pushing and find out what
comes next:

 ‘Europe will be white’: Polish leaders sanction massive far-right
 march in Warsaw
 https://www.rt.com/news/443656-far-right-march-given-greenlight/
   Government officials have agreed to conduct a joint march with
   far-right groups on Poland’s Independence Day

   … This year’s event, marking the centenary of Poland’s
   independence, attracted some 200,000 people – more than three
   times the numbers at last year’s march that was dubbed the largest
   far-right gathering in the world.

   The event included explicitly white supremacist symbols and
   banners with slogans such as “White Europe” and “Refugees get
   out!” The rally was cited in a European Parliament resolution that
   encouraged member states to crack down on far-right groups, but
   the leadership of Poland seem to have other plans.

   There was a last-minute attempt by the mayor of Warsaw to ban the
   march, but a court overturned his decision and allowed the event
   to go ahead – despite the fact that months of negotiations had

of elephants and men

[Zenaan Harkness]

The younger generations today need rescuing, frankly.

 In the Absence of Fathers: A Story of Elephants and Men
 
http://thesestonewalls.com/gordon-macrae/in-the-absence-of-fathers-a-story-of-elephants-and-men/

 The Delinquents - CBS News
 https://www.cbsnews.com/news/the-delinquents/


 [PDF] The effect of mature elephant bull introductions on ranging
 patterns ...
 https://koedoe.co.za/index.php/koedoe/article/download/115/117
 … this abnormal behaviour was corrected by introducing older bulls
 and culling certain problem elephants…


 Elephants Run To Greeting A New Rescued Baby Elephant
 https://www.youtube.com/watch?v=H_D4qqciraI

 Blind elephant dances to the music of Bach on the piano
 
https://scroll.in/video/887112/watch-this-video-of-a-blind-elephant-swaying-to-classical-music-on-the-piano-will-move-you


Cheers
Zen

Re: X86 dispatch contention vulnerability

[Travis Biehn]

On Wed, Nov 14, 2018 at 4:15 PM jim bell  wrote:

>
>
> On Wednesday, November 14, 2018, 11:52:43 AM PST, juan 
> wrote:
>
>
> On Wed, 14 Nov 2018 19:00:52 + (UTC)
>
> jim bell  wrote:
>
>
> >> My company, SemiDisk Systems, was very close to the first disk emulator
> for a number of types of PC, including the S-100, TRS-80 Model II, IBM PC,
> Epson Q-10.
> https://www.pcworld.com/article/246617/storage/evolution-of-the-solid-state-drive.html
>
>
> >IIRC you also worked for intel designing memory chips? Excuse my
> rather naive question but...Did you see/hear at that time any hints that
> chips  were being tampered with or somehow backdooored  because of
> 'national security'?
>
> I didn't design memory chips.  I was a "product engineer" for a specific
> self-refreshing dynamic RAM (otherwise called a "pseudo-static") device
> called a 2186.
> https://www.ebay.com/p/Vintage-Intel-D2186a-30-8k-X-8-Pseudo-Static-RAM-D2186-2186-SRAM/1918155784
>  Vintage Intel D2186a-30 8k X 8 Pseudo Static RAM D2186 2186 SRAM | eBay
> 
>   It, along with a 32K x 8 "21D1", were Intel's first by-8 dynamic RAMs.
>
> Product engineers design the test programs which check out the performance
> of a chip, using (at that time) an ultra-fast dedicated computer made by
> Teradyne.
> https://www.teradyne.com/products/test-solutions/semiconductor-test
>  This computer very accurately placed clock edges, to a position and
> accuracy of a small fraction of a nanosecond.   The 2186 was tricky by the
> standards of the day, partly due to the self-refreshing feature, but also
> because the 2186 (and 21D1) were the first Intel memory devices (possibly
> the first from anyone?) that employed "redundancy":  Previous memory
> devices were essentially unusable if even a single bit, or row, or column
> failed.  The 2186 incorporated many spare rows, and spare columns, which
> could be programmed in to substitute for bits, rows, and columns that had
> failed.
>
> My program tested the chip, then took the map of bad rows, columns, and
> bits, and first checked to see if the part could be made good, at least
> theoretically, if the available rows and columns would solve the visible
> problems.  If that appeared to be possible, my program determined which
> redundant rows and columns needed to be activated, and at which row and
> column they needed to be placed at.  From this, a bit stream was generated
> that was clocked into the chip, one bit at a time, and was used to blow
> poly-silicon links (fuses) in a write-once memory area.  That was the
> memory area which told the chip where to access the redundant rows and
> columns, instead of the array rows and columns.
>
> In fact, I was the first person at Intel, and perhaps in the world, who
> saw the flash(es) through the microscope of the as-being-blown fuses on
> these chips.  Intel was doing this redundancy before anyone else, I
> believe.
> ×
>
> Pseudo-static DRAMs refreshed themselves, with the (possible) aid of RFSH
> signal that might occasionally be applied to the chip.  Myself, I didn't
> think that DRAMs were hard to use, having designed a digital circuit and a
> DRAM card using an old Motorola DRAM called a "6605", that I got cheaply.
>
> https://computerarchive.org/files/mirror/www.bitsavers.org/pdf/motorola/_dataBooks/1979_Motorola_Memory_Data_Book.pdf
>
> I don't think that the 2186 was successful, mostly because Intel
> eventually got out of the DRAM business, and mostly that because other
> manufacturers got much better and more efficient than Intel was.
>
> I was never in a position to hear if chips could be "backdoored".
>
> Jim Bell
>
>
>
>
>

I believe Intel refers to 'backdoors' as 'features' for 'customer support
scenarios'.

-- 
Twitter  | LinkedIn
 | GitHub 
| TravisBiehn.com  | Google Plus

Re: X86 dispatch contention vulnerability

[jim bell]

 

On Wednesday, November 14, 2018, 11:52:43 AM PST, juan  
wrote:  
 
 On Wed, 14 Nov 2018 19:00:52 + (UTC)
jim bell  wrote:

 
>> My company, SemiDisk Systems, was very close to the first disk emulator for 
>> a number of types of PC, including the S-100, TRS-80 Model II, IBM PC, Epson 
>> Q-10.https://www.pcworld.com/article/246617/storage/evolution-of-the-solid-state-drive.html

>    IIRC you also worked for intel designing memory chips? Excuse my rather 
>naive question but...Did you see/hear at that time any hints that chips  were 
>being tampered with or somehow backdooored  because of 'national security'? 
I didn't design memory chips.  I was a "product engineer" for a specific 
self-refreshing dynamic RAM (otherwise called a "pseudo-static") device called 
a 2186.   
https://www.ebay.com/p/Vintage-Intel-D2186a-30-8k-X-8-Pseudo-Static-RAM-D2186-2186-SRAM/1918155784
    Vintage Intel D2186a-30 8k X 8 Pseudo Static RAM D2186 2186 SRAM | eBay    
It, along with a 32K x 8 "21D1", were Intel's first by-8 dynamic RAMs.
Product engineers design the test programs which check out the performance of a 
chip, using (at that time) an ultra-fast dedicated computer made by Teradyne. 
https://www.teradyne.com/products/test-solutions/semiconductor-test     This 
computer very accurately placed clock edges, to a position and accuracy of a 
small fraction of a nanosecond.   The 2186 was tricky by the standards of the 
day, partly due to the self-refreshing feature, but also because the 2186 (and 
21D1) were the first Intel memory devices (possibly the first from anyone?) 
that employed "redundancy":  Previous memory devices were essentially unusable 
if even a single bit, or row, or column failed.  The 2186 incorporated many 
spare rows, and spare columns, which could be programmed in to substitute for 
bits, rows, and columns that had failed.  

My program tested the chip, then took the map of bad rows, columns, and bits, 
and first checked to see if the part could be made good, at least 
theoretically, if the available rows and columns would solve the visible 
problems.  If that appeared to be possible, my program determined which 
redundant rows and columns needed to be activated, and at which row and column 
they needed to be placed at.  From this, a bit stream was generated that was 
clocked into the chip, one bit at a time, and was used to blow poly-silicon 
links (fuses) in a write-once memory area.  That was the memory area which told 
the chip where to access the redundant rows and columns, instead of the array 
rows and columns.  
In fact, I was the first person at Intel, and perhaps in the world, who saw the 
flash(es) through the microscope of the as-being-blown fuses on these chips.  
Intel was doing this redundancy before anyone else, I believe.  ×
Pseudo-static DRAMs refreshed themselves, with the (possible) aid of RFSH 
signal that might occasionally be applied to the chip.  Myself, I didn't think 
that DRAMs were hard to use, having designed a digital circuit and a DRAM card 
using an old Motorola DRAM called a "6605", that I got cheaply.  
https://computerarchive.org/files/mirror/www.bitsavers.org/pdf/motorola/_dataBooks/1979_Motorola_Memory_Data_Book.pdf
I don't think that the 2186 was successful, mostly because Intel eventually got 
out of the DRAM business, and mostly that because other manufacturers got much 
better and more efficient than Intel was.   
I was never in a position to hear if chips could be "backdoored".  
            Jim Bell




  

Re: X86 dispatch contention vulnerability

[juan]

On Wed, 14 Nov 2018 19:00:52 + (UTC)
jim bell  wrote:

 
> My company, SemiDisk Systems, was very close to the first disk emulator for a 
> number of types of PC, including the S-100, TRS-80 Model II, IBM PC, Epson 
> Q-10.https://www.pcworld.com/article/246617/storage/evolution-of-the-solid-state-drive.html

IIRC you also worked for intel designing memory chips? Excuse my rather 
naive question but...Did you see/hear at that time any hints that chips  were 
being tampered with or somehow backdooored  because of 'national security'?  

Re: X86 dispatch contention vulnerability

[jim bell]

 In "the good old days", in the 1970's, microprocessors were so much simpler.  
My favorite one for awhile, the Z-80 was trivial by today's standards.  No 
multi-threading, no pipelining, no speculative instruction execution, etc.   I 
built my own homebrew personal computer, which I called the "Bellyache I", 
using a Z-80.  I also built a 'brick' shaped disk-emulator for it, consisting 
of a board with 32 sockets of stacked-8-high 2118 16-kilobit DRAM chips.  
(5-volt only 16 kilobit.)   512kbytes of disk emulator, which actually seemed a 
lot of memory at the time!!!
In about October 1981, I actually discovered an error in the documentation 
sheet for the Z-80:  I was implementing my first "SemiDisk", and I was trying 
to use the INIR and OTIR instructions to do fast block-moves of data to/from 
the i/o mapped memory.  It turned out that doing those transfers from a 
128-byte block of memory had one of them "off" by 1 byte-count, and I traced 
the error to the fact that the Z-80 didn't operate precisely as the data-sheet 
indicated it should.  
My company, SemiDisk Systems, was very close to the first disk emulator for a 
number of types of PC, including the S-100, TRS-80 Model II, IBM PC, Epson 
Q-10.https://www.pcworld.com/article/246617/storage/evolution-of-the-solid-state-drive.html

http://www.ryli.net/the-brief-history-of-solid-state-drive-ssd/



                    Jim Bell


On Wednesday, November 14, 2018, 9:44:33 AM PST, Ryan Carboni 
 wrote:  
 
 Pretty embarrassing for “Intel Inside” if you ask me. Wonder how many 
“whitehats” let their findings get suppressed for money.


On Wednesday, November 14, 2018, jim bell  wrote:

 Sounds like a valid issue!
            Jim Bell
On Wednesday, November 14, 2018, 9:36:06 AM PST, Ryan Carboni 
 wrote:  
 
 While many x86 implementation vulnerabilities in the past involve either 
electromagnetic emissions or cache timing attacks, I have not read anything 
about instruction dispatch contention. According to anger fog’s research, 
Intel’s implementation of the x86 instruction set does not dispatch more than 
three of a single instruction, and it has been so for a long time. Irregardless 
of their design decisions for instruction dispatch, this provides a side 
channel in which two cooperating processes operating on the same core can 
conduct half-duplex communication at the rate of 2 bits per cycle by one 
process attempting to compete with another process for the same capacity for 
dispatches over a single instruction (0, 1, 2, 3). While I do not have the 
resources to know how x86 processors handles dispatch contention issues, if it 
is handled in a regular and non-random manner, it would reach that theoretical 
level of severity.
This violates certain access controls assumed to be imposed by the kernel.

I suppose I can’t collect my quarter million dollar prize if I publish this to 
the world?  
  

Re: X86 dispatch contention vulnerability

[Ryan Carboni]

Let my life be a lesson in futility. Go up against the government, and
they’ll send everything they got against you, including things that defy
known laws of physics.

Go with the government, get paid out of the NATO vulnerability slush fund
of tens of millions of dollars a year.

And sometimes a higher power will even the odds. All I ever did was reveal
a small fraction of vulnerabilities the government didn’t know about or had
already purchased. What’s that compared to what they do have?

Re: X86 dispatch contention vulnerability

[Ryan Carboni]

Pretty embarrassing for “Intel Inside” if you ask me. Wonder how many
“whitehats” let their findings get suppressed for money.



On Wednesday, November 14, 2018, jim bell  wrote:

> Sounds like a valid issue!
>
> Jim Bell
>
> On Wednesday, November 14, 2018, 9:36:06 AM PST, Ryan Carboni <
> rya...@gmail.com> wrote:
>
>
> While many x86 implementation vulnerabilities in the past involve either
> electromagnetic emissions or cache timing attacks, I have not read anything
> about instruction dispatch contention. According to anger fog’s research,
> Intel’s implementation of the x86 instruction set does not dispatch more
> than three of a single instruction, and it has been so for a long time.
> Irregardless of their design decisions for instruction dispatch, this
> provides a side channel in which two cooperating processes operating on the
> same core can conduct half-duplex communication at the rate of 2 bits per
> cycle by one process attempting to compete with another process for the
> same capacity for dispatches over a single instruction (0, 1, 2, 3). While
> I do not have the resources to know how x86 processors handles dispatch
> contention issues, if it is handled in a regular and non-random manner, it
> would reach that theoretical level of severity.
>
> This violates certain access controls assumed to be imposed by the kernel.
>
> I suppose I can’t collect my quarter million dollar prize if I publish
> this to the world?
>

Re: X86 dispatch contention vulnerability

[jim bell]

 Sounds like a valid issue!
            Jim Bell
On Wednesday, November 14, 2018, 9:36:06 AM PST, Ryan Carboni 
 wrote:  
 
 While many x86 implementation vulnerabilities in the past involve either 
electromagnetic emissions or cache timing attacks, I have not read anything 
about instruction dispatch contention. According to anger fog’s research, 
Intel’s implementation of the x86 instruction set does not dispatch more than 
three of a single instruction, and it has been so for a long time. Irregardless 
of their design decisions for instruction dispatch, this provides a side 
channel in which two cooperating processes operating on the same core can 
conduct half-duplex communication at the rate of 2 bits per cycle by one 
process attempting to compete with another process for the same capacity for 
dispatches over a single instruction (0, 1, 2, 3). While I do not have the 
resources to know how x86 processors handles dispatch contention issues, if it 
is handled in a regular and non-random manner, it would reach that theoretical 
level of severity.
This violates certain access controls assumed to be imposed by the kernel.

I suppose I can’t collect my quarter million dollar prize if I publish this to 
the world?  

X86 dispatch contention vulnerability

[Ryan Carboni]

While many x86 implementation vulnerabilities in the past involve either
electromagnetic emissions or cache timing attacks, I have not read anything
about instruction dispatch contention. According to anger fog’s research,
Intel’s implementation of the x86 instruction set does not dispatch more
than three of a single instruction, and it has been so for a long time.
Irregardless of their design decisions for instruction dispatch, this
provides a side channel in which two cooperating processes operating on the
same core can conduct half-duplex communication at the rate of 2 bits per
cycle by one process attempting to compete with another process for the
same capacity for dispatches over a single instruction (0, 1, 2, 3). While
I do not have the resources to know how x86 processors handles dispatch
contention issues, if it is handled in a regular and non-random manner, it
would reach that theoretical level of severity.

This violates certain access controls assumed to be imposed by the kernel.

I suppose I can’t collect my quarter million dollar prize if I publish this
to the world?

Re: Nigerian 404: Google not found, Internet wobbly

[grarpamp]

> Don't
> even tell me a worm armed with the NSA's login credential (reversed from
> the hard coded hash) is jumping around between Cisco routers...

### Welcome to Tier-N Global Network Console ###
% [research...]
# for node in $critnodes do shell $node "{ write erase ; reload ; } &"
# { dd if=/dev/zero of=/dev/boot bs=1m count=1 ; reboot ; } &
# exit

Strange that such never really happened in history, yet...


> O sunshine take me now away from here,
> I'm a needle on a spiral in a groove
> The turntable spins as the last waltz begins,
> and the weatherman say's someting's on the move...
>
> https://www.youtube.com/watch?v=o2rOWVWJmWU
>
> Then again, it's probably nothing.