https://www.nextplatform.com/2022/06/09/strong-showing-for-first-experimental-risc-v-supercomputer/
A European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance. More importantly, it demonstrates a potential path forward for RISC-V in high performance computing and by proxy, another shot for Europe to shed total reliance on American chip technologies beyond Arm-driven architectures. The “Monte Cimone” cluster will not be crunching massive weather simulations or the like anytime soon since it’s just an experimental machine. That said, it does show that performance sacrifices for lower power envelopes aren’t necessarily as dramatic as many believe. The six-node cluster, built by folks at Università di Bologna and CINECA, the largest supercomputing center in Italy, was part of a broader student cluster competition to showcase various elements of HPC performance beyond just floating-point capability. The cluster-building team, called NotOnlyFLOPs, wanted to establish the power-performance profile of RISC-V when using SiFive’s Freedom U740 system-on-chip. That 2020-era SoC has five 64-bit RISC-V CPU cores – four U7 application cores and an S7 system management core – 2MB of L2 cache, gigabit Ethernet, and various peripheral and hardware controllers. It can run up to around 1.4GHz. Here’s a look at the components as well as feeds and speeds of Monte Cimone: - Six dual-board servers with a form factor of 4.44 cm (1U) high, 42.5 cm width, 40 cm deep. Each board follows the industry standard Mini-ITX form factor (170 mm per 170 mm); - Each board features one SiFive Freedom U740 SoC and 16GB of 64-bit DDR memory operating at 1866s MT/s, plus a PCIe Gen 3 x8 bus operating at 7.8 GB/s, one gigabit Ethernet port, and USB 3.2 Gen 1 interfaces; - Each node has an M.2 M-key expansion slot occupied by a 1TB NVME 2280 SSD used by the operating system. A microSD card is inserted in each board and used for UEFI booting; - Two 250 W power supplies are integrated inside each node to support the hardware and future PCIe accelerators and expansion board
