From: Grygorii Strashko grygorii.stras...@ti.com
Date: Wed, 16 Jul 2014 15:13:01 +0300
The similar MDIO HW blocks is used by keystone 2 SoCs as
in Davinci SoCs:
- one in Gigabit Ethernet (GbE) Switch Subsystem
See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf
- one in 10 Gigabit Ethernet
From: Grygorii Strashko grygorii.stras...@ti.com
Date: Thu, 10 Jul 2014 15:58:31 +0300
Hi David,
On 07/10/2014 02:52 AM, David Miller wrote:
From: Grygorii Strashko grygorii.stras...@ti.com
Date: Wed, 9 Jul 2014 16:10:50 +0300
Required properties:
-- compatible : Should
From: Grygorii Strashko grygorii.stras...@ti.com
Date: Wed, 9 Jul 2014 16:10:50 +0300
Required properties:
-- compatible : Should be ti,davinci_mdio
+- compatible : Should be ti,davinci_mdio or ti,keystone-mdio
Why the inconsistency in naming schemes? I don't see any reason
From: Sekhar Nori nsek...@ti.com
Date: Tue, 20 May 2014 15:41:37 +0530
Commit e194312854edc22a2faf1931b3c0608fe20cb969 (drivers: net:
davinci_cpdma: Convert kzalloc() to devm_kzalloc()) triggered
a bug in emac_probe() wherein dev member of net_device is used
for devres allocations even before
From: Grygorii Strashko grygorii.stras...@ti.com
Date: Wed, 30 Apr 2014 15:23:32 +0300
Introduce a resource managed devm_mdiobus_alloc[_size]()/devm_mdiobus_free()
to automatically clean up MDIO bus alocations made by MDIO drivers,
thus leading to simplified MDIO drivers code.
Clean up
From: Christian Riesch christian.rie...@omicron.at
Date: Mon, 24 Mar 2014 13:46:25 +0100
since commit 6892b41d9701283085b655c6086fb57a5d63fa47 (Linux 3.11) the
davinci_emac driver is broken. After doing ifconfig down, ifconfig up,
requesting the interrupts for the driver fails. The interface
From: Sergei Shtylyov sergei.shtyl...@cogentembedded.com
Date: Tue, 28 Jan 2014 02:45:34 +0300
Though described as required, couple more properties in the DaVinci EMAC
binding are actually optional, as the driver will happily function without
them.
The patchset is against DaveM's
From: Sergei Shtylyov sergei.shtyl...@cogentembedded.com
Date: Fri, 17 Jan 2014 01:32:13 +0300
Though described as required, the phy-handle property for the DaVinci EMAC
binding is actually optional, as the driver will happily function without it,
assuming 100/FULL link; the property is not
From: Prabhakar Lad prabhakar.cse...@gmail.com
Date: Tue, 25 Jun 2013 21:24:50 +0530
From: Lad, Prabhakar prabhakar.cse...@gmail.com
This patch series cleans up the davinci driver.
This patch series applies on 3.10.rc7 and is boot tested
on OMAP-L138 EVM with DT and non DT cases.
Series
From: Sekhar Nori nsek...@ti.com
Date: Tue, 26 Mar 2013 15:35:43 +0530
This patch can then be dropped for now, but 1/2 can still be applied.
That one is pretty harmless!
I've applied it.
___
Davinci-linux-open-source mailing list
From: Prabhakar Lad prabhakar.cse...@gmail.com
Date: Sat, 16 Mar 2013 12:43:14 +0530
Hi Mugunthan
Thanks for the patch!
On Fri, Mar 15, 2013 at 7:40 PM, Mugunthan V N mugunthan...@ti.com wrote:
Fix which was done in the following commit in cpsw driver has
to be taken forward to davinci
From: Anatolij Gustschin ag...@denx.de
Date: Tue, 17 Jul 2012 12:34:24 +0200
From: Heiko Schocher h...@denx.de
add OF support for the davinci_emac driver.
Signed-off-by: Heiko Schocher h...@denx.de
Acked-by: Sekhar Nori nsek...@ti.com
Signed-off-by: Anatolij Gustschin ag...@denx.de
From: Christian Riesch christian.rie...@omicron.at
Date: Mon, 16 Apr 2012 16:35:25 +0200
Under heavy load (flood ping) it is possible for the MDIO timeout to
expire before the loop checks the GO bit again. This patch adds an
additional check whether the operation was done before actually
From: Christian Riesch christian.rie...@omicron.at
Date: Thu, 23 Feb 2012 08:58:00 +0100
chan-chan_num is 0..CPDMA_MAX_CHANNELS-1 for tx channels and
CPDMA_MAX_CHANNELS..2*CPDMA_MAX_CHANNELS-1 for rx channels. However,
the rx and tx teardown registers expect zero based channel numbering.
From: Christian Riesch christian.rie...@omicron.at
Date: Thu, 23 Feb 2012 09:07:58 +0100
The CLKDIV bitfield in the MDIO Control Register is a 16 bit field,
therefore the CLKDIV value may range from 0 to 0x.
Signed-off-by: Christian Riesch christian.rie...@omicron.at
Also applied to
From: Christian Riesch christian.rie...@omicron.at
Date: Thu, 23 Feb 2012 12:14:17 +0100
This patch fixes a regression that was introduced by
commit 0a5f38467765ee15478db90d81e40c269c8dda20
davinci_emac: Add Carrier Link OK check in Davinci RX Handler
Said commit adds a check whether the
From: Sriramakrishnan A G s...@ti.com
Date: Tue, 12 Apr 2011 10:12:31 +0530
The DMA cleanup function was holding the spinlock across
a busy loop where it waits for HW to indicate teardown is complete.
This generates a backtrace, when DEBUG_SPINLOCK is enabled. Make the
locking more granular.
From: Sergei Shtylyov sshtyl...@mvista.com
Date: Tue, 22 Mar 2011 13:11:13 +0300
Hello.
On 22-03-2011 13:06, Sriramakrishnan wrote:
With recent changes to the driver(switch to new cpdma layer),
the support for buffer descriptor address translation logic
is broken. This affects platforms
From: Nori, Sekhar nsek...@ti.com
Date: Tue, 22 Mar 2011 20:10:01 +0530
On Tue, Mar 22, 2011 at 18:01:03, Govindarajan, Sriramakrishnan wrote:
With recent changes to the driver(switch to new cpdma layer),
the support for buffer descriptor address translation logic
is broken. This affects
From: Cyril Chemparathy cy...@ti.com
Date: Fri, 03 Sep 2010 14:20:47 -0400
Hi Kevin,
[...]
Although am3517 (omap) board support code has been updated as needed,
emac does not work on this platform.
Just to clarify... did EMAC work on AM3517 before this series?
No. It didn't work
From: Sriramakrishnan s...@ti.com
Date: Thu, 29 Jul 2010 18:04:00 +0530
The EMAC modules control registers vary as per the version of the
EMAC module. EMAC_CTRL_EWCTL,EMAC_CTRL_EWINTTCNT are available
only on EMAC_VERSION_1. The emac_dump_regs() function accesses
these indiscriminately. This
From: Sriramakrishnan s...@ti.com
Date: Thu, 29 Jul 2010 18:03:59 +0530
The current implementation of NAPI poll function in the driver does not
service
Rx packets, error condition even if a single Tx packet gets serviced in
the napi poll call. This behavior severely affects performance for
From: Sriramakrishnan s...@ti.com
Date: Thu, 29 Jul 2010 18:03:58 +0530
DaVinci EMAC module includes an interrupt pacing block that can
be programmed to throttle the rate at which interrupts are
generated. This patch implements interrupt pacing logic that can
be controlled through the ethtool
From: Kevin Hilman khil...@deeprootsystems.com
Date: Fri, 12 Mar 2010 14:27:09 -0800
Sriramakrishnan s...@ti.com writes:
Source for the EMAC PHY clock can be different from the
module clock and driver needs to request/enable the EMAC
phy clock explicitly. This was not required earlier as on
From: Kevin Hilman khil...@deeprootsystems.com
Date: Thu, 11 Mar 2010 14:56:01 -0800
Sekhar Nori nsek...@ti.com writes:
The davinci emac driver uses some ARM specific DMA APIs
for cache coherency which have been removed from kernel
with the 2.6.34 merge.
Modify the driver to use the
From: Kevin Hilman khil...@deeprootsystems.com
Date: Fri, 12 Mar 2010 15:28:47 -0800
Chaithrika U S chaithr...@ti.com writes:
Migrate from the legacy PM hooks to use dev_pm_ops structure.
Signed-off-by: Chaithrika U S chaithr...@ti.com
Acked-by: Kevin Hilman khil...@deeprootsystems.com
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