Hi. On Wed, Jan 06, 2021 at 10:19:48AM -0800, Vagrant Cascadian wrote: > It is a little unclear weather there's a significance to the difference > between bl31.img and bl31.bin ... you might first try using the vendor > "bl31" instead, and then see if bl31.bin works; if the vendor bl31 works > and the one from arm-trusted-firmware do not, we might need to adjust > the arm-trusted-firmware package somehow...
So I have a good news, and a bad news. Starting with good - Debian u-boot works as intended, see attached bl31.img.log. Continuing with bad. Building upstream u-boot requires Linaro toolchain, there's no easy way about it short of rewriting the build system. Oh, and it's a cross-compilation, there's no easy possibility to build it on ARM64 natively. aml_encrypt_g12b is a statically linked AMD64 binary, so future u-boot updates on this board will be painful. One can try to cheat it with qemu-user-static, but it'll be fragile for obvious reasons. Next, bl31 filename does not seem to make a difference, but it's contents definitely are. I'm unsure what exactly gone wrong (bl31.bin from arm-trusted-firmware did initialize CPU after all), but u-boot didn't even launch - see bl31.bin.log. Reco
G12B:BL:6e7c85:7898ac;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0. bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:00008067 L3:04000000 B2:00002000 B1:e0f83180 TE: 417617 BL2 Built : 06:17:13, Jun 28 2019. g12b gf0505d7-dirty - qi.duan@droid13 Board ID = 4 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0006a787 DDR driver_vesion: LPDDR4_PHY_V_0_1_14 build time: Jun 28 2019 06:17:09 board id: 4 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 255 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==440 bdlr_100_min==440 bdlr_100_max==440 bdlr_100_cur==440 aft test bdlr_100_average==440 bdlr_100_min==440 bdlr_100_max==440 bdlr_100_cur==440 non-sec scramble use zero key ddr scramble enabled 100bdlr_step_size ps== 450 result report boot times 0Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00093400, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz] OPS=0x40 ring efuse init chipver efuse init 29 0a 40 00 01 26 0e 00 00 02 30 32 54 52 4d 50 [0.019859 Inits done] secure task start! high task start! low task start! run into bl31 NOTICE: BL31: v1.3(release):ab8811b NOTICE: BL31: Built : 15:03:31, Feb 12 2019 NOTICE: BL31: G12A normal boot! NOTICE: BL31: BL33 decompress pass ERROR: Error initializing runtime service opteed_fast U-Boot 2021.01-rc4+dfsg-2 (Jan 06 2021 - 01:51:36 +0000) odroid-n2 Model: Hardkernel ODROID-N2 SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) DRAM: 3.8 GiB MMC: sd@ffe05000: 0, mmc@ffe07000: 1 In: serial Out: serial Err: serial Net: eth0: ethernet@ff3f0000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... Found U-Boot script /boot/boot.scr
=> G12B:BL:6e7c85:7898ac;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0 bl2_stage_init 0x01 bl2_stage_init 0x81 hw id: 0x0000 - pwm id 0x01 bl2_stage_init 0xc1 bl2_stage_init 0x02 no sdio debug board detected L0:00000000 L1:00000703 L2:00008067 L3:04000000 B2:00002000 B1:e0f83180 TE: 374240 BL2 Built : 06:17:13, Jun 28 2019. g12b gf0505d7-dirty - qi.duan@droid13 Board ID = 4 Set A53 clk to 24M Set A73 clk to 24M Set clk81 to 24M A53 clk: 1200 MHz A73 clk: 1200 MHz CLK81: 166.6M smccc: 0005fe17 DDR driver_vesion: LPDDR4_PHY_V_0_1_14 build time: Jun 28 2019 06:17:09 board id: 4 Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0 fw parse done Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0 Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0 PIEI prepare done fastboot data load fastboot data verify verify result: 255 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg DDR4 probe ddr clk to 1320MHz Load ddrfw from SD, src: 0x00014200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of read enable training INFO : End of fine write leveling INFO : End of read dq deskew training INFO : End of MPR read delay center optimization INFO : End of Write leveling coarse delay INFO : End of write delay center optimization INFO : End of read delay center optimization INFO : End of max read latency training INFO : Training has run successfully! 1D training succeed Load ddrfw from SD, src: 0x00020200, des: 0xfffd0000, size: 0x0000c000, part: 0 Check phy result INFO : End of initialization INFO : End of 2D read delay Voltage center optimization INFO : End of 2D write delay Voltage center optimization INFO : Training has run successfully! R0_RxClkDly_Margin==82 ps 7 R0_TxDqDly_Margi==106 ps 9 R1_RxClkDly_Margin==0 ps 0 R1_TxDqDly_Margi==0 ps 0 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 2D training succeed auto size-- 65535DDR cs0 size: 2048MB DDR cs1 size: 2048MB DMC_DDR_CTRL: 00600024DDR size: 3928MB cs0 DataBus test pass cs1 DataBus test pass cs0 AddrBus test pass cs1 AddrBus test pass pre test bdlr_100_average==440 bdlr_100_min==440 bdlr_100_max==440 bdlr_100_cur==440 aft test bdlr_100_average==440 bdlr_100_min==440 bdlr_100_max==440 bdlr_100_cur==440 non-sec scramble use zero key ddr scramble enabled 100bdlr_step_size ps== 440 result report boot times 0Enable ddr reg access Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0 Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00073200, part: 0 0.0;M3 CHK:0;cm4_sp_mode 0 E30HDR MVN_1=0x00000000 MVN_2=0x00000000 [Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz] OPS=0x40 ring efuse init chipver efuse init 29 0a 40 00 01 26 0e 00 00 02 30 32 54 52 4d 50 [0.019859 Inits done] secure task start! high task start! low task start! rNOTICE: BL31: v2.4(debug): NOTICE: BL31: Built : 21:40:33, Jan 4 2021 INFO: ARM GICv2 driver initialized INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 819472 was applied INFO: BL31: cortex_a53: CPU workaround for 824069 was applied INFO: BL31: cortex_a53: CPU workaround for 827319 was applied INFO: BL31: cortex_a53: CPU workaround for 855873 was applied WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing! INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x1000000 INFO: SPSR = 0x3c9