tags 989840 + patch
thx
diff -Nru nvme-cli-1.12/debian/changelog nvme-cli-1.12/debian/changelog
--- nvme-cli-1.12/debian/changelog      2020-09-22 19:37:51.000000000 +0000
+++ nvme-cli-1.12/debian/changelog      2021-06-14 17:50:30.000000000 +0000
@@ -1,3 +1,10 @@
+nvme-cli (1.12-5+deb11u1) UNRELEASED; urgency=medium
+
+  * Fix issue where 'showregs' can cause certain Samsung devices
+    to go offline. (Closes: #989840)
+
+ -- dann frazier <da...@ubuntu.com>  Mon, 14 Jun 2021 11:50:30 -0600
+
 nvme-cli (1.12-5) unstable; urgency=medium
 
   * Add uuid-runtime as dependency. (Closes: #970637)
diff -Nru 
nvme-cli-1.12/debian/patches/Prevent-compiler-from-optimizing-mmio_read64-to-sing.patch
 
nvme-cli-1.12/debian/patches/Prevent-compiler-from-optimizing-mmio_read64-to-sing.patch
--- 
nvme-cli-1.12/debian/patches/Prevent-compiler-from-optimizing-mmio_read64-to-sing.patch
     1970-01-01 00:00:00.000000000 +0000
+++ 
nvme-cli-1.12/debian/patches/Prevent-compiler-from-optimizing-mmio_read64-to-sing.patch
     2021-06-14 16:51:31.000000000 +0000
@@ -0,0 +1,34 @@
+From 33e60ff64a043b189d2661543b417b21b6f3667b Mon Sep 17 00:00:00 2001
+From: Adam Judge <aju...@iol.unh.edu>
+Date: Tue, 9 Jun 2020 15:58:49 -0400
+Subject: [PATCH] Prevent compiler from optimizing mmio_read64 to single 64b
+ read
+
+Bug-Debian: https://bugs.debian.org/989840
+Bug-Ubuntu: https://bugs.launchpad.net/bugs/1931886
+Origin: 
https://github.com/linux-nvme/nvme-cli/commit/33e60ff64a043b189d2661543b417b21b6f3667b
+Last-Updated: 2021-06-14
+
+diff --git a/nvme-print.c b/nvme-print.c
+index fc8f99d..c0de928 100644
+--- a/nvme-print.c
++++ b/nvme-print.c
+@@ -1311,9 +1311,13 @@ static inline uint32_t mmio_read32(void *addr)
+ /* Access 64-bit registers as 2 32-bit; Some devices fail 64-bit MMIO. */
+ static inline __u64 mmio_read64(void *addr)
+ {
+-      __le32 *p = addr;
++      const volatile __u32 *p = addr;
++      __u32 low, high;
++
++      low = le32_to_cpu(*p);
++      high = le32_to_cpu(*(p + 1));
+ 
+-      return le32_to_cpu(*p) | ((uint64_t)le32_to_cpu(*(p + 1)) << 32);
++      return ((__u64) high << 32) | low;
+ }
+ 
+ static void json_ctrl_registers(void *bar)
+-- 
+2.32.0
+
diff -Nru 
nvme-cli-1.12/debian/patches/nvme-print-split-pmrmsc-into-pmrmscl-and-pmrmscu.patch
 
nvme-cli-1.12/debian/patches/nvme-print-split-pmrmsc-into-pmrmscl-and-pmrmscu.patch
--- 
nvme-cli-1.12/debian/patches/nvme-print-split-pmrmsc-into-pmrmscl-and-pmrmscu.patch
 1970-01-01 00:00:00.000000000 +0000
+++ 
nvme-cli-1.12/debian/patches/nvme-print-split-pmrmsc-into-pmrmscl-and-pmrmscu.patch
 2021-06-14 16:52:09.000000000 +0000
@@ -0,0 +1,139 @@
+From d43d545a68cc6cea5ac78fda4edeedf3b5198847 Mon Sep 17 00:00:00 2001
+From: Gollu Appalanaidu <anaidu.go...@samsung.com>
+Date: Sat, 27 Feb 2021 01:23:44 +0530
+Subject: [PATCH] nvme-print: split pmrmsc into pmrmscl and pmrmscu
+
+Split the PMR Memory Space Control register 64 bits into
+PMR Memory Space Control Lower and Upper 32 bits each as
+per NVM Express Spec. 1.4b changes.
+
+Signed-off-by: Gollu Appalanaidu <anaidu.go...@samsung.com>
+[dannf: Backported to 1.12]
+
+Bug-Debian: https://bugs.debian.org/989840
+Bug-Ubuntu: https://bugs.launchpad.net/bugs/1931886
+Origin: 
https://github.com/linux-nvme/nvme-cli/commit/d43d545a68cc6cea5ac78fda4edeedf3b5198847
+Last-Updated: 2021-06-14
+
+Index: nvme-cli-1.12/linux/nvme.h
+===================================================================
+--- nvme-cli-1.12.orig/linux/nvme.h
++++ nvme-cli-1.12/linux/nvme.h
+@@ -172,7 +172,8 @@ enum {
+       NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
+       NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity 
Buffer Size */
+       NVME_REG_PMRSWTP= 0x0e10,       /* Persistent Memory Region Sustained 
Write Throughput */
+-      NVME_REG_PMRMSC = 0x0e14,       /* Persistent Memory Region Controller 
Memory Space Control */
++      NVME_REG_PMRMSCL= 0x0e14,       /* Persistent Memory Region Controller 
Memory Space Control Lower */
++      NVME_REG_PMRMSCU= 0x0e18,       /* Persistent Memory Region Controller 
Memory Space Control Upper*/
+       NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
+ };
+ 
+Index: nvme-cli-1.12/nvme-print.c
+===================================================================
+--- nvme-cli-1.12.orig/nvme-print.c
++++ nvme-cli-1.12/nvme-print.c
+@@ -1293,12 +1293,18 @@ static void nvme_show_registers_pmrswtp(
+               nvme_register_pmr_pmrszu_to_string(pmrswtp & 0x0000000f));
+ }
+ 
+-static void nvme_show_registers_pmrmsc(uint64_t pmrmsc)
++static void nvme_show_registers_pmrmscl(uint32_t pmrmscl)
+ {
+-      printf("\tController Base Address (CBA)         : %" PRIx64 "\n",
+-              (pmrmsc & 0xfffffffffffff000) >> 12);
+-      printf("\tController Memory Space Enable (CMSE) : %" PRIx64 "\n\n",
+-              (pmrmsc & 0x0000000000000002) >> 1);
++      printf("\tController Base Address         (CBA): %#x\n",
++              (pmrmscl & 0xfffff000) >> 12);
++      printf("\tController Memory Space Enable (CMSE): %#x\n\n",
++              (pmrmscl & 0x00000002) >> 1);
++}
++
++static void nvme_show_registers_pmrmscu(uint32_t pmrmscu)
++{
++      printf("\tController Base Address         (CBA): %#x\n",
++              pmrmscu);
+ }
+ 
+ static inline uint32_t mmio_read32(void *addr)
+@@ -1322,9 +1328,10 @@ static inline __u64 mmio_read64(void *ad
+ 
+ static void json_ctrl_registers(void *bar)
+ {
+-      uint64_t cap, asq, acq, bpmbl, cmbmsc, pmrmsc;
++      uint64_t cap, asq, acq, bpmbl, cmbmsc;
+       uint32_t vs, intms, intmc, cc, csts, nssr, aqa, cmbsz, cmbloc,
+-              bpinfo, bprsel, cmbsts, pmrcap, pmrctl, pmrsts, pmrebs, pmrswtp;
++              bpinfo, bprsel, cmbsts, pmrcap, pmrctl, pmrsts, pmrebs, pmrswtp,
++              pmrmscl, pmrmscu;
+       struct json_object *root;
+ 
+       cap = mmio_read64(bar + NVME_REG_CAP);
+@@ -1349,7 +1356,8 @@ static void json_ctrl_registers(void *ba
+       pmrsts = mmio_read32(bar + NVME_REG_PMRSTS);
+       pmrebs = mmio_read32(bar + NVME_REG_PMREBS);
+       pmrswtp = mmio_read32(bar + NVME_REG_PMRSWTP);
+-      pmrmsc = mmio_read64(bar + NVME_REG_PMRMSC);
++      pmrmscl = mmio_read32(bar + NVME_REG_PMRMSCL);
++      pmrmscu = mmio_read32(bar + NVME_REG_PMRMSCU);
+ 
+       root = json_create_object();
+       json_object_add_value_uint(root, "cap", cap);
+@@ -1374,7 +1382,8 @@ static void json_ctrl_registers(void *ba
+       json_object_add_value_int(root, "pmrsts", pmrsts);
+       json_object_add_value_int(root, "pmrebs", pmrebs);
+       json_object_add_value_int(root, "pmrswtp", pmrswtp);
+-      json_object_add_value_uint(root, "pmrmsc", pmrmsc);
++      json_object_add_value_uint(root, "pmrmscl", pmrmscl);
++      json_object_add_value_uint(root, "pmrmscu", pmrmscu);
+       json_print_object(root, NULL);
+       printf("\n");
+       json_free_object(root);
+@@ -1383,9 +1392,10 @@ static void json_ctrl_registers(void *ba
+ void nvme_show_ctrl_registers(void *bar, bool fabrics, enum nvme_print_flags 
flags)
+ {
+       const unsigned int reg_size = 0x50;  /* 00h to 4Fh */
+-      uint64_t cap, asq, acq, bpmbl, cmbmsc, pmrmsc;
++      uint64_t cap, asq, acq, bpmbl, cmbmsc;
+       uint32_t vs, intms, intmc, cc, csts, nssr, aqa, cmbsz, cmbloc, bpinfo,
+-               bprsel, cmbsts, pmrcap, pmrctl, pmrsts, pmrebs, pmrswtp;
++               bprsel, cmbsts, pmrcap, pmrctl, pmrsts, pmrebs, pmrswtp,
++               pmrmscl, pmrmscu;
+       int human = flags & VERBOSE;
+ 
+       if (flags & BINARY)
+@@ -1415,7 +1425,8 @@ void nvme_show_ctrl_registers(void *bar,
+       pmrsts = mmio_read32(bar + NVME_REG_PMRSTS);
+       pmrebs = mmio_read32(bar + NVME_REG_PMREBS);
+       pmrswtp = mmio_read32(bar + NVME_REG_PMRSWTP);
+-      pmrmsc = mmio_read64(bar + NVME_REG_PMRMSC);
++      pmrmscl = mmio_read32(bar + NVME_REG_PMRMSCL);
++      pmrmscu = mmio_read32(bar + NVME_REG_PMRMSCU);
+ 
+       if (human) {
+               if (cap != 0xffffffff) {
+@@ -1494,8 +1505,11 @@ void nvme_show_ctrl_registers(void *bar,
+                       printf("pmrswtp : %x\n", pmrswtp);
+                       nvme_show_registers_pmrswtp(pmrswtp);
+ 
+-                      printf("pmrmsc  : %"PRIx64"\n", pmrmsc);
+-                      nvme_show_registers_pmrmsc(pmrmsc);
++                      printf("pmrmscl : %#x\n", pmrmscl);
++                      nvme_show_registers_pmrmscl(pmrmscl);
++
++                      printf("pmrmscu : %#x\n", pmrmscu);
++                      nvme_show_registers_pmrmscu(pmrmscu);
+               }
+       } else {
+               if (cap != 0xffffffff)
+@@ -1526,7 +1540,8 @@ void nvme_show_ctrl_registers(void *bar,
+                       printf("pmrsts  : %x\n", pmrsts);
+                       printf("pmrebs  : %x\n", pmrebs);
+                       printf("pmrswtp : %x\n", pmrswtp);
+-                      printf("pmrmsc  : %"PRIx64"\n", pmrmsc);
++                      printf("pmrmscl : %#x\n", pmrmscl);
++                      printf("pmrmscu : %#x\n", pmrmscu);
+               }
+       }
+ }
diff -Nru nvme-cli-1.12/debian/patches/series 
nvme-cli-1.12/debian/patches/series
--- nvme-cli-1.12/debian/patches/series 1970-01-01 00:00:00.000000000 +0000
+++ nvme-cli-1.12/debian/patches/series 2021-06-14 15:03:42.000000000 +0000
@@ -0,0 +1,2 @@
+Prevent-compiler-from-optimizing-mmio_read64-to-sing.patch
+nvme-print-split-pmrmsc-into-pmrmscl-and-pmrmscu.patch

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