Package: valgrind
Version: 1:3.14.0-3
Severity: normal
Tags: patch
Hi!
I'm afraid that valgrind doesn't recognize cache flush instructons on
arm64, and will make the program being run crash upon encountering any
of them other than "dc cvau".
Patch attached.
Meow!
-- System Information:
Debian Release: 10.0
APT prefers unstable
APT policy: (500, 'unstable'), (1, 'experimental')
Architecture: arm64 (aarch64)
Kernel: Linux 4.4.167-1213-rockchip-ayufan-g34ae07687fce (SMP w/6 CPU cores)
Locale: LANG=C.UTF-8, LC_CTYPE=C.UTF-8 (charmap=UTF-8), LANGUAGE=C.UTF-8
(charmap=UTF-8)
Shell: /bin/sh linked to /bin/dash
Init: sysvinit (via /sbin/init)
Versions of packages valgrind depends on:
ii libc6 2.28-10
ii libc6-dbg 2.28-10
Versions of packages valgrind recommends:
ii gdb 8.2.1-2
pn valgrind-dbg <none>
Versions of packages valgrind suggests:
pn alleyoop <none>
pn kcachegrind <none>
pn valgrind-mpi <none>
pn valkyrie <none>
-- no debconf information
>From e2d680a06acc7a02ec9a784597760a0a437119b4 Mon Sep 17 00:00:00 2001
From: Adam Borowski <kilob...@angband.pl>
Date: Wed, 19 Jun 2019 01:41:22 +0200
Subject: [PATCH] Fix SIGILL on dcache flushes on arm64.
Only "dc cvau" was supported; the list is:
* cvau: to Point of Unification (icache = dcache, usu. L2)
* cvac: to Point of Coherence (all hardware that can access memory)
* cvap: to Point of Persistence (v8.2, usu. memory controller)
* cvadp: to Point of Deep Persistence (v8.5)
* civac: cvac + invalidate
For tools other than cachegrind, we don't care about which exact flush
is used; this patch doesn't yet teach cachegrind that -- but at least
there's no crash, and all other tools work right.
---
VEX/priv/guest_arm64_toIR.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 476eedc..72526c9 100644
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -7097,10 +7097,19 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres,
UInt insn,
return True;
}
+ /* ------------------ DC_CVAC ------------------ */
/* ------------------ DC_CVAU ------------------ */
- /* D5 0B 7B 001 Rt dc cvau, rT
+ /* ------------------ DC_CVAP ------------------ */
+ /* ------------------ DC_CVADP ----------------- */
+ /* ------------------ DC_CIVAC ----------------- */
+ /* D5 0B 7A 001 Rt dc cvac, rT
+ D5 0B 7B 001 Rt dc cvau, rT
+ D5 0B 7C 001 Rt dc cvap, rT
+ D5 0B 7D 001 Rt dc cvadp, rT
+ D5 0B 7E 001 Rt dc civac, rT
+ 78, 79 and 7F are unassigned -- speculate they'll also be dcache flushes.
*/
- if ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20) {
+ if ((INSN(31,0) & 0xFFFFF8E0) == 0xD50B7820) {
/* Exactly the same scheme as for IC IVAU, except we observe the
dMinLine size, and request an Ijk_FlushDCache instead of
Ijk_InvalICache. */
--
2.20.1
