Package: wnpp Severity: wishlist Owner: Ruben Undheim <ruben.undh...@gmail.com>
* Package name : opensta Version : 0.0 - GIT HEAD Upstream Author : Parallax Software, Inc. * URL : https://github.com/abk-openroad/OpenSTA * License : GPL-3+ Programming Lang: C++ Description : Gate-level Static Timing Analyzer After synthesis, place and route of a digital circuit, it is necessary to verify the timing of the design. OpenSTA is a tool for doing exactly that. It has a TCL interface for entering commands for analysing designs. It typically takes as input a verilog netlist, a liberty file, and other parasitics information from the placed and routed design. There is one similar, but more basic, tool called 'vesta' inside the qflow package already in Debian, but OpenSTA is a more complete solution. I plan to maintain it in the Debian Electronics team.