Re: Intel CPU architecture

2016-03-02 Thread Edmon Begoli
Yes (about JICS/NICS) There are many platforms here. Beacon is probably better because it is a large memory machine, and it can be allocated more easily: https://www.nics.tennessee.edu/beacon I also have authority to commit 1000s of hours of Beacon to the Arrow project, if needed. Titan is li

Re: Intel CPU architecture

2016-03-02 Thread Venkat Krishnamurthy
Is JICS the Joint Institute for Comp Sciences at ORNL/UT? If so, is one of the target platforms Titan@ORNL? On Wed, Mar 2, 2016 at 2:56 PM, Edmon Begoli wrote: > Would you guys be interested in perhaps having a Hangout with my team from > JICS/NICS? > > We have some major experts and research th

Re: Intel CPU architecture

2016-03-02 Thread Edmon Begoli
Would you guys be interested in perhaps having a Hangout with my team from JICS/NICS? We have some major experts and research thrusts in this area (code optimizations for Intel chipsets, MKL and other kernels, memory/IO optimizations, etc) We are a research shop. People just get excited over thin

Re: Intel CPU architecture

2016-03-02 Thread Wes McKinney
hi Edmon, Since Arrow arrays are arranged with like-data in contiguous memory regions (for example, in an array of strings, the UTF8 bytes are all laid out in contiguous memory -- see https://github.com/apache/arrow/blob/master/format/Layout.md), it is cache-friendly for scan operations and amenab

Intel CPU architecture

2016-03-02 Thread Edmon Begoli
Hey folks, How could I get more details on what and how Arrow uses Intel CPUs for whatever computational advantage? At JICS, we run very large experimental Intel HPC systems, and I would like to learn how can we possibly run some interesting Arrow on Intel CPUs experiments. Thank you, Edmon