[dpdk-dev] Why doesn`t test-acl work when IP filed is RTE_ACL_FIELD_TYPE_RANGE?

ok, I notice now that my rule file was wrong. I modified the range of SIP/DIP like the value of SIP/DIP (like 192.168.10.100), and it works!

[dpdk-dev] Why doesn`t test-acl work when IP filed is RTE_ACL_FIELD_TYPE_RANGE?

hi, I ran test-acl without any modification and it worked well, and I modified test-acl like below: { //.type = RTE_ACL_FIELD_TYPE_MASK, .type = RTE_ACL_FIELD_TYPE_RANGE, .size = sizeof(uint32_t), .field_index = SRC_FIELD_IPV4, .input_index = RTE_

[dpdk-dev] Intel 82599 tx_conf setting

Hi I've read the Intel 82599 official manual and I found that optimal PTHRESH is the tx descriptor buffer size - N (N is CPU cache line divided by 16). 1. I guess the size of the tx descriptor buffer is 128. Isn't it right? Where is the size of the tx descriptor buffer in the official manual

[dpdk-dev] Relationship between H/W ring and S/W ring

ring_dma_zone_reserve function, and its size is RX_RING_SZ. I don't think the RX_RING_SZ is configurable but it is fixed value. Is there any other code configuring the size of H/W ring? 2014-10-30 ?? 6:55? Bruce Richardson ?(?) ? ?: > On Thu, Oct 30, 2014 at 04:32:16PM +0900, Gyumin wrote: >>

[dpdk-dev] Relationship between H/W ring and S/W ring

Hi I`m reading the ixgbe code especially about H/W ring and S/W ring. Is the relationship between H/W ring and S/W ring one-to-one mapping? As far as I know, H/W ring size is determined in the code(hard coded) while S/W ring size is determined in port configuration time. In the ixgbe_rx_alloc_bu