[dpdk-dev] [PATCH v1 6/6] crypto/ccp: updating ccp document
From: Amaranath Somalapuram Signed-off-by: Amaranath Somalapuram --- doc/guides/cryptodevs/ccp.rst | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/doc/guides/cryptodevs/ccp.rst b/doc/guides/cryptodevs/ccp.rst index 034d20367..a43fe92de 100644 --- a/doc/guides/cryptodevs/ccp.rst +++ b/doc/guides/cryptodevs/ccp.rst @@ -109,14 +109,14 @@ To validate ccp pmd, l2fwd-crypto example can be used with following command: .. code-block:: console - sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 - --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC - --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f - --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff - --auth_op GENERATE --auth_algo SHA1_HMAC - --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 +sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 +--chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo aes-cbc +--cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f +--cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff +--auth_op GENERATE --auth_algo sha1-hmac +--auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 +:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 The CCP PMD also supports computing authentication over CPU with cipher offloaded to CCP. To enable this feature, pass an additional argument as ccp_auth_opt=1 to --vdev parameters as @@ -124,14 +124,14 @@ following: .. code-block:: console - sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp,ccp_auth_opt=1" -- -p 0x1 - --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC - --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f - --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff - --auth_op GENERATE --auth_algo SHA1_HMAC - --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 +sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp,ccp_auth_opt=1" -- -p 0x1 +--chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo aes-cbc +--cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f +--cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff +--auth_op GENERATE --auth_algo sha1-hmac +--auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 +:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 Limitations --- -- 2.17.1
Re: [dpdk-dev] [PATCH v2 0/9] net/qede/base: update FW to 8.40.25.0
On Mon, Oct 7, 2019 at 1:44 AM Rasesh Mody wrote: > > Hi, > > This patch series updates the FW to 8.40.25.0 and includes corresponding > base driver changes. It also includes some enhancements and fixes. > The PMD version is bumped to 2.11.0.1. > > v2: >Addressed checkpatch issues >9/9 - print adapter info for any failure (not just probe) during init > > Thanks! > -Rasesh Series applied to dpdk-next-net-mrvl/master. Thanks. > > Rasesh Mody (9): > net/qede/base: calculate right page index for PBL chains > net/qede/base: change MFW mailbox command log verbosity > net/qede/base: lock entire QM reconfiguration flow > net/qede/base: rename HSI datatypes and funcs > net/qede/base: update rt defs NVM cfg and mcp code > net/qede/base: move dmae code to HSI > net/qede/base: update HSI code > net/qede/base: update the FW to 8.40.25.0 > net/qede: print adapter info during init failure > > drivers/net/qede/base/bcm_osal.c |1 + > drivers/net/qede/base/bcm_osal.h |5 +- > drivers/net/qede/base/common_hsi.h| 257 +-- > drivers/net/qede/base/ecore.h | 77 +- > drivers/net/qede/base/ecore_chain.h | 84 +- > drivers/net/qede/base/ecore_cxt.c | 520 --- > drivers/net/qede/base/ecore_cxt.h | 12 + > drivers/net/qede/base/ecore_dcbx.c|7 +- > drivers/net/qede/base/ecore_dev.c | 753 + > drivers/net/qede/base/ecore_dev_api.h | 92 -- > drivers/net/qede/base/ecore_gtt_reg_addr.h| 42 +- > drivers/net/qede/base/ecore_gtt_values.h | 18 +- > drivers/net/qede/base/ecore_hsi_common.h | 1134 +++--- > drivers/net/qede/base/ecore_hsi_debug_tools.h | 475 +++--- > drivers/net/qede/base/ecore_hsi_eth.h | 1386 - > drivers/net/qede/base/ecore_hsi_init_func.h | 25 +- > drivers/net/qede/base/ecore_hsi_init_tool.h | 42 +- > drivers/net/qede/base/ecore_hw.c | 68 +- > drivers/net/qede/base/ecore_hw.h | 98 +- > drivers/net/qede/base/ecore_init_fw_funcs.c | 718 - > drivers/net/qede/base/ecore_init_fw_funcs.h | 107 +- > drivers/net/qede/base/ecore_init_ops.c| 66 +- > drivers/net/qede/base/ecore_init_ops.h| 12 +- > drivers/net/qede/base/ecore_int.c | 131 +- > drivers/net/qede/base/ecore_int.h |4 +- > drivers/net/qede/base/ecore_int_api.h | 13 +- > drivers/net/qede/base/ecore_iov_api.h |4 +- > drivers/net/qede/base/ecore_iro.h | 320 ++-- > drivers/net/qede/base/ecore_iro_values.h | 336 ++-- > drivers/net/qede/base/ecore_l2.c | 10 +- > drivers/net/qede/base/ecore_l2_api.h |2 + > drivers/net/qede/base/ecore_mcp.c | 296 ++-- > drivers/net/qede/base/ecore_mcp.h |9 +- > drivers/net/qede/base/ecore_proto_if.h|1 + > drivers/net/qede/base/ecore_rt_defs.h | 870 +-- > drivers/net/qede/base/ecore_sp_commands.c | 15 +- > drivers/net/qede/base/ecore_spq.c | 55 +- > drivers/net/qede/base/ecore_sriov.c | 178 ++- > drivers/net/qede/base/ecore_sriov.h |4 +- > drivers/net/qede/base/ecore_vf.c | 18 +- > drivers/net/qede/base/eth_common.h| 101 +- > drivers/net/qede/base/mcp_public.h| 59 +- > drivers/net/qede/base/nvm_cfg.h | 909 ++- > drivers/net/qede/base/reg_addr.h | 75 +- > drivers/net/qede/qede_ethdev.c| 81 +- > drivers/net/qede/qede_ethdev.h| 21 +- > drivers/net/qede/qede_main.c |2 +- > drivers/net/qede/qede_rxtx.c | 28 +- > 48 files changed, 5493 insertions(+), 4048 deletions(-) > > -- > 2.18.0 >
Re: [dpdk-dev] packet data access bug in bpf and pdump libs
> -Original Message-
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev,
> Konstantin
> Sent: Thursday, October 10, 2019 5:37 PM
>
> > -Original Message-
> > From: Morten Brørup [mailto:m...@smartsharesystems.com]
> > Sent: Thursday, October 10, 2019 8:30 AM
> >
> > > -Original Message-
> > > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Stephen
> Hemminger
> > > Sent: Wednesday, October 9, 2019 7:25 PM
> > >
> > > On Wed, 9 Oct 2019 17:20:58 +0200
> > > Morten Brørup wrote:
> > >
> > > > > -Original Message-
> > > > > From: Stephen Hemminger [mailto:step...@networkplumber.org]
> > > > > Sent: Wednesday, October 9, 2019 5:15 PM
> > > > >
> > > > > On Wed, 9 Oct 2019 17:06:24 +0200
> > > > > Morten Brørup wrote:
> > > > >
> > > > > > > -Original Message-
> > > > > > > From: Stephen Hemminger [mailto:step...@networkplumber.org]
> > > > > > > Sent: Wednesday, October 9, 2019 5:02 PM
> > > > > > >
> > > > > > > On Wed, 9 Oct 2019 11:11:46 +
> > > > > > > "Ananyev, Konstantin" wrote:
> > > > > > >
> > > > > > > > Hi Morten,
> > > > > > > >
> > > > > > > > >
> > > > > > > > > Hi Konstantin and Stephen,
> > > > > > > > >
> > > > > > > > > I just noticed the same bug in your bpf and pcap
> libraries:
> > > > > > > > >
> > > > > > > > > You are using rte_pktmbuf_mtod(), but should be using
> > > > > > > rte_pktmbuf_read(). Otherwise you cannot read data across
> > > multiple
> > > > > > > segments.
> > > > > > > >
> > > > > > > > In plain data buffer mode expected input for BPF program
> is
> > > start
> > > > > of
> > > > > > > first segment packet data.
> > > > > > > > Other segments are simply not available to BPF program in
> > > that
> > > > > mode.
> > > > > > > > AFAIK, cBPF uses the same model.
> > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > Med venlig hilsen / kind regards
> > > > > > > > > - Morten Brørup
> > > > > > > >
> > > > > > >
> > > > > > > For packet capture, the BPF program is only allowed to look
> at
> > > > > first
> > > > > > > segment.
> > > > > > > pktmbuf_read is expensive and can cause a copy.
> > > > > >
> > > > > > It is only expensive if going beyond the first segment:
> > > > > >
> > > > > > static inline const void *rte_pktmbuf_read(const struct
> rte_mbuf
> > > *m,
> > > > > > uint32_t off, uint32_t len, void *buf)
> > > > > > {
> > > > > > if (likely(off + len <= rte_pktmbuf_data_len(m)))
> > > > > > return rte_pktmbuf_mtod_offset(m, char *, off);
> > > > > > else
> > > > > > return __rte_pktmbuf_read(m, off, len, buf);
> > > > > > }
> > > > >
> > > > > But it would mean potentially big buffer on the stack (in case)
> > > >
> > > > No, the buffer only needs to be the size of the accessed data. I
> use
> > > it like this:
> > > >
> > > > char buffer[sizeof(uint32_t)];
> > > >
> > > > for (;; pc++) {
> > > > switch (pc->code) {
> > > > case BPF_LD_ABS_32:
> > > > p = rte_pktmbuf_read(m, pc->k, sizeof(uint32_t),
> buffer);
> > > > if (unlikely(p == NULL)) return 0; /* Attempting to
> read
> > > beyond packet. Bail out. */
> > > > a = rte_be_to_cpu_32(*(const uint32_t *)p);
> > > > continue;
> > > > case BPF_LD_ABS_16:
> > > > p = rte_pktmbuf_read(m, pc->k, sizeof(uint16_t),
> buffer);
> > > > if (unlikely(p == NULL)) return 0; /* Attempting to
> read
> > > beyond packet. Bail out. */
> > > > a = rte_be_to_cpu_16(*(const uint16_t *)p);
> > > > continue;
> > > >
> > >
> > > Reading down the chain of mbuf segments to find a uint32_t (and
> that
> > > potentially crosses)
> > > seems like a waste.
>
> +1
> Again just imagine how painful it would be to support it in JIT...
>
Compiling the BPF_LD_ABS instruction into a function call (i.e. a series of
instructions) instead of a single instruction doesn't seem like a showstopper
to me. The major modification is probably in the bpf library, passing the mbuf
instead of a pointer to the data of the first segment.
> Another thing - in librte_bpf, if RTE_BPF_ARG_PTR is used,
> it means that input parameter for exec/jit is just a plain data buffer
> and it doesn’t
> make any assumptions about it (mbuf or not, etc.).
>
> Though there is a possibility to access mbuf metadata
> and call rte_pktmbuf_read() or any other functions from your eBPF
> code,
> but for that you need to specify RTE_BPF_ARG_PTR_MBUF at load stage.
>
So one way of solving it is making an cBPF to eBPF converter that does this
trickery, if conversion to eBPF is the path taken. Although that could be
harder to implement than simply adding a cBPF processor (or JIT compiler)
directly in the bpf library.
C is not C++, and perhaps cBPF and eBPF do not have as many things in common as
their names might suggest.
> > >
> >
> > Slow and painful is the only way to read beyond the first segment, I
> agree.
> >
> > But when reading from the
Re: [dpdk-dev] [PATCH] net/octeontx2: add set supported types op
On Tue, Oct 8, 2019 at 2:30 PM wrote:
>
> From: Pavan Nikhilesh
>
> Add support to set supported ptypes for octeontx2.
>
> Signed-off-by: Pavan Nikhilesh
> ---
> This patch depends on the following series
> http://patches.dpdk.org/project/dpdk/list/?series=6715
>
> drivers/net/octeontx2/otx2_ethdev.c | 1 +
> drivers/net/octeontx2/otx2_ethdev.h | 2 ++
> drivers/net/octeontx2/otx2_ethdev_devargs.c | 21 -
> drivers/net/octeontx2/otx2_lookup.c | 15 +++
Remove following from doc/guides/nics/octeontx2.rst as well.
- ``HW offload ptype parsing disable`` (default ``0``)
Packet type parsing is HW offloaded by default and this feature may
be toggled
using ``ptype_disable`` ``devargs`` parameter.
> 4 files changed, 18 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/net/octeontx2/otx2_ethdev.c
> b/drivers/net/octeontx2/otx2_ethdev.c
> index b84128fef..5ee0e382d 100644
> --- a/drivers/net/octeontx2/otx2_ethdev.c
> +++ b/drivers/net/octeontx2/otx2_ethdev.c
> @@ -1619,6 +1619,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
> .dev_set_link_up = otx2_nix_dev_set_link_up,
> .dev_set_link_down= otx2_nix_dev_set_link_down,
> .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
> + .dev_supported_ptypes_set = otx2_nix_supported_ptypes_set,
> .dev_reset= otx2_nix_dev_reset,
> .stats_get= otx2_nix_dev_stats_get,
> .stats_reset = otx2_nix_dev_stats_reset,
> +int
> +otx2_nix_supported_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t
> ptype_mask)
> +{
> + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
> +
> + if (!ptype_mask)
> + dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
> + else
> + dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
Prefer to have positive logic.
if (ptype_mask)
dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;
else
dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;
> +
> + otx2_eth_set_rx_function(eth_dev);
> +
> + return 0;
> +}
> +
> /*
> * +-- +-- +
> * | | IL4 | IL3| IL2 | TU | L4 | L3 | L2 |
> --
> 2.17.1
>
[dpdk-dev] [PATCH v8 00/18] add PCIe AER disable and IRQ support for ipn3ke
This patch set adds PCIe AER disable and IRQ support for ipn3ke. Disable PCIe AER is very useful when FPGA reload. IRQ is used very widely in interrupt process. For ipn3ke is connect to CPU with PCIe switch, driver needs to scan all PCIe devices of ipn3ke, it also can get all i40e of card, so ipn3ke driver doesn't need to take some configuration of i40e. v8 updates: = - add multiple cards support. v7 updates: == - rename function i40e_set_switch_dev to rte_pmd_i40e_set_switch_dev and move it to rte_pmd_i40e.c since it is declared at rte_pmd_i40e.h - function rte_pmd_i40e_set_switch_dev works as an external API, use port_id but not rte_eth_dev as parameter. - add doxygen header here for the new API. - update the rte_pmd_i40e_version.map. - fix coding style issue. - enable CONFIG_RTE_EAL_VFIO in linux environment to build irq support. - for functions with a lot of similarity, extract out common function to reduce duplication. v6 updates: = - correct author information. - correct typo in commit message and remove Gerrit Change-Id's before submitting upstream v5 updates: == - add lightweight fpga image support. in lightweight fpga image mode, ipn3ke representor will not be probed. v4 updates: === - align with new naming standard. v3 updates: === - Add FPGA network side port MTU configuration v2 updates: === - Add AUX feature support Andy Pei (2): net/i40e: i40e support ipn3ke FPGA port bonding raw/ifpga: add lightweight fpga image support Rosen Xu (3): raw/ifpga: add SEU error handler raw/ifpga: add PCIe BDF devices tree scan net/ipn3ke: remove configuration for i40e port bonding Tianfei zhang (13): raw/ifpga/base: add irq support raw/ifpga/base: clear pending bit raw/ifpga/base: add SEU error support raw/ifpga/base: add device tree support raw/ifpga/base: align the send buffer for SPI raw/ifpga/base: add sensor support raw/ifpga/base: introducing sensor APIs raw/ifpga/base: update SEU register definition raw/ifpga/base: add secure support raw/ifpga/base: configure FEC mode raw/ifpga/base: clean fme errors raw/ifpga/base: add new API get board info raw/ifpga/base: add multiple cards support config/common_base| 4 +- config/common_linux | 6 + drivers/net/i40e/base/i40e_type.h | 3 + drivers/net/i40e/i40e_ethdev.c| 6 + drivers/net/i40e/rte_pmd_i40e.c | 21 + drivers/net/i40e/rte_pmd_i40e.h | 18 + drivers/net/i40e/rte_pmd_i40e_version.map | 8 +- drivers/net/ipn3ke/Makefile | 2 + drivers/net/ipn3ke/ipn3ke_ethdev.c| 289 ++--- drivers/net/ipn3ke/ipn3ke_representor.c | 8 +- drivers/raw/ifpga/base/ifpga_api.c| 21 + drivers/raw/ifpga/base/ifpga_defines.h| 75 ++- drivers/raw/ifpga/base/ifpga_feature_dev.c| 59 ++ drivers/raw/ifpga/base/ifpga_feature_dev.h| 3 + drivers/raw/ifpga/base/ifpga_fme.c| 166 - drivers/raw/ifpga/base/ifpga_fme_error.c | 74 ++- drivers/raw/ifpga/base/ifpga_hw.h | 2 +- drivers/raw/ifpga/base/ifpga_port.c | 18 + drivers/raw/ifpga/base/ifpga_port_error.c | 19 + drivers/raw/ifpga/base/opae_debug.c | 3 + drivers/raw/ifpga/base/opae_hw_api.c | 137 drivers/raw/ifpga/base/opae_hw_api.h | 26 + drivers/raw/ifpga/base/opae_ifpga_hw_api.h| 2 + drivers/raw/ifpga/base/opae_intel_max10.c | 598 +- drivers/raw/ifpga/base/opae_intel_max10.h | 157 - drivers/raw/ifpga/base/opae_osdep.h | 7 +- drivers/raw/ifpga/base/opae_spi.c | 1 + drivers/raw/ifpga/base/opae_spi.h | 25 +- drivers/raw/ifpga/base/opae_spi_transaction.c | 40 +- drivers/raw/ifpga/ifpga_rawdev.c | 860 +- drivers/raw/ifpga/ifpga_rawdev.h | 16 + mk/rte.app.mk | 2 +- 32 files changed, 2277 insertions(+), 399 deletions(-) -- 1.8.3.1
[dpdk-dev] [PATCH v8 01/18] net/i40e: i40e support ipn3ke FPGA port bonding
In ipn3ke, each FPGA network side port bonding to an i40e pf,
each i40e pf link status should get data from FPGA network,
side port. This patch provide bonding relationship.
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/net/i40e/base/i40e_type.h | 3 +++
drivers/net/i40e/i40e_ethdev.c| 6 ++
drivers/net/i40e/rte_pmd_i40e.c | 21 +
drivers/net/i40e/rte_pmd_i40e.h | 18 ++
drivers/net/i40e/rte_pmd_i40e_version.map | 8 +++-
5 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/net/i40e/base/i40e_type.h
b/drivers/net/i40e/base/i40e_type.h
index 112866b..06863d7 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -660,6 +660,9 @@ struct i40e_hw {
struct i40e_nvm_info nvm;
struct i40e_fc_info fc;
+ /* switch device is used to get link status when i40e is in ipn3ke */
+ struct rte_eth_dev *switch_dev;
+
/* pci info */
u16 device_id;
u16 vendor_id;
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 2ca14da..bae1ca2 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -1390,6 +1390,9 @@ static inline void i40e_config_automask(struct i40e_pf
*pf)
hw->adapter_stopped = 0;
hw->adapter_closed = 0;
+ /* Init switch device pointer */
+ hw->switch_dev = NULL;
+
/*
* Switch Tag value should not be identical to either the First Tag
* or Second Tag values. So set something other than common Ethertype
@@ -2901,6 +2904,9 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
else
update_link_aq(hw, &link, enable_lse, wait_to_complete);
+ if (hw->switch_dev)
+ rte_eth_linkstatus_get(hw->switch_dev, &link);
+
ret = rte_eth_linkstatus_set(dev, &link);
i40e_notify_all_vfs_link_status(dev);
diff --git a/drivers/net/i40e/rte_pmd_i40e.c b/drivers/net/i40e/rte_pmd_i40e.c
index 4c3c708..fdcb1a4 100644
--- a/drivers/net/i40e/rte_pmd_i40e.c
+++ b/drivers/net/i40e/rte_pmd_i40e.c
@@ -3207,3 +3207,24 @@ int rte_pmd_i40e_flow_add_del_packet_template(
I40E_WRITE_FLUSH(hw);
return 0;
}
+
+int
+rte_pmd_i40e_set_switch_dev(uint16_t port_id, struct rte_eth_dev *switch_dev)
+{
+ struct rte_eth_dev *i40e_dev;
+ struct i40e_hw *hw;
+
+ RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
+
+ i40e_dev = &rte_eth_devices[port_id];
+ if (!is_i40e_supported(i40e_dev))
+ return -ENOTSUP;
+
+ hw = I40E_DEV_PRIVATE_TO_HW(i40e_dev->data->dev_private);
+ if (!hw)
+ return -1;
+
+ hw->switch_dev = switch_dev;
+
+ return 0;
+}
diff --git a/drivers/net/i40e/rte_pmd_i40e.h b/drivers/net/i40e/rte_pmd_i40e.h
index faac9e2..355b8be 100644
--- a/drivers/net/i40e/rte_pmd_i40e.h
+++ b/drivers/net/i40e/rte_pmd_i40e.h
@@ -1061,4 +1061,22 @@ int rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype,
return 0;
}
+/**
+ * For ipn3ke, i40e works with FPGA.
+ * In this situation, i40e get link status from fpga,
+ * fpga works as switch_dev for i40e.
+ * This function set switch_dev for i40e.
+ *
+ * @param inset
+ *Input set value.
+ * @param field_idx
+ *Field index for input set.
+ * @return
+ * - (less than 0) if failed.
+ * - (0) if success.
+ */
+__rte_experimental
+int
+rte_pmd_i40e_set_switch_dev(uint16_t port_id, struct rte_eth_dev *switch_dev);
+
#endif /* _PMD_I40E_H_ */
diff --git a/drivers/net/i40e/rte_pmd_i40e_version.map
b/drivers/net/i40e/rte_pmd_i40e_version.map
index cccd576..79641f2 100644
--- a/drivers/net/i40e/rte_pmd_i40e_version.map
+++ b/drivers/net/i40e/rte_pmd_i40e_version.map
@@ -64,4 +64,10 @@ DPDK_18.02 {
rte_pmd_i40e_inset_get;
rte_pmd_i40e_inset_set;
-} DPDK_17.11;
\ No newline at end of file
+} DPDK_17.11;
+
+EXPERIMENTAL {
+ global:
+
+ rte_pmd_i40e_set_switch_dev;
+} DPDK_18.02;
\ No newline at end of file
--
1.8.3.1
[dpdk-dev] [PATCH v8 02/18] raw/ifpga/base: add irq support
From: Tianfei zhang
Add irq support for ifpga FME global error, port error and uint unit.
We implmented this feature by vfio interrupt mechanism.
To build this feature, CONFIG_RTE_EAL_VFIO should be enabled.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
config/common_base | 2 +-
config/common_linux| 6 +++
drivers/raw/ifpga/base/ifpga_feature_dev.c | 59 ++
drivers/raw/ifpga/base/ifpga_fme_error.c | 19 ++
drivers/raw/ifpga/base/ifpga_port.c| 18 +
drivers/raw/ifpga/base/ifpga_port_error.c | 19 ++
6 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/config/common_base b/config/common_base
index e843a21..68a4f70 100644
--- a/config/common_base
+++ b/config/common_base
@@ -772,7 +772,7 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=n
#
# Compile PMD for Intel FPGA raw device
#
-CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
+CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=n
#
# Compile PMD for Intel IOAT raw device
diff --git a/config/common_linux b/config/common_linux
index 96e2e1f..a78b8c6 100644
--- a/config/common_linux
+++ b/config/common_linux
@@ -68,3 +68,9 @@ CONFIG_RTE_LIBRTE_HINIC_PMD=y
# Hisilicon HNS3 PMD driver
#
CONFIG_RTE_LIBRTE_HNS3_PMD=y
+
+#
+# Compile PMD for Intel FPGA raw device
+# To compile, CONFIG_RTE_EAL_VFIO should be enabled.
+#
+CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
diff --git a/drivers/raw/ifpga/base/ifpga_feature_dev.c
b/drivers/raw/ifpga/base/ifpga_feature_dev.c
index 63c8bcc..0f852a7 100644
--- a/drivers/raw/ifpga/base/ifpga_feature_dev.c
+++ b/drivers/raw/ifpga/base/ifpga_feature_dev.c
@@ -3,6 +3,7 @@
*/
#include
+#include
#include "ifpga_feature_dev.h"
@@ -331,3 +332,61 @@ int port_hw_init(struct ifpga_port_hw *port)
port_hw_uinit(port);
return ret;
}
+
+#define FPGA_MAX_MSIX_VEC_COUNT128
+/* irq set buffer length for interrupt */
+#define MSIX_IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + \
+ sizeof(int) * FPGA_MAX_MSIX_VEC_COUNT)
+
+/* only support msix for now*/
+static int vfio_msix_enable_block(s32 vfio_dev_fd, unsigned int vec_start,
+ unsigned int count, s32 *fds)
+{
+ char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
+ struct vfio_irq_set *irq_set;
+ int len, ret;
+ int *fd_ptr;
+
+ len = sizeof(irq_set_buf);
+
+ irq_set = (struct vfio_irq_set *)irq_set_buf;
+ irq_set->argsz = len;
+ /* 0 < irq_set->count < FPGA_MAX_MSIX_VEC_COUNT */
+ irq_set->count = count ?
+ (count > FPGA_MAX_MSIX_VEC_COUNT ?
+FPGA_MAX_MSIX_VEC_COUNT : count) : 1;
+ irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
+ VFIO_IRQ_SET_ACTION_TRIGGER;
+ irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
+ irq_set->start = vec_start;
+
+ fd_ptr = (int *)&irq_set->data;
+ opae_memcpy(fd_ptr, fds, sizeof(int) * count);
+
+ ret = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+ if (ret)
+ printf("Error enabling MSI-X interrupts\n");
+
+ return ret;
+}
+
+int fpga_msix_set_block(struct ifpga_feature *feature, unsigned int start,
+ unsigned int count, s32 *fds)
+{
+ struct feature_irq_ctx *ctx = feature->ctx;
+ unsigned int i;
+ int ret;
+
+ if (start >= feature->ctx_num || start + count > feature->ctx_num)
+ return -EINVAL;
+
+ /* assume that each feature has continuous vector space in msix*/
+ ret = vfio_msix_enable_block(feature->vfio_dev_fd,
+ctx[start].idx, count, fds);
+ if (!ret) {
+ for (i = 0; i < count; i++)
+ ctx[i].eventfd = fds[i];
+ }
+
+ return ret;
+}
diff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c
b/drivers/raw/ifpga/base/ifpga_fme_error.c
index 3794564..2978c79 100644
--- a/drivers/raw/ifpga/base/ifpga_fme_error.c
+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c
@@ -373,9 +373,28 @@ static int fme_global_error_set_prop(struct ifpga_feature
*feature,
return -ENOENT;
}
+static int fme_global_err_set_irq(struct ifpga_feature *feature, void *irq_set)
+{
+ struct fpga_fme_err_irq_set *err_irq_set = irq_set;
+ struct ifpga_fme_hw *fme;
+ int ret;
+
+ fme = (struct ifpga_fme_hw *)feature->parent;
+
+ if (!(fme->capability & FPGA_FME_CAP_ERR_IRQ))
+ return -ENODEV;
+
+ spinlock_lock(&fme->lock);
+ ret = fpga_msix_set_block(feature, 0, 1, &err_irq_set->evtfd);
+ spinlock_unlock(&fme->lock);
+
+ return ret;
+}
+
struct ifpga_feature_ops fme_global_err_ops = {
.init = fme_global_error_init,
.uinit = fme_global_error_uinit,
.get_prop = fme_global_error_get_prop,
.set_prop = fme_global_error_set_prop,
+ .set_irq = fme_global_err_set_irq,
};
diff
[dpdk-dev] [PATCH v8 04/18] raw/ifpga/base: add SEU error support
From: Tianfei zhang
This patch exposes SEU error information to application then application
could compare this information (128bit) with its own SMH file to know
if this SEU is a fatal error or not.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_defines.h | 5 -
drivers/raw/ifpga/base/ifpga_fme_error.c | 31 ++
drivers/raw/ifpga/base/opae_ifpga_hw_api.h | 2 ++
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/raw/ifpga/base/ifpga_defines.h
b/drivers/raw/ifpga/base/ifpga_defines.h
index 4216128..b450cb1 100644
--- a/drivers/raw/ifpga/base/ifpga_defines.h
+++ b/drivers/raw/ifpga/base/ifpga_defines.h
@@ -1149,7 +1149,8 @@ struct feature_fme_error_capability {
u8 support_intr:1;
/* MSI-X vector table entry number */
u16 intr_vector_num:12;
- u64 rsvd:51;/* Reserved */
+ u64 rsvd:50;/* Reserved */
+ u64 seu_support:1;
};
};
};
@@ -1171,6 +1172,8 @@ struct feature_fme_err {
struct feature_fme_ras_catfaterror ras_catfaterr;
struct feature_fme_ras_error_inj ras_error_inj;
struct feature_fme_error_capability fme_err_capability;
+ u64 seu_emr_l;
+ u64 seu_emr_h;
};
/* FME Partial Reconfiguration Control */
diff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c
b/drivers/raw/ifpga/base/ifpga_fme_error.c
index be041ec..5d6d630 100644
--- a/drivers/raw/ifpga/base/ifpga_fme_error.c
+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c
@@ -257,6 +257,33 @@ static void fme_global_error_uinit(struct ifpga_feature
*feature)
UNUSED(feature);
}
+static int fme_err_check_seu(struct feature_fme_err *fme_err)
+{
+ struct feature_fme_error_capability error_cap;
+
+ error_cap.csr = readq(&fme_err->fme_err_capability);
+
+ return error_cap.seu_support ? 1 : 0;
+}
+
+static int fme_err_get_seu_emr(struct ifpga_fme_hw *fme,
+ u64 *val, bool high)
+{
+ struct feature_fme_err *fme_err
+ = get_fme_feature_ioaddr_by_index(fme,
+ FME_FEATURE_ID_GLOBAL_ERR);
+
+ if (!fme_err_check_seu(fme_err))
+ return -ENODEV;
+
+ if (high)
+ *val = readq(&fme_err->seu_emr_h);
+ else
+ *val = readq(&fme_err->seu_emr_l);
+
+ return 0;
+}
+
static int fme_err_fme_err_get_prop(struct ifpga_feature *feature,
struct feature_prop *prop)
{
@@ -270,6 +297,10 @@ static int fme_err_fme_err_get_prop(struct ifpga_feature
*feature,
return fme_err_get_first_error(fme, &prop->data);
case 0x3: /* NEXT_ERROR */
return fme_err_get_next_error(fme, &prop->data);
+ case 0x5: /* SEU EMR LOW */
+ return fme_err_get_seu_emr(fme, &prop->data, 0);
+ case 0x6: /* SEU EMR HIGH */
+ return fme_err_get_seu_emr(fme, &prop->data, 1);
}
return -ENOENT;
diff --git a/drivers/raw/ifpga/base/opae_ifpga_hw_api.h
b/drivers/raw/ifpga/base/opae_ifpga_hw_api.h
index 4c2c990..bab3386 100644
--- a/drivers/raw/ifpga/base/opae_ifpga_hw_api.h
+++ b/drivers/raw/ifpga/base/opae_ifpga_hw_api.h
@@ -74,6 +74,8 @@ struct feature_prop {
#define FME_ERR_PROP_FIRST_ERROR ERR_PROP_FME_ERR(0x2)
#define FME_ERR_PROP_NEXT_ERRORERR_PROP_FME_ERR(0x3)
#define FME_ERR_PROP_CLEAR ERR_PROP_FME_ERR(0x4) /* WO */
+#define FME_ERR_PROP_SEU_EMR_LOWERR_PROP_FME_ERR(0x5)
+#define FME_ERR_PROP_SEU_EMR_HIGH ERR_PROP_FME_ERR(0x6)
#define FME_ERR_PROP_REVISION ERR_PROP_ROOT(0x5)
#define FME_ERR_PROP_PCIE0_ERRORS ERR_PROP_ROOT(0x6) /* RW */
#define FME_ERR_PROP_PCIE1_ERRORS ERR_PROP_ROOT(0x7) /* RW */
--
1.8.3.1
[dpdk-dev] [PATCH v8 03/18] raw/ifpga/base: clear pending bit
From: Tianfei zhang
Every defined bit in FME_ERROR0 is RW1C. Other reserved bits are always
0 when readout and it will plan to be RW1C if needed in future.
So it is safe just write the read back value to clear all the errors.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_defines.h | 9 -
drivers/raw/ifpga/base/ifpga_fme_error.c | 4 ++--
drivers/raw/ifpga/base/opae_osdep.h | 7 +--
3 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/raw/ifpga/base/ifpga_defines.h
b/drivers/raw/ifpga/base/ifpga_defines.h
index b7151ca..4216128 100644
--- a/drivers/raw/ifpga/base/ifpga_defines.h
+++ b/drivers/raw/ifpga/base/ifpga_defines.h
@@ -957,25 +957,24 @@ struct feature_fme_dperf {
};
struct feature_fme_error0 {
-#define FME_ERROR0_MASK0xFFUL
#define FME_ERROR0_MASK_DEFAULT 0x40UL /* pcode workaround */
union {
u64 csr;
struct {
u8 fabric_err:1; /* Fabric error */
u8 fabfifo_overflow:1; /* Fabric fifo overflow */
- u8 kticdc_parity_err:2;/* KTI CDC Parity Error */
- u8 iommu_parity_err:1; /* IOMMU Parity error */
+ u8 reserved2:3;
/* AFU PF/VF access mismatch detected */
u8 afu_acc_mode_err:1;
- u8 mbp_err:1; /* Indicates an MBP event */
+ u8 reserved6:1;
/* PCIE0 CDC Parity Error */
u8 pcie0cdc_parity_err:5;
/* PCIE1 CDC Parity Error */
u8 pcie1cdc_parity_err:5;
/* CVL CDC Parity Error */
u8 cvlcdc_parity_err:3;
- u64 rsvd:44;/* Reserved */
+ u8 fpgaseuerr:1;
+ u64 rsvd:43;/* Reserved */
};
};
};
diff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c
b/drivers/raw/ifpga/base/ifpga_fme_error.c
index 2978c79..be041ec 100644
--- a/drivers/raw/ifpga/base/ifpga_fme_error.c
+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c
@@ -54,7 +54,7 @@ static int fme_err_set_clear(struct ifpga_fme_hw *fme, u64
val)
int ret = 0;
spinlock_lock(&fme->lock);
- writeq(FME_ERROR0_MASK, &fme_err->fme_err_mask);
+ writeq(GENMASK_ULL(63, 0), &fme_err->fme_err_mask);
fme_error0.csr = readq(&fme_err->fme_err);
if (val != fme_error0.csr) {
@@ -65,7 +65,7 @@ static int fme_err_set_clear(struct ifpga_fme_hw *fme, u64
val)
fme_first_err.csr = readq(&fme_err->fme_first_err);
fme_next_err.csr = readq(&fme_err->fme_next_err);
- writeq(fme_error0.csr & FME_ERROR0_MASK, &fme_err->fme_err);
+ writeq(fme_error0.csr, &fme_err->fme_err);
writeq(fme_first_err.csr & FME_FIRST_ERROR_MASK,
&fme_err->fme_first_err);
writeq(fme_next_err.csr & FME_NEXT_ERROR_MASK,
diff --git a/drivers/raw/ifpga/base/opae_osdep.h
b/drivers/raw/ifpga/base/opae_osdep.h
index 1596adc..416cef0 100644
--- a/drivers/raw/ifpga/base/opae_osdep.h
+++ b/drivers/raw/ifpga/base/opae_osdep.h
@@ -32,10 +32,12 @@ struct uuid {
#ifndef BITS_PER_LONG
#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
#endif
+#ifndef BITS_PER_LONG_LONG
+#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
+#endif
#ifndef BIT
#define BIT(a) (1UL << (a))
#endif /* BIT */
-#define U64_C(x) x ## ULL
#ifndef BIT_ULL
#define BIT_ULL(a) (1ULL << (a))
#endif /* BIT_ULL */
@@ -43,7 +45,8 @@ struct uuid {
#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h
#endif /* GENMASK */
#ifndef GENMASK_ULL
-#define GENMASK_ULL(h, l) (((U64_C(1) << ((h) - (l) + 1)) - 1) << (l))
+#define GENMASK_ULL(h, l) \
+ (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h
#endif /* GENMASK_ULL */
#endif /* LINUX_MACROS */
--
1.8.3.1
[dpdk-dev] [PATCH v8 05/18] raw/ifpga/base: add device tree support
From: Tianfei zhang
In PAC N3000 card, this is a BMC chip which using MAX10 FPGA
to manage the board configuration, like sensors, flash controller,
QSFP, powers. And this is a SPI bus connected between A10 FPGA and
MAX10, we can access the MAX10 registers over this SPI bus.
In BMC, there are about 19 sensors in MAX10 chip, including the FPGA
core temperature, Board temperature, board current, voltage and so on.
We use DTB (Device tree table) to describe it. This DTB file is store
in nor flash partition, which will flashed in Factory when the boards
delivery to customers. And the same time, the customers can easy to
customizate the BMC configuration like change the sensors.
Add device tree support by using libfdt library in Linux distribution.
The end-user should pre-install the libfdt and libfdt-devel package
before use DPDK on PAC N3000 Card.
For Centos 7.x: sudo yum install libfdt libfdt-devel
For Ubuntu 18.04: sudo apt install libfdt-dev libfdt1
To eliminate build error, we currently do not compile raw/ifpga
and net/ipn3ke. User should install libfdt and libfdt-devel first,
modify config/common_linux, CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=n
to CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y, modify config/common_base,
CONFIG_RTE_LIBRTE_IPN3KE_PMD=y to CONFIG_RTE_LIBRTE_IPN3KE_PMD=n.
Then this function can work.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
config/common_base| 2 +-
config/common_linux | 2 +-
drivers/raw/ifpga/base/opae_intel_max10.c | 183 ++
drivers/raw/ifpga/base/opae_intel_max10.h | 10 ++
mk/rte.app.mk | 2 +-
5 files changed, 196 insertions(+), 3 deletions(-)
diff --git a/config/common_base b/config/common_base
index 68a4f70..c0c9d5e 100644
--- a/config/common_base
+++ b/config/common_base
@@ -336,7 +336,7 @@ CONFIG_RTE_LIBRTE_IAVF_16BYTE_RX_DESC=n
#
# Compile burst-oriented IPN3KE PMD driver
#
-CONFIG_RTE_LIBRTE_IPN3KE_PMD=y
+CONFIG_RTE_LIBRTE_IPN3KE_PMD=n
#
# Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD
diff --git a/config/common_linux b/config/common_linux
index a78b8c6..c5cf3d6 100644
--- a/config/common_linux
+++ b/config/common_linux
@@ -73,4 +73,4 @@ CONFIG_RTE_LIBRTE_HNS3_PMD=y
# Compile PMD for Intel FPGA raw device
# To compile, CONFIG_RTE_EAL_VFIO should be enabled.
#
-CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
+CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=n
diff --git a/drivers/raw/ifpga/base/opae_intel_max10.c
b/drivers/raw/ifpga/base/opae_intel_max10.c
index 9ed10e2..305baba 100644
--- a/drivers/raw/ifpga/base/opae_intel_max10.c
+++ b/drivers/raw/ifpga/base/opae_intel_max10.c
@@ -3,6 +3,7 @@
*/
#include "opae_intel_max10.h"
+#include
static struct intel_max10_device *g_max10;
@@ -26,6 +27,174 @@ int max10_reg_write(unsigned int reg, unsigned int val)
reg, 4, (unsigned char *)&tmp);
}
+static struct max10_compatible_id max10_id_table[] = {
+ {.compatible = MAX10_PAC,},
+ {.compatible = MAX10_PAC_N3000,},
+ {.compatible = MAX10_PAC_END,}
+};
+
+static struct max10_compatible_id *max10_match_compatible(const char *fdt_root)
+{
+ struct max10_compatible_id *id = max10_id_table;
+
+ for (; strcmp(id->compatible, MAX10_PAC_END); id++) {
+ if (fdt_node_check_compatible(fdt_root, 0, id->compatible))
+ continue;
+
+ return id;
+ }
+
+ return NULL;
+}
+
+static inline bool
+is_max10_pac_n3000(struct intel_max10_device *max10)
+{
+ return max10->id && !strcmp(max10->id->compatible,
+ MAX10_PAC_N3000);
+}
+
+static void max10_check_capability(struct intel_max10_device *max10)
+{
+ if (!max10->fdt_root)
+ return;
+
+ if (is_max10_pac_n3000(max10)) {
+ max10->flags |= MAX10_FLAGS_NO_I2C2 |
+ MAX10_FLAGS_NO_BMCIMG_FLASH;
+ dev_info(max10, "found %s card\n", max10->id->compatible);
+ }
+}
+
+static int altera_nor_flash_read(u32 offset,
+ void *buffer, u32 len)
+{
+ int word_len;
+ int i;
+ unsigned int *buf = (unsigned int *)buffer;
+ unsigned int value;
+ int ret;
+
+ if (!buffer || len <= 0)
+ return -ENODEV;
+
+ word_len = len/4;
+
+ for (i = 0; i < word_len; i++) {
+ ret = max10_reg_read(offset + i*4,
+ &value);
+ if (ret)
+ return -EBUSY;
+
+ *buf++ = value;
+ }
+
+ return 0;
+}
+
+static int enable_nor_flash(bool on)
+{
+ unsigned int val = 0;
+ int ret;
+
+ ret = max10_reg_read(RSU_REG_OFF, &val);
+ if (ret) {
+ dev_err(NULL "enabling flash error\n");
+ return ret;
+ }
+
+ if (on)
+ val |= RSU_ENABLE;
+ else
+ val &= ~RSU_ENABLE;
+
+
[dpdk-dev] [PATCH v8 07/18] raw/ifpga/base: add sensor support
From: Tianfei zhang
The sensor devices are connected in MAX10 FPGA. we used the
device tree to describe those sensor devices. Parse the device
tree to get the sensor devices and add them into a list.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/opae_intel_max10.c | 279 ++
drivers/raw/ifpga/base/opae_intel_max10.h | 56 ++
2 files changed, 335 insertions(+)
diff --git a/drivers/raw/ifpga/base/opae_intel_max10.c
b/drivers/raw/ifpga/base/opae_intel_max10.c
index 305baba..ae7a8df 100644
--- a/drivers/raw/ifpga/base/opae_intel_max10.c
+++ b/drivers/raw/ifpga/base/opae_intel_max10.c
@@ -7,6 +7,9 @@
static struct intel_max10_device *g_max10;
+struct opae_sensor_list opae_sensor_list =
+ TAILQ_HEAD_INITIALIZER(opae_sensor_list);
+
int max10_reg_read(unsigned int reg, unsigned int *val)
{
if (!g_max10)
@@ -195,6 +198,277 @@ static int init_max10_device_table(struct
intel_max10_device *max10)
return ret;
}
+static u64 fdt_get_number(const fdt32_t *cell, int size)
+{
+ u64 r = 0;
+
+ while (size--)
+ r = (r << 32) | fdt32_to_cpu(*cell++);
+
+ return r;
+}
+
+static int fdt_get_reg(const void *fdt, int node, unsigned int idx,
+ u64 *start, u64 *size)
+{
+ const fdt32_t *prop, *end;
+ int na = 0, ns = 0, len = 0, parent;
+
+ parent = fdt_parent_offset(fdt, node);
+ if (parent < 0)
+ return parent;
+
+ prop = fdt_getprop(fdt, parent, "#address-cells", NULL);
+ na = prop ? fdt32_to_cpu(*prop) : 2;
+
+ prop = fdt_getprop(fdt, parent, "#size-cells", NULL);
+ ns = prop ? fdt32_to_cpu(*prop) : 2;
+
+ prop = fdt_getprop(fdt, node, "reg", &len);
+ if (!prop)
+ return -FDT_ERR_NOTFOUND;
+
+ end = prop + len/sizeof(*prop);
+ prop = prop + (na + ns) * idx;
+
+ if (prop + na + ns > end)
+ return -FDT_ERR_NOTFOUND;
+
+ *start = fdt_get_number(prop, na);
+ *size = fdt_get_number(prop + na, ns);
+
+ return 0;
+}
+
+static int __fdt_stringlist_search(const void *fdt, int offset,
+ const char *prop, const char *string)
+{
+ int length, len, index = 0;
+ const char *list, *end;
+
+ list = fdt_getprop(fdt, offset, prop, &length);
+ if (!list)
+ return length;
+
+ len = strlen(string) + 1;
+ end = list + length;
+
+ while (list < end) {
+ length = strnlen(list, end - list) + 1;
+
+ if (list + length > end)
+ return -FDT_ERR_BADVALUE;
+
+ if (length == len && memcmp(list, string, length) == 0)
+ return index;
+
+ list += length;
+ index++;
+ }
+
+ return -FDT_ERR_NOTFOUND;
+}
+
+static int fdt_get_named_reg(const void *fdt, int node, const char *name,
+ u64 *start, u64 *size)
+{
+ int idx;
+
+ idx = __fdt_stringlist_search(fdt, node, "reg-names", name);
+ if (idx < 0)
+ return idx;
+
+ return fdt_get_reg(fdt, node, idx, start, size);
+}
+
+static void max10_sensor_uinit(void)
+{
+ struct opae_sensor_info *info;
+
+ TAILQ_FOREACH(info, &opae_sensor_list, node) {
+ TAILQ_REMOVE(&opae_sensor_list, info, node);
+ opae_free(info);
+ }
+}
+
+static bool sensor_reg_valid(struct sensor_reg *reg)
+{
+ return !!reg->size;
+}
+
+static int max10_add_sensor(struct raw_sensor_info *info,
+ struct opae_sensor_info *sensor)
+{
+ int i;
+ int ret = 0;
+ unsigned int val;
+
+ if (!info || !sensor)
+ return -ENODEV;
+
+ sensor->id = info->id;
+ sensor->name = info->name;
+ sensor->type = info->type;
+ sensor->multiplier = info->multiplier;
+
+ for (i = SENSOR_REG_VALUE; i < SENSOR_REG_MAX; i++) {
+ if (!sensor_reg_valid(&info->regs[i]))
+ continue;
+
+ ret = max10_reg_read(info->regs[i].regoff, &val);
+ if (ret)
+ break;
+
+ if (val == 0xdeadbeef)
+ continue;
+
+ val *= info->multiplier;
+
+ switch (i) {
+ case SENSOR_REG_VALUE:
+ sensor->value_reg = info->regs[i].regoff;
+ sensor->flags |= OPAE_SENSOR_VALID;
+ break;
+ case SENSOR_REG_HIGH_WARN:
+ sensor->high_warn = val;
+ sensor->flags |= OPAE_SENSOR_HIGH_WARN_VALID;
+ break;
+ case SENSOR_REG_HIGH_FATAL:
+ sensor->high_fatal = val;
+ sensor->flags |= OPAE_SENSOR_HIGH_FATAL_VALID;
+ break;
+ case SENSOR_REG_LOW_WARN:
+ sens
[dpdk-dev] [PATCH v8 06/18] raw/ifpga/base: align the send buffer for SPI
From: Tianfei zhang
The length of send buffer of SPI bus should be 4bytes align.
Signed-off-by: Tianfei Zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/opae_spi_transaction.c | 40 ---
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/raw/ifpga/base/opae_spi_transaction.c
b/drivers/raw/ifpga/base/opae_spi_transaction.c
index 17ec3c1..06ca625 100644
--- a/drivers/raw/ifpga/base/opae_spi_transaction.c
+++ b/drivers/raw/ifpga/base/opae_spi_transaction.c
@@ -109,6 +109,34 @@ static int resp_find_sop_eop(unsigned char *resp, unsigned
int len,
return ret;
}
+static void phy_tx_pad(unsigned char *phy_buf, unsigned int phy_buf_len,
+ unsigned int *aligned_len)
+{
+ unsigned char *p = &phy_buf[phy_buf_len - 1], *dst_p;
+
+ *aligned_len = IFPGA_ALIGN(phy_buf_len, 4);
+
+ if (*aligned_len == phy_buf_len)
+ return;
+
+ dst_p = &phy_buf[*aligned_len - 1];
+
+ /* move EOP and bytes after EOP to the end of aligned size */
+ while (p > phy_buf) {
+ *dst_p = *p;
+
+ if (*p == SPI_PACKET_EOP)
+ break;
+
+ p--;
+ dst_p--;
+ }
+
+ /* fill the hole with PHY_IDLE */
+ while (p < dst_p)
+ *p++ = SPI_BYTE_IDLE;
+}
+
static int byte_to_core_convert(struct spi_transaction_dev *dev,
unsigned int send_len, unsigned char *send_data,
unsigned int resp_len, unsigned char *resp_data,
@@ -149,15 +177,19 @@ static int byte_to_core_convert(struct
spi_transaction_dev *dev,
}
}
- print_buffer("before spi:", send_packet, p-send_packet);
+ tx_len = p - send_packet;
+
+ print_buffer("before spi:", send_packet, tx_len);
- reorder_phy_data(32, send_packet, p - send_packet);
+ phy_tx_pad(send_packet, tx_len, &tx_len);
+ print_buffer("after pad:", send_packet, tx_len);
- print_buffer("after order to spi:", send_packet, p-send_packet);
+ reorder_phy_data(32, send_packet, tx_len);
+
+ print_buffer("after order to spi:", send_packet, tx_len);
/* call spi */
tx_buffer = send_packet;
- tx_len = p - send_packet;
rx_buffer = resp_packet;
rx_len = resp_max_len;
spi_flags = SPI_NOT_FOUND;
--
1.8.3.1
[dpdk-dev] [PATCH v8 10/18] raw/ifpga: add SEU error handler
From: Rosen Xu
Add SEU interrupt support for FPGA.
Signed-off-by: Tianfei zhang
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/ifpga_rawdev.c | 245 +++
1 file changed, 245 insertions(+)
diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c
index 1825143..f5e6119 100644
--- a/drivers/raw/ifpga/ifpga_rawdev.c
+++ b/drivers/raw/ifpga/ifpga_rawdev.c
@@ -27,6 +27,8 @@
#include
#include "base/opae_hw_api.h"
+#include "base/opae_ifpga_hw_api.h"
+#include "base/ifpga_api.h"
#include "rte_rawdev.h"
#include "rte_rawdev_pmd.h"
#include "rte_bus_ifpga.h"
@@ -605,6 +607,236 @@
};
static int
+ifpga_get_fme_error_prop(struct opae_manager *mgr,
+ u64 prop_id, u64 *val)
+{
+ struct feature_prop prop;
+
+ prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
+ prop.prop_id = prop_id;
+
+ if (opae_manager_ifpga_get_prop(mgr, &prop))
+ return -EINVAL;
+
+ *val = prop.data;
+
+ return 0;
+}
+
+static int
+ifpga_set_fme_error_prop(struct opae_manager *mgr,
+ u64 prop_id, u64 val)
+{
+ struct feature_prop prop;
+
+ prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
+ prop.prop_id = prop_id;
+
+ prop.data = val;
+
+ if (opae_manager_ifpga_set_prop(mgr, &prop))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int
+fme_err_read_seu_emr(struct opae_manager *mgr)
+{
+ u64 val;
+ int ret;
+
+ ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
+ if (ret)
+ return -EINVAL;
+
+ IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%lx\n", val);
+
+ ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
+ if (ret)
+ return -EINVAL;
+
+ IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%lx\n", val);
+
+ return 0;
+}
+
+static int fme_clear_warning_intr(struct opae_manager *mgr)
+{
+ u64 val;
+
+ if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
+ return -EINVAL;
+
+ if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
+ return -EINVAL;
+ if ((val & 0x40) != 0)
+ IFPGA_RAWDEV_PMD_INFO("clean not done\n");
+
+ return 0;
+}
+
+static int
+fme_err_handle_error0(struct opae_manager *mgr)
+{
+ struct feature_fme_error0 fme_error0;
+ u64 val;
+
+ if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
+ return -EINVAL;
+
+ fme_error0.csr = val;
+
+ if (fme_error0.fabric_err)
+ IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
+ else if (fme_error0.fabfifo_overflow)
+ IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
+ else if (fme_error0.afu_acc_mode_err)
+ IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
+ else if (fme_error0.pcie0cdc_parity_err)
+ IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
+ else if (fme_error0.cvlcdc_parity_err)
+ IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
+ else if (fme_error0.fpgaseuerr) {
+ fme_err_read_seu_emr(mgr);
+ rte_panic("SEU error occurred\n");
+ }
+
+ /* clean the errors */
+ if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int
+fme_err_handle_catfatal_error(struct opae_manager *mgr)
+{
+ struct feature_fme_ras_catfaterror fme_catfatal;
+ u64 val;
+
+ if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
+ return -EINVAL;
+
+ fme_catfatal.csr = val;
+
+ if (fme_catfatal.cci_fatal_err)
+ IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
+ else if (fme_catfatal.fabric_fatal_err)
+ IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
+ else if (fme_catfatal.pcie_poison_err)
+ IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
+ else if (fme_catfatal.inject_fata_err)
+ IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
+ else if (fme_catfatal.crc_catast_err)
+ IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
+ else if (fme_catfatal.injected_catast_err)
+ IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
+ else if (fme_catfatal.bmc_seu_catast_err) {
+ fme_err_read_seu_emr(mgr);
+ rte_panic("SEU error occurred in BMC\n");
+ }
+
+ return 0;
+}
+
+static int
+fme_err_handle_nonfaterror(struct opae_manager *mgr)
+{
+ struct feature_fme_ras_nonfaterror nonfaterr;
+ u64 val;
+
+ if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
+ return -EINVAL;
+
+ nonfaterr.csr = val;
+
+ if (nonfaterr.temp_thresh_ap1)
+ IFPGA_R
[dpdk-dev] [PATCH v8 09/18] raw/ifpga/base: update SEU register definition
From: Tianfei zhang
Update the SEU registser definition.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_defines.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/raw/ifpga/base/ifpga_defines.h
b/drivers/raw/ifpga/base/ifpga_defines.h
index b450cb1..8993cc6 100644
--- a/drivers/raw/ifpga/base/ifpga_defines.h
+++ b/drivers/raw/ifpga/base/ifpga_defines.h
@@ -1122,7 +1122,9 @@ struct feature_fme_ras_catfaterror {
u8 therm_catast_err:1;
/* Injected Catastrophic Error */
u8 injected_catast_err:1;
- u64 rsvd:52;
+ /* SEU error on BMC */
+ u8 bmc_seu_catast_err:1;
+ u64 rsvd:51;
};
};
};
--
1.8.3.1
[dpdk-dev] [PATCH v8 08/18] raw/ifpga/base: introducing sensor APIs
From: Tianfei zhang
Introducing sensor APIs to PMD driver for PAC N3000 card.
Those sensor APIs:
1. opae_mgr_for_each_sensor()
2. opae_mgr_get_sensor_by_name()
3. opae_mgr_get_sensor_by_id()
4. opae_mgr_get_sensor_value_by_name()
5. opae_mgr_get_sensor_value_by_id()
6. opae_mgr_get_sensor_value()
Signed-off-by: Tianfei Zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_api.c | 10 +++
drivers/raw/ifpga/base/ifpga_feature_dev.h | 3 +
drivers/raw/ifpga/base/ifpga_fme.c | 21 ++
drivers/raw/ifpga/base/opae_hw_api.c | 115 +
drivers/raw/ifpga/base/opae_hw_api.h | 16
5 files changed, 165 insertions(+)
diff --git a/drivers/raw/ifpga/base/ifpga_api.c
b/drivers/raw/ifpga/base/ifpga_api.c
index 7ae626d..33d1da3 100644
--- a/drivers/raw/ifpga/base/ifpga_api.c
+++ b/drivers/raw/ifpga/base/ifpga_api.c
@@ -209,9 +209,19 @@ static int ifpga_mgr_get_eth_group_region_info(struct
opae_manager *mgr,
return 0;
}
+static int ifpga_mgr_get_sensor_value(struct opae_manager *mgr,
+ struct opae_sensor_info *sensor,
+ unsigned int *value)
+{
+ struct ifpga_fme_hw *fme = mgr->data;
+
+ return fme_mgr_get_sensor_value(fme, sensor, value);
+}
+
struct opae_manager_ops ifpga_mgr_ops = {
.flash = ifpga_mgr_flash,
.get_eth_group_region_info = ifpga_mgr_get_eth_group_region_info,
+ .get_sensor_value = ifpga_mgr_get_sensor_value,
};
static int ifpga_mgr_read_mac_rom(struct opae_manager *mgr, int offset,
diff --git a/drivers/raw/ifpga/base/ifpga_feature_dev.h
b/drivers/raw/ifpga/base/ifpga_feature_dev.h
index e243d42..2b1309b 100644
--- a/drivers/raw/ifpga/base/ifpga_feature_dev.h
+++ b/drivers/raw/ifpga/base/ifpga_feature_dev.h
@@ -218,4 +218,7 @@ int fme_mgr_get_retimer_info(struct ifpga_fme_hw *fme,
struct opae_retimer_info *info);
int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,
struct opae_retimer_status *status);
+int fme_mgr_get_sensor_value(struct ifpga_fme_hw *fme,
+ struct opae_sensor_info *sensor,
+ unsigned int *value);
#endif /* _IFPGA_FEATURE_DEV_H_ */
diff --git a/drivers/raw/ifpga/base/ifpga_fme.c
b/drivers/raw/ifpga/base/ifpga_fme.c
index 2b447fd..794ca09 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -1300,3 +1300,24 @@ int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,
return 0;
}
+
+int fme_mgr_get_sensor_value(struct ifpga_fme_hw *fme,
+ struct opae_sensor_info *sensor,
+ unsigned int *value)
+{
+ struct intel_max10_device *dev;
+
+ dev = (struct intel_max10_device *)fme->max10_dev;
+ if (!dev)
+ return -ENODEV;
+
+ if (max10_reg_read(sensor->value_reg, value)) {
+ dev_err(dev, "%s: read sensor value register 0x%x fail\n",
+ __func__, sensor->value_reg);
+ return -EINVAL;
+ }
+
+ *value *= sensor->multiplier;
+
+ return 0;
+}
diff --git a/drivers/raw/ifpga/base/opae_hw_api.c
b/drivers/raw/ifpga/base/opae_hw_api.c
index 8964e79..d0e66d6 100644
--- a/drivers/raw/ifpga/base/opae_hw_api.c
+++ b/drivers/raw/ifpga/base/opae_hw_api.c
@@ -575,3 +575,118 @@ int opae_manager_get_retimer_status(struct opae_manager
*mgr,
return -ENOENT;
}
+
+/**
+ * opae_manager_get_sensor_by_id - get sensor device
+ * @id: the id of the sensor
+ *
+ * Return: the pointer of the opae_sensor_info
+ */
+struct opae_sensor_info *
+opae_mgr_get_sensor_by_id(unsigned int id)
+{
+ struct opae_sensor_info *sensor;
+
+ opae_mgr_for_each_sensor(sensor)
+ if (sensor->id == id)
+ return sensor;
+
+ return NULL;
+}
+
+/**
+ * opae_manager_get_sensor_by_name - get sensor device
+ * @name: the name of the sensor
+ *
+ * Return: the pointer of the opae_sensor_info
+ */
+struct opae_sensor_info *
+opae_mgr_get_sensor_by_name(const char *name)
+{
+ struct opae_sensor_info *sensor;
+
+ opae_mgr_for_each_sensor(sensor)
+ if (!strcmp(sensor->name, name))
+ return sensor;
+
+ return NULL;
+}
+
+/**
+ * opae_manager_get_sensor_value_by_name - find the sensor by name and read out
+ * the value
+ * @mgr: opae_manager for sensor.
+ * @name: the name of the sensor
+ * @value: the readout sensor value
+ *
+ * Return: 0 on success, otherwise error code
+ */
+int
+opae_mgr_get_sensor_value_by_name(struct opae_manager *mgr,
+ const char *name, unsigned int *value)
+{
+ struct opae_sensor_info *sensor;
+
+ if (!mgr)
+ return -EINVAL;
+
+ sensor = opae_mgr_get_sensor_by_name(name);
+ if (!sensor)
+ return -ENODEV;
+
+ if (mgr->ops && mgr->ops->get_sensor_value)
+ return mgr->ops->get_sensor_value(mgr, sensor, value);
+
+ return -E
[dpdk-dev] [PATCH v8 11/18] raw/ifpga: add PCIe BDF devices tree scan
From: Rosen Xu
Add PCIe BDF devices tree scan for ipn3ke.
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/ifpga_rawdev.c | 551 ++-
drivers/raw/ifpga/ifpga_rawdev.h | 16 ++
2 files changed, 562 insertions(+), 5 deletions(-)
diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c
index f5e6119..01ff76a 100644
--- a/drivers/raw/ifpga/ifpga_rawdev.c
+++ b/drivers/raw/ifpga/ifpga_rawdev.c
@@ -8,6 +8,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -17,7 +19,7 @@
#include
#include
#include
-
+#include
#include
#include
#include
@@ -25,6 +27,7 @@
#include
#include
#include
+#include
#include "base/opae_hw_api.h"
#include "base/opae_ifpga_hw_api.h"
@@ -37,6 +40,12 @@
#include "ifpga_rawdev.h"
#include "ipn3ke_rawdev_api.h"
+#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
+#define RTE_PCI_CFG_SPACE_SIZE 256
+#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
+#define RTE_PCI_EXT_CAP_ID(header) (int)(header & 0x)
+#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
+
int ifpga_rawdev_logtype;
#define PCI_VENDOR_ID_INTEL 0x8086
@@ -64,6 +73,494 @@
{ .vendor_id = 0, /* sentinel */ },
};
+static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
+
+static int ifpga_monitor_start;
+static pthread_t ifpga_monitor_start_thread;
+
+static struct ifpga_rawdev *
+ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
+static int set_surprise_link_check_aer(
+ struct ifpga_rawdev *ifpga_rdev, int force_disable);
+static int ifpga_pci_find_next_ext_capability(unsigned int fd,
+ int start, int cap);
+static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
+
+struct ifpga_rawdev *
+ifpga_rawdev_get(const struct rte_rawdev *rawdev)
+{
+ struct ifpga_rawdev *dev;
+ unsigned int i;
+
+ if (rawdev == NULL)
+ return NULL;
+
+ for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
+ dev = &ifpga_rawdevices[i];
+ if (dev->rawdev == rawdev)
+ return dev;
+ }
+
+ return NULL;
+}
+
+static inline uint8_t
+ifpga_rawdev_find_free_device_index(void)
+{
+ uint16_t dev_id;
+
+ for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
+ if (ifpga_rawdevices[dev_id].rawdev == NULL)
+ return dev_id;
+ }
+
+ return IFPGA_RAWDEV_NUM;
+}
+static struct ifpga_rawdev *
+ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
+{
+ struct ifpga_rawdev *dev;
+ uint16_t dev_id;
+
+ dev = ifpga_rawdev_get(rawdev);
+ if (dev != NULL) {
+ IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
+ return NULL;
+ }
+
+ dev_id = ifpga_rawdev_find_free_device_index();
+ if (dev_id == IFPGA_RAWDEV_NUM) {
+ IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
+ return NULL;
+ }
+
+ dev = &ifpga_rawdevices[dev_id];
+ dev->rawdev = rawdev;
+ dev->dev_id = dev_id;
+
+ return dev;
+}
+
+static int ifpga_pci_find_next_ext_capability(unsigned int fd,
+int start, int cap)
+{
+ uint32_t header;
+ int ttl;
+ int pos = RTE_PCI_CFG_SPACE_SIZE;
+ int ret;
+
+ /* minimum 8 bytes per capability */
+ ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
+
+ if (start)
+ pos = start;
+ ret = pread(fd, &header, sizeof(header), pos);
+ if (ret == -1)
+ return -1;
+
+ /*
+* If we have no capabilities, this is indicated by cap ID,
+* cap version and next pointer all being 0.
+*/
+ if (header == 0)
+ return 0;
+
+ while (ttl-- > 0) {
+ if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
+ return pos;
+
+ pos = RTE_PCI_EXT_CAP_NEXT(header);
+ if (pos < RTE_PCI_CFG_SPACE_SIZE)
+ break;
+ ret = pread(fd, &header, sizeof(header), pos);
+ if (ret == -1)
+ return -1;
+ }
+
+ return 0;
+}
+
+static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
+{
+ return ifpga_pci_find_next_ext_capability(fd, 0, cap);
+}
+
+static int ifpga_get_dev_vendor_id(const char *bdf,
+ uint32_t *dev_id, uint32_t *vendor_id)
+{
+ int fd;
+ char path[1024];
+ int ret;
+ uint32_t header;
+
+ strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
+ strlcat(path, bdf, sizeof(path));
+ strlcat(path, "/config", sizeof(path));
+ fd = open(path, O_RDWR);
+ if (fd < 0)
+ return -1;
+ ret = pread(fd, &header, sizeof(header), 0);
+ if (ret == -1) {
+ close(f
[dpdk-dev] [PATCH v8 12/18] net/ipn3ke: remove configuration for i40e port bonding
From: Rosen Xu
The ipn3ke board FPGA and i40e BDF scan has added in ifpga_rawdev,
so it doesn't need to provide configuration for i40e port bonding.
Signed-off-by: Rosen Xu
Signed-off-by: Andy Pei
---
drivers/net/ipn3ke/Makefile | 2 +
drivers/net/ipn3ke/ipn3ke_ethdev.c | 289
drivers/net/ipn3ke/ipn3ke_representor.c | 8 +-
3 files changed, 44 insertions(+), 255 deletions(-)
diff --git a/drivers/net/ipn3ke/Makefile b/drivers/net/ipn3ke/Makefile
index 8c3ae37..2c65e49 100644
--- a/drivers/net/ipn3ke/Makefile
+++ b/drivers/net/ipn3ke/Makefile
@@ -19,6 +19,8 @@ CFLAGS += -DALLOW_EXPERIMENTAL_API
CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
CFLAGS += -I$(RTE_SDK)/drivers/bus/ifpga
+CFLAGS += -I$(RTE_SDK)/drivers/raw/ifpga
+CFLAGS += -I$(RTE_SDK)/drivers/net/i40e
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
LDLIBS += -lrte_bus_ifpga
diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c
b/drivers/net/ipn3ke/ipn3ke_ethdev.c
index 28d8aaf..3051cdf 100644
--- a/drivers/net/ipn3ke/ipn3ke_ethdev.c
+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include "ipn3ke_rawdev_api.h"
#include "ipn3ke_flow.h"
@@ -324,7 +325,8 @@
"LineSideMACType", &mac_type);
hw->retimer.mac_type = (int)mac_type;
- IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", IPN3KE_READ_REG(hw, 0));
+ hw->acc_tm = 0;
+ hw->acc_flow = 0;
if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
@@ -342,6 +344,12 @@
/* After reset, wait until init done */
if (ipn3ke_vbng_init_done(hw))
return -1;
+
+ hw->acc_tm = 1;
+ hw->acc_flow = 1;
+
+ IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n",
+ IPN3KE_READ_REG(hw, 0));
}
if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
@@ -409,9 +417,6 @@
hw->flow_hw_enable = 1;
}
- hw->acc_tm = 0;
- hw->acc_flow = 0;
-
return 0;
}
@@ -462,7 +467,11 @@ static int ipn3ke_vswitch_probe(struct rte_afu_device
*afu_dev)
{
char name[RTE_ETH_NAME_MAX_LEN];
struct ipn3ke_hw *hw;
- int i, retval;
+ struct rte_eth_dev *i40e_eth;
+ struct ifpga_rawdev *ifpga_dev;
+ uint16_t port_id;
+ int i, j, retval;
+ char *fvl_bdf;
/* check if the AFU device has been probed already */
/* allocate shared mcp_vswitch structure */
@@ -489,7 +498,12 @@ static int ipn3ke_vswitch_probe(struct rte_afu_device
*afu_dev)
if (retval)
return retval;
+ ifpga_dev = ifpga_rawdev_get(hw->rawdev);
+ if (!ifpga_dev)
+ IPN3KE_AFU_PMD_ERR("failed to find ifpga_device.");
+
/* probe representor ports */
+ j = 0;
for (i = 0; i < hw->port_num; i++) {
struct ipn3ke_rpst rpst = {
.port_id = i,
@@ -501,6 +515,22 @@ static int ipn3ke_vswitch_probe(struct rte_afu_device
*afu_dev)
snprintf(name, sizeof(name), "net_%s_representor_%d",
afu_dev->device.name, i);
+ for (; j < 8; j++) {
+ fvl_bdf = ifpga_dev->fvl_bdf[j];
+ retval = rte_eth_dev_get_port_by_name(fvl_bdf,
+ &port_id);
+ if (retval) {
+ continue;
+ } else {
+ i40e_eth = &rte_eth_devices[port_id];
+ rpst.i40e_pf_eth = i40e_eth;
+ rpst.i40e_pf_eth_port_id = port_id;
+
+ j++;
+ break;
+ }
+ }
+
retval = rte_eth_dev_create(&afu_dev->device, name,
sizeof(struct ipn3ke_rpst), NULL, NULL,
ipn3ke_rpst_init, &rpst);
@@ -508,6 +538,7 @@ static int ipn3ke_vswitch_probe(struct rte_afu_device
*afu_dev)
if (retval)
IPN3KE_AFU_PMD_ERR("failed to create ipn3ke representor
%s.",
name);
+
}
return 0;
@@ -553,254 +584,6 @@ static int ipn3ke_vswitch_remove(struct rte_afu_device
*afu_dev)
RTE_PMD_REGISTER_AFU(net_ipn3ke_afu, afu_ipn3ke_driver);
-static const char * const valid_args[] = {
-#define IPN3KE_AFU_NAME "afu"
- IPN3KE_AFU_NAME,
-#define IPN3KE_FPGA_ACCELERATION_LIST "fpga_acc"
- IPN3KE_FPGA_ACCELERATION_LIST,
-#define IPN3KE_I40E_PF_LIST "i40e_pf"
- IPN3KE_I40E_PF_LIST,
- NULL
-};
-
-st
[dpdk-dev] [PATCH v8 14/18] raw/ifpga/base: configure FEC mode
From: Tianfei zhang
We can change the PKVL FEC mode when the A10 NIOS FW
initialization. The end-user can use this feature the
change the FEC mode, the default mode is RS FEC mode.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_fme.c | 42 +-
drivers/raw/ifpga/base/opae_spi.h | 23 +
2 files changed, 47 insertions(+), 18 deletions(-)
diff --git a/drivers/raw/ifpga/base/ifpga_fme.c
b/drivers/raw/ifpga/base/ifpga_fme.c
index 87fa596..2bc7c10 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -941,9 +941,34 @@ static int nios_spi_wait_init_done(struct
altera_spi_device *dev)
u32 val = 0;
unsigned long timeout = msecs_to_timer_cycles(1);
unsigned long ticks;
+ int major_version;
+ if (spi_reg_read(dev, NIOS_VERSION, &val))
+ return -EIO;
+
+ major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &
+ NIOS_VERSION_MAJOR;
+ dev_debug(dev, "A10 NIOS FW version %d\n", major_version);
+
+ if (major_version >= 3) {
+ /* read NIOS_INIT to check if PKVL INIT done or not */
+ if (spi_reg_read(dev, NIOS_INIT, &val))
+ return -EIO;
+
+ /* check if PKVLs are initialized already */
+ if (val & NIOS_INIT_DONE || val & NIOS_INIT_START)
+ goto nios_init_done;
+
+ /* start to config the default FEC mode */
+ val = NIOS_INIT_START;
+
+ if (spi_reg_write(dev, NIOS_INIT, val))
+ return -EIO;
+ }
+
+nios_init_done:
do {
- if (spi_reg_read(dev, NIOS_SPI_INIT_DONE, &val))
+ if (spi_reg_read(dev, NIOS_INIT, &val))
return -EIO;
if (val)
break;
@@ -961,23 +986,20 @@ static int nios_spi_check_error(struct altera_spi_device
*dev)
{
u32 value = 0;
- if (spi_reg_read(dev, NIOS_SPI_INIT_STS0, &value))
+ if (spi_reg_read(dev, PKVL_A_MODE_STS, &value))
return -EIO;
- dev_debug(dev, "SPI init status0 0x%x\n", value);
+ dev_debug(dev, "PKVL A Mode Status 0x%x\n", value);
- /* Error code: 0xFFF0 to 0xFFFC */
- if (value >= 0xFFF0 && value <= 0xFFFC)
+ if (value >= 0x100)
return -EINVAL;
- value = 0;
- if (spi_reg_read(dev, NIOS_SPI_INIT_STS1, &value))
+ if (spi_reg_read(dev, PKVL_B_MODE_STS, &value))
return -EIO;
- dev_debug(dev, "SPI init status1 0x%x\n", value);
+ dev_debug(dev, "PKVL B Mode Status 0x%x\n", value);
- /* Error code: 0xFFF0 to 0xFFFC */
- if (value >= 0xFFF0 && value <= 0xFFFC)
+ if (value >= 0x100)
return -EINVAL;
return 0;
diff --git a/drivers/raw/ifpga/base/opae_spi.h
b/drivers/raw/ifpga/base/opae_spi.h
index ab66e1f..6355deb 100644
--- a/drivers/raw/ifpga/base/opae_spi.h
+++ b/drivers/raw/ifpga/base/opae_spi.h
@@ -149,12 +149,19 @@ int spi_reg_write(struct altera_spi_device *dev, u32 reg,
#define NIOS_SPI_STAT 0x18
#define NIOS_SPI_VALID BIT_ULL(32)
#define NIOS_SPI_READ_DATA GENMASK_ULL(31, 0)
-#define NIOS_SPI_INIT_DONE 0x1000
-
-#define NIOS_SPI_INIT_DONE 0x1000
-#define NIOS_SPI_INIT_STS0 0x1020
-#define NIOS_SPI_INIT_STS1 0x1024
-#define PKVL_STATUS_RESET 0
-#define PKVL_10G_MODE 1
-#define PKVL_25G_MODE 2
+
+#define NIOS_INIT 0x1000
+#define REQ_FEC_MODE GENMASK(23, 8)
+#define FEC_MODE_NO0x0
+#define FEC_MODE_KR0x
+#define FEC_MODE_RS0x
+#define NIOS_INIT_STARTBIT(1)
+#define NIOS_INIT_DONE BIT(0)
+#define NIOS_VERSION 0x1004
+#define NIOS_VERSION_MAJOR_SHIFT 28
+#define NIOS_VERSION_MAJOR GENMASK(31, 28)
+#define NIOS_VERSION_MINOR GENMASK(27, 24)
+#define NIOS_VERSION_PATCH GENMASK(23, 20)
+#define PKVL_A_MODE_STS0x1020
+#define PKVL_B_MODE_STS0x1024
#endif
--
1.8.3.1
[dpdk-dev] [PATCH v8 15/18] raw/ifpga/base: clean fme errors
From: Tianfei zhang
Clean fme errors register when some fme errors occurred.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_fme_error.c | 24 ++--
drivers/raw/ifpga/ifpga_rawdev.c | 22 ++
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c
b/drivers/raw/ifpga/base/ifpga_fme_error.c
index 5d6d630..5905eac 100644
--- a/drivers/raw/ifpga/base/ifpga_fme_error.c
+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c
@@ -48,34 +48,14 @@ static int fme_err_set_clear(struct ifpga_fme_hw *fme, u64
val)
struct feature_fme_err *fme_err
= get_fme_feature_ioaddr_by_index(fme,
FME_FEATURE_ID_GLOBAL_ERR);
- struct feature_fme_error0 fme_error0;
- struct feature_fme_first_error fme_first_err;
- struct feature_fme_next_error fme_next_err;
- int ret = 0;
spinlock_lock(&fme->lock);
- writeq(GENMASK_ULL(63, 0), &fme_err->fme_err_mask);
-
- fme_error0.csr = readq(&fme_err->fme_err);
- if (val != fme_error0.csr) {
- ret = -EBUSY;
- goto exit;
- }
-
- fme_first_err.csr = readq(&fme_err->fme_first_err);
- fme_next_err.csr = readq(&fme_err->fme_next_err);
- writeq(fme_error0.csr, &fme_err->fme_err);
- writeq(fme_first_err.csr & FME_FIRST_ERROR_MASK,
- &fme_err->fme_first_err);
- writeq(fme_next_err.csr & FME_NEXT_ERROR_MASK,
- &fme_err->fme_next_err);
+ writeq(val, &fme_err->fme_err);
-exit:
- writeq(FME_ERROR0_MASK_DEFAULT, &fme_err->fme_err_mask);
spinlock_unlock(&fme->lock);
- return ret;
+ return 0;
}
static int fme_err_get_revision(struct ifpga_fme_hw *fme, u64 *val)
diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c
index 01ff76a..95f079a 100644
--- a/drivers/raw/ifpga/ifpga_rawdev.c
+++ b/drivers/raw/ifpga/ifpga_rawdev.c
@@ -1174,6 +1174,25 @@ static int fme_clear_warning_intr(struct opae_manager
*mgr)
return 0;
}
+static int fme_clean_fme_error(struct opae_manager *mgr)
+{
+ u64 val;
+
+ if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
+ return -EINVAL;
+
+ IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%lx\n", val);
+
+ ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
+
+ if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
+ return -EINVAL;
+
+ IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%lx\n", val);
+
+ return 0;
+}
+
static int
fme_err_handle_error0(struct opae_manager *mgr)
{
@@ -1183,6 +1202,9 @@ static int fme_clear_warning_intr(struct opae_manager
*mgr)
if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
return -EINVAL;
+ if (fme_clean_fme_error(mgr))
+ return -EINVAL;
+
fme_error0.csr = val;
if (fme_error0.fabric_err)
--
1.8.3.1
[dpdk-dev] [PATCH v8 17/18] raw/ifpga: add lightweight fpga image support
if fpga image support lightweight feature, set afu uuid to all 0, ipn3ke
representor will not be probed.
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/ifpga_rawdev.c | 44 +---
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c
index 95f079a..e87af66 100644
--- a/drivers/raw/ifpga/ifpga_rawdev.c
+++ b/drivers/raw/ifpga/ifpga_rawdev.c
@@ -835,6 +835,8 @@ static int set_surprise_link_check_aer(
rte_rawdev_obj_t pr_conf)
{
struct opae_adapter *adapter;
+ struct opae_manager *mgr;
+ struct opae_board_info *info;
struct rte_afu_pr_conf *afu_pr_conf;
int ret;
struct uuid uuid;
@@ -861,22 +863,40 @@ static int set_surprise_link_check_aer(
}
}
- acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
- if (!acc)
- return -ENODEV;
+ mgr = opae_adapter_get_mgr(adapter);
+ if (!mgr) {
+ IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
+ return -1;
+ }
- ret = opae_acc_get_uuid(acc, &uuid);
- if (ret)
- return ret;
+ if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
+ IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
+ return -1;
+ }
+
+ if (info->lightweight) {
+ /* set uuid to all 0, when fpga is lightweight image */
+ memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
+ memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
+ } else {
+ acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
+ if (!acc)
+ return -ENODEV;
- rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b, sizeof(u64));
- rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high,
- uuid.b + 8, sizeof(u64));
+ ret = opae_acc_get_uuid(acc, &uuid);
+ if (ret)
+ return ret;
- IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n", __func__,
- (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
- (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
+ rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
+ sizeof(u64));
+ rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
+ sizeof(u64));
+ IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
+ __func__,
+ (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
+ (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
+ }
return 0;
}
--
1.8.3.1
[dpdk-dev] [PATCH v8 16/18] raw/ifpga/base: add new API get board info
From: Tianfei zhang
Add new API to get the board info.
opae_mgr_get_board_info()
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_api.c | 11 +++
drivers/raw/ifpga/base/ifpga_defines.h | 55 ++
drivers/raw/ifpga/base/ifpga_fme.c | 53 +---
drivers/raw/ifpga/base/ifpga_hw.h | 2 +-
drivers/raw/ifpga/base/opae_hw_api.c | 20 +
drivers/raw/ifpga/base/opae_hw_api.h | 5
6 files changed, 121 insertions(+), 25 deletions(-)
diff --git a/drivers/raw/ifpga/base/ifpga_api.c
b/drivers/raw/ifpga/base/ifpga_api.c
index 33d1da3..6dbd715 100644
--- a/drivers/raw/ifpga/base/ifpga_api.c
+++ b/drivers/raw/ifpga/base/ifpga_api.c
@@ -218,10 +218,21 @@ static int ifpga_mgr_get_sensor_value(struct opae_manager
*mgr,
return fme_mgr_get_sensor_value(fme, sensor, value);
}
+static int ifpga_mgr_get_board_info(struct opae_manager *mgr,
+ struct opae_board_info **info)
+{
+ struct ifpga_fme_hw *fme = mgr->data;
+
+ *info = &fme->board_info;
+
+ return 0;
+}
+
struct opae_manager_ops ifpga_mgr_ops = {
.flash = ifpga_mgr_flash,
.get_eth_group_region_info = ifpga_mgr_get_eth_group_region_info,
.get_sensor_value = ifpga_mgr_get_sensor_value,
+ .get_board_info = ifpga_mgr_get_board_info,
};
static int ifpga_mgr_read_mac_rom(struct opae_manager *mgr, int offset,
diff --git a/drivers/raw/ifpga/base/ifpga_defines.h
b/drivers/raw/ifpga/base/ifpga_defines.h
index 1e84b15..9f0147d 100644
--- a/drivers/raw/ifpga/base/ifpga_defines.h
+++ b/drivers/raw/ifpga/base/ifpga_defines.h
@@ -1667,18 +1667,29 @@ struct bts_header {
(((bts_hdr)->guid_h == GBS_GUID_H) && \
((bts_hdr)->guid_l == GBS_GUID_L))
+#define check_support(n) (n == 1 ? "support" : "no")
+
/* bitstream id definition */
struct fme_bitstream_id {
union {
u64 id;
struct {
- u64 hash:32;
- u64 interface:4;
- u64 reserved:12;
- u64 debug:4;
- u64 patch:4;
- u64 minor:4;
- u64 major:4;
+ u8 build_patch:8;
+ u8 build_minor:8;
+ u8 build_major:8;
+ u8 fvl_bypass:1;
+ u8 mac_lightweight:1;
+ u8 disagregate:1;
+ u8 lightweiht:1;
+ u8 seu:1;
+ u8 ptp:1;
+ u8 reserve:2;
+ u8 interface:4;
+ u32 afu_revision:12;
+ u8 patch:4;
+ u8 minor:4;
+ u8 major:4;
+ u8 reserved:4;
};
};
};
@@ -1691,13 +1702,31 @@ enum board_interface {
VC_2_2_25G = 4,
};
-struct ifpga_fme_board_info {
+enum pac_major {
+ VISTA_CREEK = 0,
+ RUSH_CREEK = 1,
+ DARBY_CREEK = 2,
+};
+
+enum pac_minor {
+ DCP_1_0 = 0,
+ DCP_1_1 = 1,
+ DCP_1_2 = 2,
+};
+
+struct opae_board_info {
+ enum pac_major major;
+ enum pac_minor minor;
enum board_interface type;
- u32 build_hash;
- u32 debug_version;
- u32 patch_version;
- u32 minor_version;
- u32 major_version;
+
+ /* PAC features */
+ u8 fvl_bypass;
+ u8 mac_lightweight;
+ u8 disaggregate;
+ u8 lightweight;
+ u8 seu;
+ u8 ptp;
+
u32 max10_version;
u32 nios_fw_version;
u32 nums_of_retimer;
diff --git a/drivers/raw/ifpga/base/ifpga_fme.c
b/drivers/raw/ifpga/base/ifpga_fme.c
index 2bc7c10..799d67d 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -787,8 +787,22 @@ static const char *board_type_to_string(u32 type)
return "unknown";
}
+static const char *board_major_to_string(u32 major)
+{
+ switch (major) {
+ case VISTA_CREEK:
+ return "VISTA_CREEK";
+ case RUSH_CREEK:
+ return "RUSH_CREEK";
+ case DARBY_CREEK:
+ return "DARBY_CREEK";
+ }
+
+ return "unknown";
+}
+
static int board_type_to_info(u32 type,
- struct ifpga_fme_board_info *info)
+ struct opae_board_info *info)
{
switch (type) {
case VC_8_10G:
@@ -830,17 +844,34 @@ static int fme_get_board_interface(struct ifpga_fme_hw
*fme)
if (fme_hdr_get_bitstream_id(fme, &id.id))
return -EINVAL;
+ fme->board_info.major = id.major;
+ fme->board_info.minor = id.minor;
fme->board_info.type = id.interface;
- fme->board_info.build_hash = id.hash;
- fme->board_info.debug_version = id.debug;
- fme->board_info.major_version = id.major;
- fm
[dpdk-dev] [PATCH v8 18/18] raw/ifpga/base: add multiple cards support
From: Tianfei zhang
In PAC N3000 card, there is one MAX10 chip in each card, and
all of the sensors are connected to MAX10 chip. To support multiple
cards in one server, we introducing a sensor device list under
intel_max10_device instead of a global list. On the other hand, we
using seperate intel_max10_device instance for each opae_adatper.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_fme.c| 40 ---
drivers/raw/ifpga/base/opae_debug.c | 3 +
drivers/raw/ifpga/base/opae_hw_api.c | 14 ++--
drivers/raw/ifpga/base/opae_hw_api.h | 15 ++--
drivers/raw/ifpga/base/opae_intel_max10.c | 110 --
drivers/raw/ifpga/base/opae_intel_max10.h | 19 --
drivers/raw/ifpga/base/opae_spi.c | 1 +
drivers/raw/ifpga/base/opae_spi.h | 2 +-
drivers/raw/ifpga/ifpga_rawdev.c | 14 ++--
9 files changed, 134 insertions(+), 84 deletions(-)
diff --git a/drivers/raw/ifpga/base/ifpga_fme.c
b/drivers/raw/ifpga/base/ifpga_fme.c
index 799d67d..c31a94c 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -839,8 +839,13 @@ static int board_type_to_info(u32 type,
static int fme_get_board_interface(struct ifpga_fme_hw *fme)
{
struct fme_bitstream_id id;
+ struct ifpga_hw *hw;
u32 val;
+ hw = fme->parent;
+ if (!hw)
+ return -ENODEV;
+
if (fme_hdr_get_bitstream_id(fme, &id.id))
return -EINVAL;
@@ -854,7 +859,10 @@ static int fme_get_board_interface(struct ifpga_fme_hw
*fme)
fme->board_info.seu = id.seu;
fme->board_info.ptp = id.ptp;
- dev_info(fme, "found: board: %s type: %s\n",
+ dev_info(fme, "found: PCI dev: %02x:%02x:%x board: %s type: %s\n",
+ hw->pci_data->bus,
+ hw->pci_data->devid,
+ hw->pci_data->function,
board_major_to_string(fme->board_info.major),
board_type_to_string(fme->board_info.type));
@@ -882,11 +890,11 @@ static int fme_get_board_interface(struct ifpga_fme_hw
*fme)
fme->board_info.nums_of_fvl,
fme->board_info.ports_per_fvl);
- if (max10_sys_read(MAX10_BUILD_VER, &val))
+ if (max10_sys_read(fme->max10_dev, MAX10_BUILD_VER, &val))
return -EINVAL;
fme->board_info.max10_version = val & 0xff;
- if (max10_sys_read(NIOS2_FW_VERSION, &val))
+ if (max10_sys_read(fme->max10_dev, NIOS2_FW_VERSION, &val))
return -EINVAL;
fme->board_info.nios_fw_version = val & 0xff;
@@ -897,12 +905,12 @@ static int fme_get_board_interface(struct ifpga_fme_hw
*fme)
return 0;
}
-static int spi_self_checking(void)
+static int spi_self_checking(struct intel_max10_device *dev)
{
u32 val;
int ret;
- ret = max10_sys_read(MAX10_TEST_REG, &val);
+ ret = max10_sys_read(dev, MAX10_TEST_REG, &val);
if (ret)
return -EIO;
@@ -937,10 +945,11 @@ static int fme_spi_init(struct ifpga_feature *feature)
goto spi_fail;
}
+
fme->max10_dev = max10;
/* SPI self test */
- if (spi_self_checking()) {
+ if (spi_self_checking(max10)) {
ret = -EIO;
goto max10_fail;
}
@@ -1041,8 +1050,18 @@ static int fme_nios_spi_init(struct ifpga_feature
*feature)
struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
struct altera_spi_device *spi_master;
struct intel_max10_device *max10;
+ struct ifpga_hw *hw;
+ struct opae_manager *mgr;
int ret = 0;
+ hw = fme->parent;
+ if (!hw)
+ return -ENODEV;
+
+ mgr = hw->adapter->mgr;
+ if (!mgr)
+ return -ENODEV;
+
dev_info(fme, "FME SPI Master (NIOS) Init.\n");
dev_debug(fme, "FME SPI base addr %p.\n",
feature->addr);
@@ -1080,12 +1099,15 @@ static int fme_nios_spi_init(struct ifpga_feature
*feature)
goto release_dev;
}
+ max10->bus = hw->pci_data->bus;
+
fme_get_board_interface(fme);
fme->max10_dev = max10;
+ mgr->sensor_list = &max10->opae_sensor_list;
/* SPI self test */
- if (spi_self_checking())
+ if (spi_self_checking(max10))
goto spi_fail;
return ret;
@@ -1344,7 +1366,7 @@ int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,
if (!dev)
return -ENODEV;
- if (max10_sys_read(PKVL_LINK_STATUS, &val)) {
+ if (max10_sys_read(dev, PKVL_LINK_STATUS, &val)) {
dev_err(dev, "%s: read pkvl status fail\n", __func__);
return -EINVAL;
}
@@ -1372,7 +1394,7 @@ int fme_mgr_get_sensor_value(struct ifpga_fme_hw *fme,
if (!dev)
[dpdk-dev] [PATCH v8 13/18] raw/ifpga/base: add secure support
From: Tianfei zhang
Add secure max10 device support.
Signed-off-by: Tianfei zhang
Signed-off-by: Andy Pei
---
drivers/raw/ifpga/base/ifpga_defines.h| 2 +
drivers/raw/ifpga/base/ifpga_fme.c| 26 --
drivers/raw/ifpga/base/opae_intel_max10.c | 136 +-
drivers/raw/ifpga/base/opae_intel_max10.h | 80 +-
4 files changed, 197 insertions(+), 47 deletions(-)
diff --git a/drivers/raw/ifpga/base/ifpga_defines.h
b/drivers/raw/ifpga/base/ifpga_defines.h
index 8993cc6..1e84b15 100644
--- a/drivers/raw/ifpga/base/ifpga_defines.h
+++ b/drivers/raw/ifpga/base/ifpga_defines.h
@@ -1698,6 +1698,8 @@ struct ifpga_fme_board_info {
u32 patch_version;
u32 minor_version;
u32 major_version;
+ u32 max10_version;
+ u32 nios_fw_version;
u32 nums_of_retimer;
u32 ports_per_retimer;
u32 nums_of_fvl;
diff --git a/drivers/raw/ifpga/base/ifpga_fme.c
b/drivers/raw/ifpga/base/ifpga_fme.c
index 794ca09..87fa596 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -825,6 +825,7 @@ static int board_type_to_info(u32 type,
static int fme_get_board_interface(struct ifpga_fme_hw *fme)
{
struct fme_bitstream_id id;
+ u32 val;
if (fme_hdr_get_bitstream_id(fme, &id.id))
return -EINVAL;
@@ -850,6 +851,18 @@ static int fme_get_board_interface(struct ifpga_fme_hw
*fme)
fme->board_info.nums_of_fvl,
fme->board_info.ports_per_fvl);
+ if (max10_sys_read(MAX10_BUILD_VER, &val))
+ return -EINVAL;
+ fme->board_info.max10_version = val & 0xff;
+
+ if (max10_sys_read(NIOS2_FW_VERSION, &val))
+ return -EINVAL;
+ fme->board_info.nios_fw_version = val & 0xff;
+
+ dev_info(fme, "max10 version 0x%x, nios fw version 0x%x\n",
+ fme->board_info.max10_version,
+ fme->board_info.nios_fw_version);
+
return 0;
}
@@ -858,16 +871,11 @@ static int spi_self_checking(void)
u32 val;
int ret;
- ret = max10_reg_read(0x30043c, &val);
+ ret = max10_sys_read(MAX10_TEST_REG, &val);
if (ret)
return -EIO;
- if (val != 0x87654321) {
- dev_err(NULL, "Read MAX10 test register fail: 0x%x\n", val);
- return -EIO;
- }
-
- dev_info(NULL, "Read MAX10 test register success, SPI self-test
done\n");
+ dev_info(NULL, "Read MAX10 test register 0x%x\n", val);
return 0;
}
@@ -1283,7 +1291,7 @@ int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,
if (!dev)
return -ENODEV;
- if (max10_reg_read(PKVL_LINK_STATUS, &val)) {
+ if (max10_sys_read(PKVL_LINK_STATUS, &val)) {
dev_err(dev, "%s: read pkvl status fail\n", __func__);
return -EINVAL;
}
@@ -1311,7 +1319,7 @@ int fme_mgr_get_sensor_value(struct ifpga_fme_hw *fme,
if (!dev)
return -ENODEV;
- if (max10_reg_read(sensor->value_reg, value)) {
+ if (max10_sys_read(sensor->value_reg, value)) {
dev_err(dev, "%s: read sensor value register 0x%x fail\n",
__func__, sensor->value_reg);
return -EINVAL;
diff --git a/drivers/raw/ifpga/base/opae_intel_max10.c
b/drivers/raw/ifpga/base/opae_intel_max10.c
index ae7a8df..e597e47 100644
--- a/drivers/raw/ifpga/base/opae_intel_max10.c
+++ b/drivers/raw/ifpga/base/opae_intel_max10.c
@@ -30,6 +30,22 @@ int max10_reg_write(unsigned int reg, unsigned int val)
reg, 4, (unsigned char *)&tmp);
}
+int max10_sys_read(unsigned int offset, unsigned int *val)
+{
+ if (!g_max10)
+ return -ENODEV;
+
+ return max10_reg_read(g_max10->base + offset, val);
+}
+
+int max10_sys_write(unsigned int offset, unsigned int val)
+{
+ if (!g_max10)
+ return -ENODEV;
+
+ return max10_reg_write(g_max10->base + offset, val);
+}
+
static struct max10_compatible_id max10_id_table[] = {
{.compatible = MAX10_PAC,},
{.compatible = MAX10_PAC_N3000,},
@@ -66,7 +82,8 @@ static void max10_check_capability(struct intel_max10_device
*max10)
max10->flags |= MAX10_FLAGS_NO_I2C2 |
MAX10_FLAGS_NO_BMCIMG_FLASH;
dev_info(max10, "found %s card\n", max10->id->compatible);
- }
+ } else
+ max10->flags |= MAX10_FLAGS_MAC_CACHE;
}
static int altera_nor_flash_read(u32 offset,
@@ -100,7 +117,7 @@ static int enable_nor_flash(bool on)
unsigned int val = 0;
int ret;
- ret = max10_reg_read(RSU_REG_OFF, &val);
+ ret = max10_sys_read(RSU_REG, &val);
if (ret) {
dev_err(NULL "enabling flash error\n");
return ret;
@@ -111,7 +128,7 @@ static int enable_nor_flash(bool on)
Re: [dpdk-dev] [PATCH 2/3] drivers: use RTE_DIM instead of ARRAY_SIZE
> -Original Message-
> From: pbhagavat...@marvell.com
> Sent: Friday, October 11, 2019 1:07 PM
[...]
> Subject: [dpdk-dev] [PATCH 2/3] drivers: use RTE_DIM instead of
> ARRAY_SIZE
>
> From: Pavan Nikhilesh
>
> Use RTE_DIM instead of re-defining ARRAY_SIZE.
>
> Signed-off-by: Pavan Nikhilesh
> ---
[...]
> drivers/net/enic/base/vnic_dev.c | 4 +--
> drivers/net/enic/base/vnic_devcmd.h | 2 --
[...]
> diff --git a/drivers/net/enic/base/vnic_dev.c
> b/drivers/net/enic/base/vnic_dev.c
> index 8e190687d..3b9a336ff 100644
> --- a/drivers/net/enic/base/vnic_dev.c
> +++ b/drivers/net/enic/base/vnic_dev.c
> @@ -417,11 +417,11 @@ int vnic_dev_cmd(struct vnic_dev *vdev, enum
> vnic_devcmd_cmd cmd,
> switch (vdev->proxy) {
> case PROXY_BY_INDEX:
> err = vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_INDEX,
> cmd,
> - args, ARRAY_SIZE(args), wait);
> + args, RTE_DIM(args), wait);
> break;
> case PROXY_BY_BDF:
> err = vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_BDF,
> cmd,
> - args, ARRAY_SIZE(args), wait);
> + args, RTE_DIM(args), wait);
> break;
> case PROXY_NONE:
> default:
> diff --git a/drivers/net/enic/base/vnic_devcmd.h
> b/drivers/net/enic/base/vnic_devcmd.h
> index fffe307e0..5a4f48106 100644
> --- a/drivers/net/enic/base/vnic_devcmd.h
> +++ b/drivers/net/enic/base/vnic_devcmd.h
> @@ -63,8 +63,6 @@
> #define _CMD_VTYPE(cmd) (((cmd) >> _CMD_VTYPESHIFT) &
> _CMD_VTYPEMASK)
> #define _CMD_N(cmd) (((cmd) >> _CMD_NSHIFT) & _CMD_NMASK)
>
> -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
> -
> enum vnic_devcmd_cmd {
> CMD_NONE= _CMDC(_CMD_DIR_NONE,
> _CMD_VTYPE_NONE, 0),
>
[...]
For enic.
Acked-by: Hyong Youb Kim
Thanks.
-Hyong
Re: [dpdk-dev] [PATCH 2/3] drivers: use RTE_DIM instead of ARRAY_SIZE
> > [snip] > >> drivers/net/sfc/base/ef10_ev.c | 4 +-- >> drivers/net/sfc/base/ef10_filter.c | 12 >> drivers/net/sfc/base/ef10_mac.c | 18 +-- >> drivers/net/sfc/base/ef10_nic.c | 4 +-- >> drivers/net/sfc/base/ef10_nvram.c | 6 ++-- >> drivers/net/sfc/base/efx.h | 3 -- >> drivers/net/sfc/base/efx_port.c | 2 +- >> drivers/net/sfc/base/efx_rx.c | 2 +- >> drivers/net/sfc/base/siena_mac.c | 2 +- >> drivers/net/sfc/base/siena_nic.c | 20 ++--- >> drivers/net/sfc/base/siena_nvram.c | 6 ++-- > > NACK > No changes in net/sfc/base please. It is the base driver > which is used on other platforms. So, it can't use DPDK > specific macros. > Hi Pravan, > > drivers/net/atlantic/atl_hw_regs.h| 1 - > drivers/net/atlantic/hw_atl/hw_atl_utils.c| 4 +-- > .../net/atlantic/hw_atl/hw_atl_utils_fw2x.c | 2 +- We also tend to share these modules with linux and other codebases. Less diffs we have to review is better. Why not keep ARRAY_SIZE as a widely used compat alternative? Regards, Igor
Re: [dpdk-dev] Minutes of Technical Board Meeting, 2019-09-25
On Fri, Sep 27, 2019 at 4:03 PM Bruce Richardson wrote: > 2. SPDX licenses (standing agenda item): > > Hemant provided an update on the gaps to be closed for achieving > use of SPDX tags alone (i.e. no license text in files) in 19.11. > Key gaps: > > * Issue identified with pmdinfogen using GPL derived code, meaning > it needs a license exception. Tech board has approved the > exception and the request will now be passed to the governing > board for final approval. Thereafter an update will be made to > the file "license/exceptions.txt" in the DPDK repo The patch is here https://patchwork.dpdk.org/patch/59976/ Did we get a formal approval from the governing board? Thanks. -- David Marchand
Re: [dpdk-dev] [PATCH v4 16/19] net/hinic: add hinic PMD doc files
On 10/10/2019 3:52 PM, Xiaoyun wang wrote: > Add new supported features to rst file and add features to ini file. > > Signed-off-by: Xiaoyun wang > --- > doc/guides/nics/features/hinic.ini | 2 ++ > doc/guides/rel_notes/release_19_11.rst | 9 + > 2 files changed, 11 insertions(+) > > diff --git a/doc/guides/nics/features/hinic.ini > b/doc/guides/nics/features/hinic.ini > index 65a335a..dc02b4b 100644 > --- a/doc/guides/nics/features/hinic.ini > +++ b/doc/guides/nics/features/hinic.ini > @@ -34,7 +34,9 @@ Basic stats = Y > Extended stats = Y > Stats per queue = Y > Flow director= Y > +Flow control = Y > FW version = Y > +Multiprocess aware = Y > Linux UIO= Y > Linux VFIO = Y > BSD nic_uio = N > diff --git a/doc/guides/rel_notes/release_19_11.rst > b/doc/guides/rel_notes/release_19_11.rst > index 8390e5e..08b72a6 100644 > --- a/doc/guides/rel_notes/release_19_11.rst > +++ b/doc/guides/rel_notes/release_19_11.rst > @@ -297,3 +297,12 @@ Tested Platforms >* Added support for VLAN set PCP offload command. >* Added support for VLAN set VID offload command. > > +* **Updated the Huawei hinic driver.** > + > + Updated the Huawei hinic driver with new features and improvements, > including: > + > + * Enabled SR-IOV - Partially supported at this point, VFIO only. > + * Supported VLAN filter and VLAN offload. > + * Supported Unicast MAC filter and Multicast MAC filter. > + * Supported FW version get. > + * Supported Flow director for LACP, VRRP, BGP and so on. > Release files changes split into relevant patch while merging. Btw, new features should be in the "New Features" section.
Re: [dpdk-dev] [PATCH v4 00/19] Add advanced features for Huawei hinic pmd
On 10/10/2019 3:51 PM, Xiaoyun wang wrote: > This patch set adds advanced features for Huawei hinic pmd, > such as VLAN filter and VLAN offload, SR-IOV, FW version get, > set link down and up, Flow director for LACP, VRRP, BGP and so on. > > -- > v2: > - Fix RSS bugs for vxlan packets inner type > - Add comments for new added func interface > - Fix code review comments from patch v1 > - Fix code style problems > - Remove ceq interfaces and definitions that not used > - Fix aeq init bugs, firstly alloc aeq resource, then set aeq ctrl len > - Fix bar map bugs for VF Page size larger than PF > - Modify link state set, add enable or disable fiber in tx direction > - Fix mbox and mgmt channel sync lock mechanism to reduce CPU usage > - Fix FDIR bugs for VRRP packets > - Fit ABI changes from dpdk lib > > v3: > - Split hinic.ini and hinic.rst to related feature patches > - Add min_mtu & max_mtu initialization for hinic_dev_infos_get > - Fix fdir config patch with net/hinic/base > - Split link patch into link and fw version getting 2 patches > - Update pmd doc files to new next version > - Add comments for cover letter patch > - Add rxq & txq info getting interfaces > - Fix load intrinsics for receiving packets > > v4: > - Fix receive performance code review comments > - Fix 32-bit build errs for mbox logs > - Modify skb description as mbuf Series applied to dpdk-next-net/master, thanks.
Re: [dpdk-dev] [PATCH 2/3] drivers: use RTE_DIM instead of ARRAY_SIZE
> Hi Pavan, > > > > > From: Pavan Nikhilesh > > > > Use RTE_DIM instead of re-defining ARRAY_SIZE. > > > > Signed-off-by: Pavan Nikhilesh > > --- > > drivers/bus/dpaa/base/qbman/qman.c| 6 ++-- > > drivers/bus/dpaa/include/compat.h | 5 > > drivers/crypto/dpaa2_sec/hw/compat.h | 8 - > > drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h| 6 ++-- > > drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h | 2 +- > > drivers/net/atlantic/atl_hw_regs.h| 1 - > > drivers/net/atlantic/hw_atl/hw_atl_utils.c| 4 +-- > > .../net/atlantic/hw_atl/hw_atl_utils_fw2x.c | 2 +- > > drivers/net/axgbe/axgbe_common.h | 3 -- > > drivers/net/axgbe/axgbe_dev.c | 2 +- > > drivers/net/bnx2x/bnx2x.c | 6 ++-- > > drivers/net/bnx2x/bnx2x.h | 6 > > drivers/net/bnx2x/ecore_init.h| 8 ++--- > > drivers/net/bnx2x/ecore_sp.c | 2 +- > > drivers/net/bnx2x/elink.c | 14 - > > drivers/net/bnx2x/elink.h | 1 - > > drivers/net/cxgbe/base/t4_hw.c| 16 +- > > drivers/net/cxgbe/base/t4vf_hw.c | 4 +-- > > drivers/net/cxgbe/cxgbe_compat.h | 2 -- > > drivers/net/cxgbe/cxgbe_flow.c| 4 +-- > > drivers/net/cxgbe/cxgbe_main.c| 10 +++ > > drivers/net/cxgbe/sge.c | 2 +- > > drivers/net/ena/ena_ethdev.c | 8 ++--- > > drivers/net/enic/base/vnic_dev.c | 4 +-- > > drivers/net/enic/base/vnic_devcmd.h | 2 -- > > drivers/net/hns3/hns3_cmd.c | 2 +- > > drivers/net/hns3/hns3_ethdev.h| 2 -- > > drivers/net/hns3/hns3_flow.c | 18 +-- > > drivers/net/i40e/base/i40e_diag.c | 2 +- > > drivers/net/i40e/base/i40e_osdep.h| 2 -- > > drivers/net/iavf/base/iavf_osdep.h| 2 -- > > drivers/net/ice/base/ice_fdir.c | 2 +- > > drivers/net/ice/base/ice_flex_pipe.c | 2 +- > > drivers/net/ice/base/ice_flow.c | 2 +- > > drivers/net/ice/base/ice_osdep.h | 1 - > > drivers/net/ice/base/ice_switch.c | 2 +- > > .../net/nfp/nfpcore/nfp-common/nfp_platform.h | 4 --- > > drivers/net/nfp/nfpcore/nfp_cppcore.c | 2 +- > > drivers/net/nfp/nfpcore/nfp_nsp.c | 2 +- > > drivers/net/nfp/nfpcore/nfp_nsp_eth.c | 4 +-- > > drivers/net/sfc/base/ef10_ev.c| 4 +-- > > drivers/net/sfc/base/ef10_filter.c| 12 > > drivers/net/sfc/base/ef10_mac.c | 18 +-- > > drivers/net/sfc/base/ef10_nic.c | 4 +-- > > drivers/net/sfc/base/ef10_nvram.c | 6 ++-- > > drivers/net/sfc/base/efx.h| 3 -- > > drivers/net/sfc/base/efx_port.c | 2 +- > > drivers/net/sfc/base/efx_rx.c | 2 +- > > drivers/net/sfc/base/siena_mac.c | 2 +- > > drivers/net/sfc/base/siena_nic.c | 20 ++--- > > drivers/net/sfc/base/siena_nvram.c| 6 ++-- > > drivers/net/thunderx/base/nicvf_hw.c | 30 +-- > > drivers/net/thunderx/base/nicvf_hw.h | 2 -- > > .../raw/ifpga/base/osdep_rte/osdep_generic.h | 2 -- > > 54 files changed, 120 insertions(+), 170 deletions(-) > > > > diff --git a/drivers/bus/dpaa/base/qbman/qman.c > > b/drivers/bus/dpaa/base/qbman/qman.c > > index e43fc65ef..019be95e2 100644 > > --- a/drivers/bus/dpaa/base/qbman/qman.c > > +++ b/drivers/bus/dpaa/base/qbman/qman.c > > @@ -1956,7 +1956,7 @@ int qman_query_wq(u8 query_dedicated, struct > > qm_mcr_querywq *wq) > > int i, array_len; > > > > wq->channel.id = be16_to_cpu(mcr->querywq.channel.id); > > - array_len = ARRAY_SIZE(mcr->querywq.wq_len); > > + array_len = RTE_DIM(mcr->querywq.wq_len); > > [Hemant] some of these files are common Flibs and they are shared with > other projects (Linux/uboot) etc. It will be more appropriate to > map the ARRAY_SIZE to RTE_DIM in compat.h instead of changing this code > inline. > This way we need not to maintain diff from the common HW lib codes. +1 to this suggestion
Re: [dpdk-dev] 18.11.3 (LTS) patches review and test
On 07/10/2019 21:01, Thinh Tran wrote: > Hi- > > IBM - DPDK on Power result > > *Basic PF on Mallanox: No new errors or regressions were seen. > *Performance: no degradation compared to 18.11.2 > > System tested: > - IBM Power9 Model 8335-101 CPU: 2.3 (pvr 004e 1203) > Tested NICs: > - Mellanox Technologies MT28800 Family [ConnectX-5 Ex] > - firmware version: 16.26.292 > - MLNX_OFED_LINUX-4.7-1.0.0.1 > > > Regards, > Thinh Tran > Thanks for the report Thinh. I will add these to the validation notes. Kevin. > On 9/13/2019 11:31 AM, Kevin Traynor wrote: >> Hi all, >> >> Here is a list of patches targeted for LTS release 18.11.3. >> >> The planned date for the final release is 9th October. >> >> Please help with testing and validation of your use cases and report >> any issues/results in reply to this mail. For the final release the >> fixes and reported validations will be added to the release notes. >> >> A release candidate tarball can be found at: >> >> https://dpdk.org/browse/dpdk-stable/tag/?id=v18.11.3-rc1 >> >> These patches are located at branch 18.11 of dpdk-stable repo: >> https://dpdk.org/browse/dpdk-stable/ >> >> Thanks. >> >> Kevin Traynor >> >> ---
Re: [dpdk-dev] [PATCH v4 1/1] fbarray: get fbarrays from containerized secondary
Some comments.
The title does not reflect the observed issue.
I understand that secondary processeses can't be started from a docker
container.
The patch title should reflect this.
On Wed, Jul 24, 2019 at 10:20 AM wrote:
>
> From: Yasufumi Ogawa
>
> In secondary_msl_create_walk(), it creates a file for fbarrays with its
> PID for reserving unique name among secondary processes. However, it
> does not work if secondary is run as app container because each of
> containerized secondary has PID 1. To reserve unique name, use hostname
> instead of PID because hostname is assigned as a short form of 64
> digits full container ID in docker.
>
> Cc: sta...@dpdk.org
I don't think we want to backport this behavior change.
>
> Signed-off-by: Yasufumi Ogawa
> ---
> lib/librte_eal/linux/eal/eal_memalloc.c | 28 +++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/lib/librte_eal/linux/eal/eal_memalloc.c
> b/lib/librte_eal/linux/eal/eal_memalloc.c
> index 1f6a7c18f..356b304a8 100644
> --- a/lib/librte_eal/linux/eal/eal_memalloc.c
> +++ b/lib/librte_eal/linux/eal/eal_memalloc.c
> @@ -1366,6 +1366,7 @@ secondary_msl_create_walk(const struct rte_memseg_list
> *msl,
> struct rte_memseg_list *primary_msl, *local_msl;
> char name[PATH_MAX];
> int msl_idx, ret;
> + char proc_id[33] = { 0 }; /* 32bytes is enough if using hostname */
This variable only makes sense in the if (getpid() == 1) branch,
please move it there, and see below comment about using gethostname().
>
> if (msl->external)
> return 0;
> @@ -1375,8 +1376,31 @@ secondary_msl_create_walk(const struct rte_memseg_list
> *msl,
> local_msl = &local_memsegs[msl_idx];
>
> /* create distinct fbarrays for each secondary */
> - snprintf(name, RTE_FBARRAY_NAME_LEN, "%s_%i",
> - primary_msl->memseg_arr.name, getpid());
> + /* If run secondary in a container, the name of fbarray file should
> +* not be decided with pid because getpid() always returns 1.
> +* In docker, hostname is assigned as a short form of full container
> +* ID. So use hostname as unique ID among containers instead.
I understand this is how it works for docker.
Is this the same in other container environments?
> +*/
> + if (getpid() == 1) {
> + FILE *hn_fp;
> + hn_fp = fopen("/etc/hostname", "r");
Why not use gethostname() ?
Plus, this api defines the maximum size of the hostname as HOST_NAME_MAX bytes.
> + if (hn_fp == NULL) {
> + RTE_LOG(ERR, EAL,
> + "Cannot open '/etc/hostname' for
> secondary\n");
> + return -1;
> + }
> +
> + /* with docker, /etc/hostname just has one entry of hostname
> */
> + if (fscanf(hn_fp, "%32s", proc_id) == EOF) {
> + fclose(hn_fp);
> + return -1;
> + }
> + fclose(hn_fp);
> + } else
> + sprintf(proc_id, "%d", (int)getpid());
> +
> + snprintf(name, RTE_FBARRAY_NAME_LEN, "%s_%s",
> + primary_msl->memseg_arr.name, proc_id);
>
> ret = rte_fbarray_init(&local_msl->memseg_arr, name,
> primary_msl->memseg_arr.len,
> --
> 2.17.1
>
--
David Marchand
Re: [dpdk-dev] [PATCH v4 01/19] net/hinic/base: add mbox command channel for SRIOV
Hi Xiaoyun,
Please pay attention to the coding style issue, and some other inline comments.
For the bit operation functions, we are consolidating the bit operations
functions into a common eal API family, when it is ready,
the cpu_to_be32 and vice versa APIs scattered here and there can be replaced
with the common one. This can
largely reduce code duplications. The work was started and is ongoing, I don't
intend to block the proceeding of your patches,
Just keep an eye on it and please do the replacement after the common bit APIs
are accepted.
/Gavin
> -Original Message-
> From: dev On Behalf Of Xiaoyun wang
> Sent: Thursday, October 10, 2019 10:52 PM
> To: ferruh.yi...@intel.com
> Cc: dev@dpdk.org; xuanziya...@huawei.com; shahar.bel...@huawei.com;
> luoxian...@huawei.com; tanya.brokh...@huawei.com;
> zhouguoy...@huawei.com; Xiaoyun wang
>
> Subject: [dpdk-dev] [PATCH v4 01/19] net/hinic/base: add mbox command
> channel for SRIOV
>
> Add mbox command channel for SR-IOV, which is used to
> communicate between VF and VF, VF and PF. This patch
> introduces data structures, initialization, interfaces
> and commands of mbox channel.
>
> Signed-off-by: Xiaoyun wang
> ---
> doc/guides/nics/features/hinic.ini | 1 +
> doc/guides/nics/hinic.rst| 1 +
> drivers/net/hinic/Makefile | 1 +
> drivers/net/hinic/base/hinic_compat.h| 36 +-
> drivers/net/hinic/base/hinic_pmd_hwdev.h | 5 +-
> drivers/net/hinic/base/hinic_pmd_mbox.c | 937
> +++
> drivers/net/hinic/base/hinic_pmd_mbox.h | 93 +++
> drivers/net/hinic/base/meson.build | 1 +
> 8 files changed, 1070 insertions(+), 5 deletions(-)
> create mode 100644 drivers/net/hinic/base/hinic_pmd_mbox.c
> create mode 100644 drivers/net/hinic/base/hinic_pmd_mbox.h
>
> diff --git a/doc/guides/nics/features/hinic.ini
> b/doc/guides/nics/features/hinic.ini
> index fe063d6..c858411 100644
> --- a/doc/guides/nics/features/hinic.ini
> +++ b/doc/guides/nics/features/hinic.ini
> @@ -19,6 +19,7 @@ RSS hash = Y
> RSS key update = Y
> RSS reta update = Y
> Inner RSS= Y
> +SR-IOV = Y
> CRC offload = Y
> L3 checksum offload = Y
> L4 checksum offload = Y
> diff --git a/doc/guides/nics/hinic.rst b/doc/guides/nics/hinic.rst
> index c9329bc..c3ce101 100644
> --- a/doc/guides/nics/hinic.rst
> +++ b/doc/guides/nics/hinic.rst
> @@ -24,6 +24,7 @@ Features
> - Link state information
> - Link flow control
> - Scattered and gather for TX and RX
> +- SR-IOV - Partially supported at this point, VFIO only
>
> Prerequisites
> -
> diff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile
> index 42b4a78..20a338e 100644
> --- a/drivers/net/hinic/Makefile
> +++ b/drivers/net/hinic/Makefile
> @@ -59,6 +59,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) +=
> hinic_pmd_mgmt.c
> SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_niccfg.c
> SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_nicio.c
> SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_wq.c
> +SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_mbox.c
>
> SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_ethdev.c
> SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_rx.c
> diff --git a/drivers/net/hinic/base/hinic_compat.h
> b/drivers/net/hinic/base/hinic_compat.h
> index f599947..fe26aad 100644
> --- a/drivers/net/hinic/base/hinic_compat.h
> +++ b/drivers/net/hinic/base/hinic_compat.h
> @@ -121,9 +121,7 @@ static inline int hinic_test_bit(int nr, volatile unsigned
> long *addr)
> {
> int res;
>
> - rte_mb();
Why is the barrier removed?
If the barrier is moved outside, it should also be reflected in the commit log,
as this is a critical change.
/Gavin
> res = ((*addr) & (1UL << nr)) != 0;
> - rte_mb();
Ditto.
> return res;
> }
>
Re: [dpdk-dev] [PATCH] net/ice: correct lut type for RSS
> -Original Message-
> From: Su, Simei
> Sent: Friday, October 11, 2019 1:12 PM
> To: Zhang, Qi Z ; Yang, Qiming
> ; Lu, Wenzhuo
> Cc: dev@dpdk.org; Su, Simei ; sta...@dpdk.org
> Subject: [PATCH] net/ice: correct lut type for RSS
>
> This patch changes RSS lut_type to corresponding macro.
>
> Fixes: ff963bfa7cb1 ("net/ice: support RSS")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Simei Su
Acked-by: Qi Zhang
Re: [dpdk-dev] 18.11.3 (LTS) patches review and test
On 08/10/2019 11:22, Yu, PingX wrote:
> Kevin,
> FYI. All build are passed in 18.11.3-RC2 except Win10 no support. No issues
> are found now.
>
Great, thanks for confirming Ping.
Kevin.
> Regards,
> Yu Ping
>
> -Original Message-
> From: Kevin Traynor [mailto:ktray...@redhat.com]
> Sent: Thursday, October 3, 2019 9:30 PM
> To: Yu, PingX ; sta...@dpdk.org; dev@dpdk.org
> Cc: Akhil Goyal ; Ali Alnubani ;
> Walker, Benjamin ; David Christensen
> ; Hemant Agrawal ; Stokes,
> Ian ; Jerin Jacob ; Mcnamara, John
> ; Ju-Hyoung Lee ; Luca
> Boccassi ; Pei Zhang ; Xu, Qian Q
> ; Raslan Darawsheh ; Thomas
> Monjalon ; Peng, Yuan ; Chen,
> Zhaoyan
> Subject: Re: 18.11.3 (LTS) patches review and test
>
> On 26/09/2019 08:41, Yu, PingX wrote:
>> Kevin,
>> FYi.
>>> 2. [dpdk-stable 18.11.3] meson build error on ub1604-i86
>> Q1: What are the error logs?
>> Please see below Error info.
>>
>> Q2: Is it a regression for you? i.e. did this test pass with 18.11.2?
>> No, it isn't a regression. We don't test it on 18.11.1 and 18.11.2 before,
>> another the test result is still failed after testing.
>> dpdk-stable V18.11.2 commitID(06c4b12a5968caea61e96f7d6bd29d2726fbe255)，test
>> failed.
>> dpdk-stable V18.11.1 commitID(16ece46735c9b70b7033ca7ae095930e9038d9fd)，test
>> failed, the same mistake.
>>
>> Error info：
>> ninja: Entering directory `build-gcc-static'
>> [296/1419] Compiling C object
>> 'drivers/a715181@@tmp_rte_common_dpaax@sta/common_dpaax_dpaax_iova_table.c.o'.
>> FAILED:
>> drivers/a715181@@tmp_rte_common_dpaax@sta/common_dpaax_dpaax_iova_tabl
>> e.c.o gcc -Idrivers/a715181@@tmp_rte_common_dpaax@sta -Idrivers
>> -I../drivers -Idrivers/common/dpaax -I../drivers/common/dpaax -I.
>> -I../ -Iconfig -I../config -Ilib/librte_eal/common
>> -I../lib/librte_eal/common -Ilib/librte_eal/common/include
>> -I../lib/librte_eal/common/include
>> -Ilib/librte_eal/common/include/arch/x86
>> -I../lib/librte_eal/common/include/arch/x86
>> -I../lib/librte_eal/linuxapp/eal/include
>> -Ilib/librte_eal/linuxapp/eal/../../../librte_compat
>> -I../lib/librte_eal/linuxapp/eal/../../../librte_compat
>> -Ilib/librte_eal -I../lib/librte_eal
>> -Ilib/librte_kvargs/../librte_eal/common/include
>> -I../lib/librte_kvargs/../librte_eal/common/include
>> -Ilib/librte_kvargs -I../lib/librte_kvargs -Ilib/librte_compat
>> -I../lib/librte_compat -fdiagnostics-color=always -pipe
>> -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -O3 -include
>> rte_config.h -Wsign-compare -Wcast-qual -Wno-pointer-to-int-cast -fPIC
>> -march=native -D_GNU_SOURCE -DALLOW_EXPERIMENTAL_API -MD -MQ
>> 'drivers/a715181@@tmp_rte_common_dpaax@sta/common_dpaax_dpaax_iova_tab
>> le.c.o' -MF
>> 'drivers/a715181@@tmp_rte_common_dpaax@sta/common_dpaax_dpaax_iova_tab
>> le.c.o.d' -o
>> 'drivers/a715181@@tmp_rte_common_dpaax@sta/common_dpaax_dpaax_iova_tab
>> le.c.o' -c ../drivers/common/dpaax/dpaax_iova_table.c
>> In file included from ../drivers/common/dpaax/dpaax_iova_table.c:8:0:
>> ../drivers/common/dpaax/dpaax_iova_table.c: In function ‘read_memory_node’:
>> ../drivers/common/dpaax/dpaax_logs.h:18:39: error: format ‘%lu’ expects
>> argument of type ‘long unsigned int’, but argument 5 has type ‘__off64_t
>> {aka long long int}’ [-Werror=format=]
>> rte_log(RTE_LOG_DEBUG, dpaax_logger, "dpaax: %s(): " fmt "\n", \
>>^
>> ../drivers/common/dpaax/dpaax_iova_table.c:102:2: note: in expansion of
>> macro ‘DPAAX_DEBUG’
>> DPAAX_DEBUG("Size of device-tree mem node: %lu", statbuf.st_size);
>> ^
>> ../drivers/common/dpaax/dpaax_logs.h:18:39: error: format ‘%lu’ expects
>> argument of type ‘long unsigned int’, but argument 5 has type ‘__off64_t
>> {aka long long int}’ [-Werror=format=]
>> rte_log(RTE_LOG_DEBUG, dpaax_logger, "dpaax: %s(): " fmt "\n", \
>>^
>> ../drivers/common/dpaax/dpaax_iova_table.c:121:3: note: in expansion of
>> macro ‘DPAAX_DEBUG’
>>DPAAX_DEBUG("Invalid memory node values or count. (size=%lu)",
>>^
>> cc1: all warnings being treated as errors [301/1419] Compiling C object
>> 'lib/76b5a35@@rte_pipeline@sta/librte_pipeline_rte_table_action.c.o'.
>> ninja: build stopped: subcommand failed.
>>
> Thanks Yu Ping, I reproduced and applied the commits to fix this. It should
> be fixed now in RC2 (see other mail). If you could re-run this test to
> confirm same for you, that would be great.
>
> Kevin.
>
Re: [dpdk-dev] 18.11.3 (LTS) patches review and test
On 10/10/2019 19:39, Stokes, Ian wrote: > > > On 9/13/2019 5:31 PM, Kevin Traynor wrote: >> Hi all, >> >> Here is a list of patches targeted for LTS release 18.11.3. >> >> The planned date for the final release is 9th October. >> >> Please help with testing and validation of your use cases and report >> any issues/results in reply to this mail. For the final release the >> fixes and reported validations will be added to the release notes. >> >> A release candidate tarball can be found at: >> >> https://dpdk.org/browse/dpdk-stable/tag/?id=v18.11.3-rc1 >> >> These patches are located at branch 18.11 of dpdk-stable repo: >> https://dpdk.org/browse/dpdk-stable/ >> >> Thanks. >> >> Kevin Traynor > > Hi Kevin, > > I've validated with current head OVS Master, 2.12.2 and OVS 2.11.3 with > VSPERF. > Tested with i40e (X710), i40eVF, ixgbe (82599ES), ixgbeVF, igb(I350) and > igbVF devices. > > Following tests were conducted and passed: > > * vswitch_p2p_tput: vSwitch - configure switch and execute RFC2544 > throughput test. > * vswitch_p2p_cont: vSwitch - configure switch and execute RFC2544 > continuous stream test. > * vswitch_pvp_tput: vSwitch - configure switch, vnf and execute RFC2544 > throughput test. > * vswitch_pvp_cont: vSwitch - configure switch, vnf and execute RFC2544 > continuous stream test. > * ovsdpdk_hotplug_attach: Ensure successful port-add after binding a > device to igb_uio after ovs-vswitchd is launched. > * ovsdpdk_mq_p2p_rxqs: Setup rxqs on NIC port. > * ovsdpdk_mq_pvp_rxqs: Setup rxqs on vhost user port. > * ovsdpdk_mq_pvp_rxqs_linux_bridge: Confirm traffic received over vhost > RXQs with Linux virtio device in guest. > * ovsdpdk_mq_pvp_rxqs_testpmd: Confirm traffic received over vhost RXQs > with DPDK device in guest. > * ovsdpdk_vhostuser_client: Test vhost-user client mode. > * ovsdpdk_vhostuser_client_reconnect: Test vhost-user client mode > reconnect feature. > * ovsdpdk_vhostuser_server: Test vhost-user server mode. > * ovsdpdk_vhostuser_sock_dir: Verify functionality of vhost-sock-dir flag. > * ovsdpdk_vdev_add_af_packet_pmd: Test addition of port using the > af_packet DPDK PMD driver. > * ovsdpdk_vdev_del_af_packet_pmd: Test deletion of port using the > af_packet DPDK PMD driver. > * ovsdpdk_numa: Test vhost-user NUMA support. Vhostuser PMD threads > should migrate to the same numa slot, where QEMU is executed. > * ovsdpdk_jumbo_p2p: Ensure that jumbo frames are received, processed > and forwarded correctly by DPDK physical ports. > * ovsdpdk_jumbo_pvp: Ensure that jumbo frames are received, processed > and forwarded correctly by DPDK vhost-user ports. > * ovsdpdk_jumbo_p2p_upper_bound: Ensure that jumbo frames above the > configured Rx port's MTU are not accepted. > * ovsdpdk_jumbo_mtu_upper_bound_vport: Verify that the upper bound limit > is enforced for OvS DPDK vhost-user ports. > * ovsdpdk_rate_p2p: Ensure when a user creates a rate limiting physical > interface that the traffic is limited to the specified policer rate in a > p2p setup. > * ovsdpdk_rate_pvp: Ensure when a user creates a rate limiting vHost > User interface that the traffic is limited to the specified policer rate > in a pvp setup. > * ovsdpdk_qos_p2p: In a p2p setup, ensure when a QoS egress policer is > created that the traffic is limited to the specified rate. > * ovsdpdk_qos_pvp: In a pvp setup, ensure when a QoS egress policer is > created that the traffic is limited to the specified rate. > * phy2phy_scalability: LTD.Scalability.Flows.RFC2544.0PacketLoss > * phy2phy_scalability_cont: Phy2Phy Scalability Continuous Stream > * pvp_cont: PVP Continuous Stream > * pvvp_cont: PVVP Continuous Stream > * pvpv_cont: Two VMs in parallel with Continuous Stream > Thanks Ian. I might summarize it a bit to shorten and add to the release notes. Kevin. > Regards > Ian > >
Re: [dpdk-dev] [PATCH v11 3/9] vhost: add the inflight structure
On 10/9/19 10:48 PM, Jin Yu wrote: > This patch adds the inflight queue region structure include > the split and packed. > > Signed-off-by: Lin Li > Signed-off-by: Xun Ni > Signed-off-by: Yu Zhang > Signed-off-by: Jin Yu > --- > lib/librte_vhost/rte_vhost.h | 43 > 1 file changed, 43 insertions(+) > Reviewed-by: Maxime Coquelin
[dpdk-dev] [PATCH v2 0/5] Add session-less, RSA, RSA-CRT to QAT
This patchset adds session-less option, RSA algorithm, RSA-CRT algorithm to Intel QuickAssist Technology PMD. This patchset depends on the [v5] cryptodev: extend api of asymmetric crypto by session-less [1] [1] http://patchwork.dpdk.org/patch/60882/ v2: - fixed alg size problem in crt - fixed rsa capabilities - added rsa test cases Arek Kusztal (5): crypto/qat: add sessionless implementation to asym pmd crypto/qat: add rsa implementation to asym pmd crypto/qat: add rsa crt implementation to asym pmd test/crypto: add sessionless to asymmetric mod exp test/crypto: add rsa tests to qat app/test/test_cryptodev_asym.c | 182 -- app/test/test_cryptodev_rsa_test_vectors.h | 213 +++ doc/guides/cryptodevs/features/qat.ini | 4 + doc/guides/rel_notes/release_19_11.rst | 8 + .../qat/qat_adf/qat_pke_functionality_arrays.h | 27 + drivers/crypto/qat/qat_asym.c | 616 - drivers/crypto/qat/qat_asym.h | 29 +- drivers/crypto/qat/qat_asym_capabilities.h | 21 + drivers/crypto/qat/qat_asym_pmd.c | 5 +- 9 files changed, 925 insertions(+), 180 deletions(-) -- 2.1.0
[dpdk-dev] [PATCH v2 2/5] crypto/qat: add rsa implementation to asym pmd
This commit adds rsa algorithm to asymmetric pmd
using pair (n, d) private key
Signed-off-by: Arek Kusztal
---
doc/guides/cryptodevs/features/qat.ini | 2 +
doc/guides/rel_notes/release_19_11.rst | 2 +
.../qat/qat_adf/qat_pke_functionality_arrays.h | 18 ++
drivers/crypto/qat/qat_asym.c | 253 -
drivers/crypto/qat/qat_asym.h | 2 +
drivers/crypto/qat/qat_asym_capabilities.h | 21 ++
drivers/crypto/qat/qat_asym_pmd.c | 3 +-
7 files changed, 297 insertions(+), 4 deletions(-)
diff --git a/doc/guides/cryptodevs/features/qat.ini
b/doc/guides/cryptodevs/features/qat.ini
index cef8015..374b523 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -14,6 +14,7 @@ OOP LB In SGL Out = Y
OOP LB In LB Out = Y
Digest encrypted = Y
Asymmetric sessionless = Y
+RSA PRIV OP KEY EXP= Y
;
; Supported crypto algorithms of the 'qat' crypto driver.
@@ -71,3 +72,4 @@ AES CCM (256) = Y
[Asymmetric]
Modular Exponentiation = Y
Modular Inversion = Y
+RSA= Y
diff --git a/doc/guides/rel_notes/release_19_11.rst
b/doc/guides/rel_notes/release_19_11.rst
index 7730483..e081fb1 100644
--- a/doc/guides/rel_notes/release_19_11.rst
+++ b/doc/guides/rel_notes/release_19_11.rst
@@ -89,6 +89,8 @@ New Features
Added support for asymmetric session-less operations.
+ Added support for RSA algorithm with pair (n, d) private key representation.
+
* **Added cryptodev API to use asymmetric session-less operation.**
Added session-less option to cryptodev asymmetric API. It works the same way
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
index 8adf209..4f857b9 100644
--- a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -49,4 +49,22 @@ static const uint32_t MOD_INV_IDS_EVEN[][2] = {
{ 4096, MATHS_MODINV_EVEN_L4096 },
};
+static const uint32_t RSA_MODEXP_ENC_IDS[][2] = {
+ { 512, PKE_RSA_EP_512 },
+ { 1024, PKE_RSA_EP_1024 },
+ { 1536, PKE_RSA_EP_1536 },
+ { 2048, PKE_RSA_EP_2048 },
+ { 3072, PKE_RSA_EP_3072 },
+ { 4096, PKE_RSA_EP_4096 },
+};
+
+static const uint32_t RSA_MODEXP_DEC_IDS[][2] = {
+ { 512, PKE_RSA_DP1_512 },
+ { 1024, PKE_RSA_DP1_1024 },
+ { 1536, PKE_RSA_DP1_1536 },
+ { 2048, PKE_RSA_DP1_2048 },
+ { 3072, PKE_RSA_DP1_3072 },
+ { 4096, PKE_RSA_DP1_4096 },
+};
+
#endif
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index bf5d22d..8985270 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -228,6 +228,170 @@ qat_asym_fill_arrays(struct rte_crypto_asym_op *asym_op,
cookie->input_array[1],
alg_size_in_bytes);
#endif
+ } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) {
+ err = qat_asym_check_nonzero(xform->rsa.n);
+ if (err) {
+ QAT_LOG(ERR, "Empty modulus in RSA"
+ " inverse, aborting this operation");
+ return err;
+ }
+
+ alg_size_in_bytes = xform->rsa.n.length;
+ alg_size = alg_size_in_bytes << 3;
+
+ qat_req->input_param_count =
+ QAT_ASYM_RSA_NUM_IN_PARAMS;
+ qat_req->output_param_count =
+ QAT_ASYM_RSA_NUM_OUT_PARAMS;
+
+ if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT ||
+ asym_op->rsa.op_type ==
+ RTE_CRYPTO_ASYM_OP_VERIFY) {
+
+ if (qat_asym_get_sz_and_func_id(RSA_MODEXP_ENC_IDS,
+ sizeof(RSA_MODEXP_ENC_IDS)/
+ sizeof(*RSA_MODEXP_ENC_IDS),
+ &alg_size, &func_id)) {
+ err = QAT_ASYM_ERROR_INVALID_PARAM;
+ QAT_LOG(ERR,
+ "Not supported RSA parameter size
(key)");
+ return err;
+ }
+ alg_size_in_bytes = alg_size >> 3;
+ if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT)
{
+ switch (asym_op->rsa.pad) {
+ case RTE_CRYPTO_RSA_PADDING_NONE:
+ rte_memcpy(cookie->input_array[0] +
+ al
[dpdk-dev] [PATCH v2 1/5] crypto/qat: add sessionless implementation to asym pmd
This patch adds option to use asymmetric crypto pmd with
session-less support.
Signed-off-by: Arek Kusztal
---
doc/guides/cryptodevs/features/qat.ini | 1 +
doc/guides/rel_notes/release_19_11.rst | 4 +
drivers/crypto/qat/qat_asym.c | 312 -
drivers/crypto/qat/qat_asym.h | 26 +--
drivers/crypto/qat/qat_asym_pmd.c | 3 +-
5 files changed, 202 insertions(+), 144 deletions(-)
diff --git a/doc/guides/cryptodevs/features/qat.ini
b/doc/guides/cryptodevs/features/qat.ini
index 0832e59..cef8015 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -13,6 +13,7 @@ OOP SGL In LB Out = Y
OOP LB In SGL Out = Y
OOP LB In LB Out = Y
Digest encrypted = Y
+Asymmetric sessionless = Y
;
; Supported crypto algorithms of the 'qat' crypto driver.
diff --git a/doc/guides/rel_notes/release_19_11.rst
b/doc/guides/rel_notes/release_19_11.rst
index 4ede7e8..7730483 100644
--- a/doc/guides/rel_notes/release_19_11.rst
+++ b/doc/guides/rel_notes/release_19_11.rst
@@ -85,6 +85,10 @@ New Features
Added stateful decompression support in the Intel QuickAssist Technology PMD.
Please note that stateful compression is not supported.
+* **Updated the Intel QuickAssist Technology (QAT) asymmetric crypto PMD.**
+
+ Added support for asymmetric session-less operations.
+
* **Added cryptodev API to use asymmetric session-less operation.**
Added session-less option to cryptodev asymmetric API. It works the same way
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 4ddb0e5..bf5d22d 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -26,38 +26,23 @@ static int qat_asym_get_sz_and_func_id(const uint32_t
arr[][2],
return -1;
}
-static void qat_asym_build_req_tmpl(void *sess_private_data,
- struct rte_crypto_asym_xform *xform)
+static inline void qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req)
{
-
- struct icp_qat_fw_pke_request *qat_req;
- struct qat_asym_session *session = sess_private_data;
-
- qat_req = &session->req_tmpl;
memset(qat_req, 0, sizeof(*qat_req));
qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
qat_req->pke_hdr.hdr_flags =
ICP_QAT_FW_COMN_HDR_FLAGS_BUILD
(ICP_QAT_FW_COMN_REQ_FLAG_SET);
- qat_req->pke_hdr.comn_req_flags = 0;
- qat_req->pke_hdr.resrvd1 = 0;
- qat_req->pke_hdr.resrvd2 = 0;
- qat_req->pke_hdr.kpt_mask = 0;
- qat_req->pke_hdr.kpt_rn_mask = 0;
- qat_req->pke_hdr.cd_pars.content_desc_addr = 0;
- qat_req->pke_hdr.cd_pars.content_desc_resrvd = 0;
- qat_req->resrvd1 = 0;
- qat_req->resrvd2 = 0;
- qat_req->next_req_adr = 0;
+}
- if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) {
- qat_req->output_param_count = 1;
- qat_req->input_param_count = 3;
- } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) {
- qat_req->output_param_count = 1;
- qat_req->input_param_count = 2;
- }
+static inline void qat_asym_build_req_tmpl(void *sess_private_data)
+{
+ struct icp_qat_fw_pke_request *qat_req;
+ struct qat_asym_session *session = sess_private_data;
+
+ qat_req = &session->req_tmpl;
+ qat_fill_req_tmpl(qat_req);
}
static size_t max_of(int n, ...)
@@ -90,6 +75,19 @@ static void qat_clear_arrays(struct qat_asym_op_cookie
*cookie,
memset(cookie->output_array[i], 0x0, out_size);
}
+static void qat_clear_arrays_by_alg(struct qat_asym_op_cookie *cookie,
+ enum rte_crypto_asym_xform_type alg, int in_size, int out_size)
+{
+ if (alg == RTE_CRYPTO_ASYM_XFORM_MODEX)
+ qat_clear_arrays(cookie, QAT_ASYM_MODEXP_NUM_IN_PARAMS,
+ QAT_ASYM_MODEXP_NUM_OUT_PARAMS, in_size,
+ out_size);
+ else if (alg == RTE_CRYPTO_ASYM_XFORM_MODINV)
+ qat_clear_arrays(cookie, QAT_ASYM_MODINV_NUM_IN_PARAMS,
+ QAT_ASYM_MODINV_NUM_OUT_PARAMS, in_size,
+ out_size);
+}
+
static int qat_asym_check_nonzero(rte_crypto_param n)
{
if (n.length < 8) {
@@ -120,51 +118,34 @@ static int qat_asym_check_nonzero(rte_crypto_param n)
return 0;
}
-int
-qat_asym_build_request(void *in_op,
- uint8_t *out_msg,
- void *op_cookie,
- __rte_unused enum qat_device_gen qat_dev_gen)
+static int
+qat_asym_fill_arrays(struct rte_crypto_asym_op *asym_op,
+ struct icp_qat_fw_pke_request *qat_req,
+ struct qat_asym_op_cookie *cookie,
+ struct rte_crypto_asym_xform *xform)
{
- struct qat_asym_session *ctx;
- struct rte_crypto_op *op = (struct rte
[dpdk-dev] [PATCH v2 3/5] crypto/qat: add rsa crt implementation to asym pmd
This commit extends RSA implementation by CRT option
Signed-off-by: Arek Kusztal
---
doc/guides/cryptodevs/features/qat.ini | 1 +
doc/guides/rel_notes/release_19_11.rst | 2 +
.../qat/qat_adf/qat_pke_functionality_arrays.h | 9
drivers/crypto/qat/qat_asym.c | 61 +-
drivers/crypto/qat/qat_asym.h | 1 +
drivers/crypto/qat/qat_asym_pmd.c | 3 +-
6 files changed, 74 insertions(+), 3 deletions(-)
diff --git a/doc/guides/cryptodevs/features/qat.ini
b/doc/guides/cryptodevs/features/qat.ini
index 374b523..6e350eb 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -15,6 +15,7 @@ OOP LB In LB Out = Y
Digest encrypted = Y
Asymmetric sessionless = Y
RSA PRIV OP KEY EXP= Y
+RSA PRIV OP KEY QT = Y
;
; Supported crypto algorithms of the 'qat' crypto driver.
diff --git a/doc/guides/rel_notes/release_19_11.rst
b/doc/guides/rel_notes/release_19_11.rst
index e081fb1..730b198 100644
--- a/doc/guides/rel_notes/release_19_11.rst
+++ b/doc/guides/rel_notes/release_19_11.rst
@@ -91,6 +91,8 @@ New Features
Added support for RSA algorithm with pair (n, d) private key representation.
+ Added support for RSA algorithm with quintuple private key representation.
+
* **Added cryptodev API to use asymmetric session-less operation.**
Added session-less option to cryptodev asymmetric API. It works the same way
diff --git a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
index 4f857b9..4921e0c 100644
--- a/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
+++ b/drivers/common/qat/qat_adf/qat_pke_functionality_arrays.h
@@ -67,4 +67,13 @@ static const uint32_t RSA_MODEXP_DEC_IDS[][2] = {
{ 4096, PKE_RSA_DP1_4096 },
};
+static const uint32_t RSA_MODEXP_DEC_CRT_IDS[][2] = {
+ { 512, PKE_RSA_DP2_512 },
+ { 1024, PKE_RSA_DP2_1024 },
+ { 1536, PKE_RSA_DP2_1536 },
+ { 2048, PKE_RSA_DP2_2048 },
+ { 3072, PKE_RSA_DP2_3072 },
+ { 4096, PKE_RSA_DP2_4096 },
+};
+
#endif
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 8985270..92e4c9c 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -354,8 +354,65 @@ qat_asym_fill_arrays(struct rte_crypto_asym_op *asym_op,
}
if (xform->rsa.key_type == RTE_RSA_KET_TYPE_QT) {
- QAT_LOG(ERR, "RSA CRT not implemented");
- return QAT_ASYM_ERROR_INVALID_PARAM;
+
+ qat_req->input_param_count =
+ QAT_ASYM_RSA_QT_NUM_IN_PARAMS;
+ if
(qat_asym_get_sz_and_func_id(RSA_MODEXP_DEC_CRT_IDS,
+ sizeof(RSA_MODEXP_DEC_CRT_IDS)/
+ sizeof(*RSA_MODEXP_DEC_CRT_IDS),
+ &alg_size, &func_id)) {
+ return QAT_ASYM_ERROR_INVALID_PARAM;
+ }
+ alg_size_in_bytes = alg_size >> 3;
+
+ rte_memcpy(cookie->input_array[1] +
+ (alg_size_in_bytes >> 1) -
+ xform->rsa.qt.p.length
+ , xform->rsa.qt.p.data,
+ xform->rsa.qt.p.length);
+ rte_memcpy(cookie->input_array[2] +
+ (alg_size_in_bytes >> 1) -
+ xform->rsa.qt.q.length
+ , xform->rsa.qt.q.data,
+ xform->rsa.qt.q.length);
+ rte_memcpy(cookie->input_array[3] +
+ (alg_size_in_bytes >> 1) -
+ xform->rsa.qt.dP.length
+ , xform->rsa.qt.dP.data,
+ xform->rsa.qt.dP.length);
+ rte_memcpy(cookie->input_array[4] +
+ (alg_size_in_bytes >> 1) -
+ xform->rsa.qt.dQ.length
+ , xform->rsa.qt.dQ.data,
+ xform->rsa.qt.dQ.length);
+ rte_memcpy(cookie->input_array[5] +
+ (alg_size_in_bytes >> 1) -
+
[dpdk-dev] [PATCH v2 5/5] test/crypto: add rsa tests to qat
This commit adds RSA tests to Intel QuickAssist Technology pmd
test suite
Signed-off-by: Arek Kusztal
---
app/test/test_cryptodev_asym.c | 115 ++--
app/test/test_cryptodev_rsa_test_vectors.h | 213 +
2 files changed, 313 insertions(+), 15 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index 31d8bfa..66d0ec5 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -54,6 +54,7 @@ struct crypto_unittest_params {
union test_case_structure {
struct modex_test_data modex;
struct modinv_test_data modinv;
+ struct rsa_test_data_2 rsa_data;
};
struct test_cases_array {
@@ -246,10 +247,12 @@ queue_ops_rsa_enc_dec(struct rte_cryptodev_asym_session
*sess)
return status;
}
static int
-test_cryptodev_asym_ver(union test_case_structure *data_tc,
- struct rte_crypto_op *result_op)
+test_cryptodev_asym_ver(struct rte_crypto_op *op,
+ struct rte_crypto_asym_xform *xform_tc,
+ union test_case_structure *data_tc,
+ struct rte_crypto_op *result_op)
{
- int status = TEST_SUCCESS;
+ int status = TEST_FAILED;
int ret = 0;
uint8_t *data_expected = NULL, *data_received = NULL;
size_t data_size = 0;
@@ -265,17 +268,29 @@ test_cryptodev_asym_ver(union test_case_structure
*data_tc,
data_received = result_op->asym->modinv.result.data;
data_size = result_op->asym->modinv.result.length;
break;
+ case RTE_CRYPTO_ASYM_XFORM_RSA:
+ if (op->asym->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT) {
+ data_size = xform_tc->rsa.n.length;
+ data_received = result_op->asym->rsa.cipher.data;
+ data_expected = data_tc->rsa_data.ct.data;
+ } else if (op->asym->rsa.op_type == RTE_CRYPTO_ASYM_OP_DECRYPT)
{
+ data_size = xform_tc->rsa.n.length;
+ data_expected = data_tc->rsa_data.pt.data;
+ data_received = result_op->asym->rsa.message.data;
+ while (*data_received == 0 && data_size--)
+ data_received++;
+ }
+ break;
case RTE_CRYPTO_ASYM_XFORM_DH:
case RTE_CRYPTO_ASYM_XFORM_DSA:
- case RTE_CRYPTO_ASYM_XFORM_RSA:
case RTE_CRYPTO_ASYM_XFORM_NONE:
case RTE_CRYPTO_ASYM_XFORM_UNSPECIFIED:
default:
break;
}
ret = memcmp(data_expected, data_received, data_size);
- if (ret)
- status = TEST_FAILED;
+ if (!ret && data_size)
+ status = TEST_SUCCESS;
return status;
}
@@ -283,7 +298,8 @@ test_cryptodev_asym_ver(union test_case_structure *data_tc,
static int
test_cryptodev_asym_op(struct crypto_testsuite_params *ts_params,
union test_case_structure *data_tc,
- char *test_msg, int sessionless)
+ char *test_msg, int sessionless, enum rte_crypto_asym_op_type type,
+ enum rte_crypto_rsa_priv_key_type key_type)
{
struct rte_crypto_asym_op *asym_op = NULL;
struct rte_crypto_op *op = NULL;
@@ -368,9 +384,44 @@ test_cryptodev_asym_op(struct crypto_testsuite_params
*ts_params,
goto error_exit;
}
break;
+ case RTE_CRYPTO_ASYM_XFORM_RSA:
+ result = rte_zmalloc(NULL, data_tc->rsa_data.n.len, 0);
+ op->asym->rsa.op_type = type;
+ xform_tc.rsa.e.data = data_tc->rsa_data.e.data;
+ xform_tc.rsa.e.length = data_tc->rsa_data.e.len;
+ xform_tc.rsa.d.data = data_tc->rsa_data.d.data;
+ xform_tc.rsa.d.length = data_tc->rsa_data.d.len;
+ xform_tc.rsa.n.data = data_tc->rsa_data.n.data;
+ xform_tc.rsa.n.length = data_tc->rsa_data.n.len;
+
+ xform_tc.rsa.qt.p.data = data_tc->rsa_data.p.data;
+ xform_tc.rsa.qt.p.length = data_tc->rsa_data.p.len;
+ xform_tc.rsa.qt.q.data = data_tc->rsa_data.q.data;
+ xform_tc.rsa.qt.q.length = data_tc->rsa_data.q.len;
+ xform_tc.rsa.qt.dP.data = data_tc->rsa_data.dP.data;
+ xform_tc.rsa.qt.dP.length = data_tc->rsa_data.dP.len;
+ xform_tc.rsa.qt.dQ.data = data_tc->rsa_data.dQ.data;
+ xform_tc.rsa.qt.dQ.length = data_tc->rsa_data.dQ.len;
+ xform_tc.rsa.qt.qInv.data = data_tc->rsa_data.qInv.data;
+ xform_tc.rsa.qt.qInv.length = data_tc->rsa_data.qInv.len;
+
+ xform_tc.rsa.key_type = key_type;
+ op->asym->rsa.pad = data_tc->rsa_data.padding;
+
+ if (op->asym->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT) {
+ as
[dpdk-dev] [PATCH v2 4/5] test/crypto: add sessionless to asymmetric mod exp
This commmit adds asymmetric sessionless tests to mod exp
int test_cryptodev test file
Signed-off-by: Arek Kusztal
---
app/test/test_cryptodev_asym.c | 73 --
1 file changed, 49 insertions(+), 24 deletions(-)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index e8177e7..31d8bfa 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -283,7 +283,7 @@ test_cryptodev_asym_ver(union test_case_structure *data_tc,
static int
test_cryptodev_asym_op(struct crypto_testsuite_params *ts_params,
union test_case_structure *data_tc,
- char *test_msg)
+ char *test_msg, int sessionless)
{
struct rte_crypto_asym_op *asym_op = NULL;
struct rte_crypto_op *op = NULL;
@@ -382,27 +382,31 @@ test_cryptodev_asym_op(struct crypto_testsuite_params
*ts_params,
goto error_exit;
}
- sess = rte_cryptodev_asym_session_create(ts_params->session_mpool);
- if (!sess) {
- snprintf(test_msg, ASYM_TEST_MSG_LEN,
- "line %u "
- "FAILED: %s", __LINE__,
- "Session creation failed");
- status = TEST_FAILED;
- goto error_exit;
- }
-
- if (rte_cryptodev_asym_session_init(dev_id, sess, &xform_tc,
- ts_params->session_mpool) < 0) {
- snprintf(test_msg, ASYM_TEST_MSG_LEN,
- "line %u FAILED: %s",
- __LINE__, "unabled to config sym session");
- status = TEST_FAILED;
- goto error_exit;
- }
+ if (!sessionless) {
+ sess =
rte_cryptodev_asym_session_create(ts_params->session_mpool);
+ if (!sess) {
+ snprintf(test_msg, ASYM_TEST_MSG_LEN,
+ "line %u "
+ "FAILED: %s", __LINE__,
+ "Session creation failed");
+ status = TEST_FAILED;
+ goto error_exit;
+ }
- rte_crypto_op_attach_asym_session(op, sess);
+ if (rte_cryptodev_asym_session_init(dev_id, sess, &xform_tc,
+ ts_params->session_mpool) < 0) {
+ snprintf(test_msg, ASYM_TEST_MSG_LEN,
+ "line %u FAILED: %s",
+ __LINE__, "unabled to config sym
session");
+ status = TEST_FAILED;
+ goto error_exit;
+ }
+ rte_crypto_op_attach_asym_session(op, sess);
+ } else {
+ asym_op->xform = &xform_tc;
+ op->sess_type = RTE_CRYPTO_OP_SESSIONLESS;
+ }
RTE_LOG(DEBUG, USER1, "Process ASYM operation");
/* Process crypto operation */
@@ -433,7 +437,10 @@ test_cryptodev_asym_op(struct crypto_testsuite_params
*ts_params,
goto error_exit;
}
- snprintf(test_msg, ASYM_TEST_MSG_LEN, "PASS");
+ if (!sessionless)
+ snprintf(test_msg, ASYM_TEST_MSG_LEN, "PASS");
+ else
+ snprintf(test_msg, ASYM_TEST_MSG_LEN, "SESSIONLESS PASS");
error_exit:
if (sess != NULL) {
@@ -451,7 +458,7 @@ test_cryptodev_asym_op(struct crypto_testsuite_params
*ts_params,
}
static int
-test_one_case(const void *test_case)
+test_one_case(const void *test_case, int sessionless)
{
int status = TEST_SUCCESS;
char test_msg[ASYM_TEST_MSG_LEN + 1];
@@ -460,7 +467,8 @@ test_one_case(const void *test_case)
union test_case_structure tc;
memcpy(&tc, test_case, sizeof(tc));
- status = test_cryptodev_asym_op(&testsuite_params, &tc, test_msg);
+ status = test_cryptodev_asym_op(&testsuite_params, &tc, test_msg,
+ sessionless);
printf(" %u) TestCase %s %s\n", test_index++,
tc.modex.description, test_msg);
@@ -501,14 +509,31 @@ static int
test_one_by_one(void)
{
int status = TEST_SUCCESS;
+ struct crypto_testsuite_params *ts_params = &testsuite_params;
uint32_t i = 0;
+ uint8_t dev_id = ts_params->valid_devs[0];
+ struct rte_cryptodev_info dev_info;
+ int sessionless = 0;
+
+ rte_cryptodev_info_get(dev_id, &dev_info);
+ if ((dev_info.feature_flags &
+ RTE_CRYPTODEV_FF_ASYM_SESSIONLESS)) {
+ sessionless = 1;
+ }
/* Go through all test cases */
test_index = 0;
for (i = 0; i < test_vector.size; i++) {
- if (test_one_case(test_vector.address[i]) != TEST_SUCCESS)
+ if (test_one_case(test_vector.address[i], 0) != TEST_SUCCESS)
status = TEST_FAILED;
}
+ if (sessionless) {
Re: [dpdk-dev] [PATCH v11 4/9] vhost: add two new messages to support a shared buffer
On 10/9/19 10:48 PM, Jin Yu wrote: > This patch introduces two new messages VHOST_USER_GET_INFLIGHT_FD > and VHOST_USER_SET_INFLIGHT_FD to support transferring a shared > buffer between qemu and backend. > > Signed-off-by: Lin Li > Signed-off-by: Xun Ni > Signed-off-by: Yu Zhang > Signed-off-by: Jin Yu > --- > lib/librte_vhost/vhost.h | 7 + > lib/librte_vhost/vhost_user.c | 243 +- > lib/librte_vhost/vhost_user.h | 4 +- > 3 files changed, 252 insertions(+), 2 deletions(-) Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v11 5/9] vhost: checkout the resubmit inflight information
On 10/9/19 10:48 PM, Jin Yu wrote: > This patch shows how to checkout the inflight ring and construct > the resubmit information also include destroying resubmit info. > > Signed-off-by: Lin Li > Signed-off-by: Xun Ni > Signed-off-by: Yu Zhang > Signed-off-by: Jin Yu > --- > lib/librte_vhost/rte_vhost.h | 19 +++ > lib/librte_vhost/vhost.c | 29 - > lib/librte_vhost/vhost.h | 9 ++ > lib/librte_vhost/vhost_user.c | 217 +- > 4 files changed, 271 insertions(+), 3 deletions(-) > Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v11 6/9] vhost: add the APIs to operate inflight ring
On 10/9/19 10:48 PM, Jin Yu wrote: > This patch introduces three APIs to operate the inflight > ring. Three APIs are set, set last and clear. It includes > split and packed ring. > > Signed-off-by: Lin Li > Signed-off-by: Xun Ni > Signed-off-by: Yu Zhang > Signed-off-by: Jin Yu > --- > lib/librte_vhost/rte_vhost.h | 116 +++ > lib/librte_vhost/rte_vhost_version.map | 6 + > lib/librte_vhost/vhost.c | 273 + > 3 files changed, 395 insertions(+) > Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v11 7/9] vhost: add APIs for user getting inflight ring
On 10/9/19 10:48 PM, Jin Yu wrote: > This patch introduces two APIs. one is for getting inflgiht s/inflgiht/inflight/ > ring and the other is for getting base. > > Signed-off-by: Lin Li > Signed-off-by: Xun Ni > Signed-off-by: Yu Zhang > Signed-off-by: Jin Yu > --- > lib/librte_vhost/rte_vhost.h | 40 + > lib/librte_vhost/rte_vhost_version.map | 2 + > lib/librte_vhost/vhost.c | 61 ++ > 3 files changed, 103 insertions(+) > Other than the typo that I'll fix while applying: Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v11 8/9] vhost: add vring functions packed ring support
On 10/9/19 10:48 PM, Jin Yu wrote: > This patch add packed ring support in two APIs > so user can get the packed ring`. > > Signed-off-by: Lin Li > Signed-off-by: Xun Ni > Signed-off-by: Yu Zhang > Signed-off-by: Jin Yu > --- > lib/librte_vhost/vhost.c | 68 +--- > 1 file changed, 49 insertions(+), 19 deletions(-) > Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v11 9/9] vhost: add vhost-user-blk example which support inflight
On 10/9/19 10:48 PM, Jin Yu wrote: > A vhost-user-blk example that support inflight feature. It uses the > new APIs that introduced in the first patch, so it can show how these > APIs work to support inflight feature. > > Signed-off-by: Jin Yu > --- > V1 - add the case. > V2 - add the rte_vhost prefix. > V3 - add packed ring support > --- > examples/vhost_blk/Makefile | 68 ++ > examples/vhost_blk/blk.c | 125 +++ > examples/vhost_blk/blk_spec.h | 95 +++ > examples/vhost_blk/meson.build| 21 + > examples/vhost_blk/vhost_blk.c| 1092 + > examples/vhost_blk/vhost_blk.h| 128 +++ > examples/vhost_blk/vhost_blk_compat.c | 195 + > 7 files changed, 1724 insertions(+) > create mode 100644 examples/vhost_blk/Makefile > create mode 100644 examples/vhost_blk/blk.c > create mode 100644 examples/vhost_blk/blk_spec.h > create mode 100644 examples/vhost_blk/meson.build > create mode 100644 examples/vhost_blk/vhost_blk.c > create mode 100644 examples/vhost_blk/vhost_blk.h > create mode 100644 examples/vhost_blk/vhost_blk_compat.c > Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v5 3/5] ipsec: add SAD add/delete/lookup implementation
> int
> -rte_ipsec_sad_lookup(__rte_unused const struct rte_ipsec_sad *sad,
> - __rte_unused const union rte_ipsec_sad_key *keys[],
> - __rte_unused void *sa[], __rte_unused uint32_t n)
> +rte_ipsec_sad_lookup(const struct rte_ipsec_sad *sad,
> + const union rte_ipsec_sad_key *keys[], void *sa[], uint32_t n)
> {
> - return -ENOTSUP;
> + uint32_t num, i = 0;
> + int found = 0;
> +
> + if (unlikely((sad == NULL) || (keys == NULL) || (sa == NULL)))
> + return -EINVAL;
> +
> + do {
> + num = RTE_MIN(n - i,
> (uint32_t)RTE_HASH_LOOKUP_BULK_MAX);
> + found += __ipsec_sad_lookup(sad,
> + &keys[i], &sa[i], num);
> + i += num;
> + } while (i != n);
> +
> + return found;
> }
rte_ipsec_sad_lookup should return 0 or a negative value as per the comments in
the declaration.
But here it is returning more than 0. Something is not correct here.
> --
> 2.7.4
[dpdk-dev] rte_mempool_get_bulk uses either cache or common pool
The rte_mempool_get_bulk() documentation says: "If cache is enabled, objects will be retrieved first from cache, subsequently from the common pool." But __mempool_generic_get() only uses the cache if the request is smaller than the cache size. If not, objects will be retrieved from the common pool only. Either the documentation should be corrected, or the implementation should behave as described, i.e. retrieve the first of the objects from the cache and the remaining objects from the common pool. PS: I stumbled into this while writing the unit test for mbuf bulk alloc/free. PPS: It seems unit tests for mempool bulk alloc/free are missing. :-) Med venlig hilsen / kind regards - Morten Brørup
Re: [dpdk-dev] [PATCH v5 0/5] ipsec: add inbound SAD
> -Original Message- > From: Vladimir Medvedkin > Sent: Thursday, October 10, 2019 10:19 PM > To: dev@dpdk.org > Cc: konstantin.anan...@intel.com; bernard.iremon...@intel.com; Akhil Goyal > > Subject: [PATCH v5 0/5] ipsec: add inbound SAD > > According to RFC 4301 IPSec implementation needs an inbound SA database > (SAD). > For each incoming inbound IPSec-protected packet (ESP or AH) it has to > perform a lookup within it’s SAD. > Lookup should be performed by: > Security Parameters Index (SPI) + destination IP (DIP) + source IP (SIP) > or SPI + DIP > or SPI only > and an implementation has to return the “longest” existing match. > These series extend DPDK IPsec library with SAD table implementation that: > - conforms to the RFC requirements above > - can scale up to millions of entries > - supports fast lookups > - supports incremental updates > > Initial series provide an API to create/destroy SAD, and to > add/delete/lookup entries within given SAD table. > Under the hood it uses three librte_hash tables each of which contains > an entries for a specific SA type (either it is addressed by SPI only > or SPI+DIP or SPI+DIP+SIP) Also this patch series introduce test-sad > application to measure performance of the library. According to our > measurements on SKX for 1M entries average lookup cost is ~80 cycles, > average add cost ~500 cycles. > > Next Steps: > - integration with ipsec-secgw > - documentation I believe documentation should be part of this patchset combined with the patches which introduce that API. Apart from that, 0ne comment is there on the lookup API return value. Integration with IPSec Application can be done separately. No issues with that. With this series, I think we don’t need the changes done in http://patches.dpdk.org/user/todo/dpdk/?series=6499 If it is agreed, I will move it as Rejected. With Above changes - Series Acked-by: Akhil Goyal Please send these changes so that I can merge this series. > > v5: > - small fix in rte_ipsec_sad_create() > - add comments in rte_ipsec_sad.h > > v4: > - fixes in test-sad app > - small fixes in rte_ipsec_sad_create() > - fixes in test_find_existing() from unittests > > v3: > - fixes in rte_ipsec_sad_create() and rte_ipsec_sad_find_existing() > - fix typos > - updated commit messages > - added test_find_existing() in unittests > > v2: > - various bugs fixed > - rte_ipsec_sad_free renamed to rte_ipsec_sad_destroy > - added const qualifier to rte_ipsec_sad_key *key for add/delete > - added more comments into the code > - added ipv6 support into the testsad app > - added measurement into the testsad app > - random SPI values are generated without dups > - added support for configurable burst size in testsad app > - added verbose mode into the testsad app > > > Vladimir Medvedkin (5): > ipsec: add inbound SAD API > ipsec: add SAD create/destroy implementation > ipsec: add SAD add/delete/lookup implementation > test/ipsec: add ipsec SAD autotests > app: add test-sad application > > app/Makefile | 1 + > app/meson.build| 3 +- > app/test-sad/Makefile | 18 + > app/test-sad/main.c| 644 > app/test-sad/meson.build | 6 + > app/test/Makefile | 1 + > app/test/autotest_data.py | 6 + > app/test/meson.build | 1 + > app/test/test_ipsec_sad.c | 887 > + > lib/librte_ipsec/Makefile | 4 +- > lib/librte_ipsec/ipsec_sad.c | 515 +++ > lib/librte_ipsec/meson.build | 6 +- > lib/librte_ipsec/rte_ipsec_sad.h | 176 +++ > lib/librte_ipsec/rte_ipsec_version.map | 7 + > 14 files changed, 2270 insertions(+), 5 deletions(-) > create mode 100644 app/test-sad/Makefile > create mode 100644 app/test-sad/main.c > create mode 100644 app/test-sad/meson.build > create mode 100644 app/test/test_ipsec_sad.c > create mode 100644 lib/librte_ipsec/ipsec_sad.c > create mode 100644 lib/librte_ipsec/rte_ipsec_sad.h > > -- > 2.7.4
Re: [dpdk-dev] [PATCH v3] build: add emag(arm64) platform and default config
On Wed, Oct 9, 2019 at 8:15 AM Gavin Hu wrote: > > From: Jerry Hao OS > I think the subject can be changed to "build: add emag target " > config: add emag configuration > mk/machine: add emag machine configurations The above lines are not a sentence. Please make it as a sentence in the git commit. > > eMAG is Ampere Computing 64-bit ARM processor > with 32 Arm v8 64-bit CPU cores. > For more information, refer to: > https://amperecomputing.com/product/ > > Signed-off-by: Jerry Hao OS > Signed-off-by: Gavin Hu With the above changes: Acked-by: Jerin Jacob > --- > V3: > - add "mtune=emag" to generate optimized code for emag > V2: > - add meson build support > > config/arm/arm64_emag_linux_gcc | 15 +++ > config/arm/meson.build | 11 ++- > config/defconfig_arm64-emag-linux-gcc| 1 + > config/defconfig_arm64-emag-linuxapp-gcc | 11 +++ > mk/machine/emag/rte.vars.mk | 32 > > 5 files changed, 69 insertions(+), 1 deletion(-) > create mode 100644 config/arm/arm64_emag_linux_gcc > create mode 12 config/defconfig_arm64-emag-linux-gcc > create mode 100644 config/defconfig_arm64-emag-linuxapp-gcc > create mode 100644 mk/machine/emag/rte.vars.mk > > diff --git a/config/arm/arm64_emag_linux_gcc b/config/arm/arm64_emag_linux_gcc > new file mode 100644 > index 000..bcb147a > --- /dev/null > +++ b/config/arm/arm64_emag_linux_gcc > @@ -0,0 +1,15 @@ > +[binaries] > +c = 'aarch64-linux-gnu-gcc' > +cpp = 'aarch64-linux-gnu-cpp' > +ar = 'aarch64-linux-gnu-gcc-ar' > +strip = 'aarch64-linux-gnu-strip' > +pcap-config = '' > + > +[host_machine] > +system = 'linux' > +cpu_family = 'aarch64' > +cpu = 'armv8-a' > +endian = 'little' > + > +[properties] > +implementor_id = '0x50' > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 979018e..aa73e1d 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -61,6 +61,11 @@ flags_armada = [ > ['RTE_CACHE_LINE_SIZE', 64], > ['RTE_MAX_NUMA_NODES', 1], > ['RTE_MAX_LCORE', 16]] > +flags_emag = [ > + ['RTE_MACHINE', '"emag"'], > + ['RTE_CACHE_LINE_SIZE', 64], > + ['RTE_MAX_NUMA_NODES', 1], > + ['RTE_MAX_LCORE', 32]] > > flags_default_extra = [] > flags_thunderx_extra = [ > @@ -98,6 +103,10 @@ machine_args_cavium = [ > ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], > flags_thunderx2_extra], > ['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]] > > +machine_args_emag = [ > + ['default', ['-march=armv8-a+crc+crypto', '-mtune=emag']], > + ['native', ['-march=native']]] > + > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic = ['Generic armv8', flags_generic, machine_args_generic] > impl_0x41 = ['Arm', flags_arm, machine_args_generic] > @@ -107,7 +116,7 @@ impl_0x44 = ['DEC', flags_generic, machine_args_generic] > impl_0x49 = ['Infineon', flags_generic, machine_args_generic] > impl_0x4d = ['Motorola', flags_generic, machine_args_generic] > impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic] > -impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic] > +impl_0x50 = ['Ampere Computing', flags_emag, machine_args_emag] > impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic] > impl_0x53 = ['Samsung', flags_generic, machine_args_generic] > impl_0x56 = ['Marvell ARMADA', flags_armada, machine_args_generic] > diff --git a/config/defconfig_arm64-emag-linux-gcc > b/config/defconfig_arm64-emag-linux-gcc > new file mode 12 > index 000..21894a3 > --- /dev/null > +++ b/config/defconfig_arm64-emag-linux-gcc > @@ -0,0 +1 @@ > +defconfig_arm64-emag-linuxapp-gcc > \ No newline at end of file > diff --git a/config/defconfig_arm64-emag-linuxapp-gcc > b/config/defconfig_arm64-emag-linuxapp-gcc > new file mode 100644 > index 000..1db654c > --- /dev/null > +++ b/config/defconfig_arm64-emag-linuxapp-gcc > @@ -0,0 +1,11 @@ > +# SPDX-License-Identifier: BSD-3-Clause > +# Copyright(c) 2019 Ampere Computing > +# > + > +#include "defconfig_arm64-armv8a-linux-gcc" > + > +CONFIG_RTE_MACHINE="emag" > + > +CONFIG_RTE_CACHE_LINE_SIZE=64 > +CONFIG_RTE_MAX_NUMA_NODES=1 > +CONFIG_RTE_MAX_LCORE=32 > diff --git a/mk/machine/emag/rte.vars.mk b/mk/machine/emag/rte.vars.mk > new file mode 100644 > index 000..50342df > --- /dev/null > +++ b/mk/machine/emag/rte.vars.mk > @@ -0,0 +1,32 @@ > +# SPDX-License-Identifier: BSD-3-Clause > +# Copyright(c) 2019 Ampere Computing > +# > + > +# > +# machine: > +# > +# - can define ARCH variable (overridden by cmdline value) > +# - can define CROSS variable (overridden by cmdline value) > +# - define MACHINE_CFLAGS variable (overridden by cmdline value) > +# - define MACHINE_LDFLAGS variable (overridden by cmdline value) > +# - define MACHINE_ASFLAGS variable (overridden by cmdline value) > +# - can define CPU_CFLAGS variable (overridden by cmd
[dpdk-dev] [PATCH v8 2/2] mbuf: add unit test for bulk alloc/free functions
Add unit test for functions for allocating and freeing a bulk of mbufs.
Signed-off-by: Morten Brørup
---
app/test/test_mbuf.c | 171 +++
1 file changed, 171 insertions(+)
diff --git a/app/test/test_mbuf.c b/app/test/test_mbuf.c
index 2a97afe20..fbce0ca7c 100644
--- a/app/test/test_mbuf.c
+++ b/app/test/test_mbuf.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
#include
@@ -545,6 +546,170 @@ test_pktmbuf_pool(struct rte_mempool *pktmbuf_pool)
return ret;
}
+/*
+ * test bulk allocation and bulk free of mbufs
+ */
+static int
+test_pktmbuf_pool_bulk(void)
+{
+ struct rte_mempool *pool = NULL;
+ struct rte_mempool *pool2 = NULL;
+ unsigned int i;
+ struct rte_mbuf *m;
+ struct rte_mbuf *mbufs[NB_MBUF];
+ int ret = 0;
+
+ /* We cannot use the preallocated mbuf pools because their caches
+* prevent us from bulk allocating all objects in them.
+* So we create our own mbuf pools without caches.
+*/
+ printf("Create mbuf pools for bulk allocation.\n");
+ pool = rte_pktmbuf_pool_create("test_pktmbuf_bulk",
+ NB_MBUF, 0, 0, MBUF_DATA_SIZE, SOCKET_ID_ANY);
+ if (pool == NULL) {
+ printf("rte_pktmbuf_pool_create() failed. rte_errno %d\n",
+ rte_errno);
+ goto err;
+ }
+ pool2 = rte_pktmbuf_pool_create("test_pktmbuf_bulk2",
+ NB_MBUF, 0, 0, MBUF_DATA_SIZE, SOCKET_ID_ANY);
+ if (pool2 == NULL) {
+ printf("rte_pktmbuf_pool_create() failed. rte_errno %d\n",
+ rte_errno);
+ goto err;
+ }
+
+ /* Preconditions: Mempools must be full. */
+ if (!(rte_mempool_full(pool) && rte_mempool_full(pool2))) {
+ printf("Test precondition failed: mempools not full\n");
+ goto err;
+ }
+ if (!(rte_mempool_avail_count(pool) == NB_MBUF &&
+ rte_mempool_avail_count(pool2) == NB_MBUF)) {
+ printf("Test precondition failed: mempools: %u+%u != %u+%u",
+ rte_mempool_avail_count(pool),
+ rte_mempool_avail_count(pool2),
+ NB_MBUF, NB_MBUF);
+ goto err;
+ }
+
+ printf("Test single bulk alloc, followed by multiple bulk free.\n");
+
+ /* Bulk allocate all mbufs in the pool, in one go. */
+ ret = rte_pktmbuf_alloc_bulk(pool, mbufs, NB_MBUF);
+ if (ret != 0) {
+ printf("rte_pktmbuf_alloc_bulk() failed: %d\n", ret);
+ goto err;
+ }
+ /* Test that they have been removed from the pool. */
+ if (!rte_mempool_empty(pool)) {
+ printf("mempool not empty\n");
+ goto err;
+ }
+ /* Bulk free all mbufs, in four steps. */
+ for (i = 0; i < NB_MBUF; i += NB_MBUF / 4) {
+ rte_pktmbuf_free_bulk(&mbufs[i], NB_MBUF / 4);
+ /* Test that they have been returned to the pool. */
+ if (rte_mempool_avail_count(pool) != i + NB_MBUF / 4) {
+ printf("mempool avail count incorrect\n");
+ goto err;
+ }
+ }
+
+ printf("Test multiple bulk alloc, followed by single bulk free.\n");
+
+ /* Bulk allocate all mbufs in the pool, in four steps. */
+ for (i = 0; i < NB_MBUF; i += NB_MBUF / 4) {
+ ret = rte_pktmbuf_alloc_bulk(pool, &mbufs[i], NB_MBUF / 4);
+ if (ret != 0) {
+ printf("rte_pktmbuf_alloc_bulk() failed: %d\n", ret);
+ goto err;
+ }
+ }
+ /* Test that they have been removed from the pool. */
+ if (!rte_mempool_empty(pool)) {
+ printf("mempool not empty\n");
+ goto err;
+ }
+ /* Bulk free all mbufs, in one go. */
+ rte_pktmbuf_free_bulk(mbufs, NB_MBUF);
+ /* Test that they have been returned to the pool. */
+ if (!rte_mempool_full(pool)) {
+ printf("mempool not full\n");
+ goto err;
+ }
+
+ printf("Test bulk free of single long chain.\n");
+
+ /* Bulk allocate all mbufs in the pool, in one go. */
+ ret = rte_pktmbuf_alloc_bulk(pool, mbufs, NB_MBUF);
+ if (ret != 0) {
+ printf("rte_pktmbuf_alloc_bulk() failed: %d\n", ret);
+ goto err;
+ }
+ /* Create a long mbuf chain. */
+ for (i = 1; i < NB_MBUF; i++) {
+ ret = rte_pktmbuf_chain(mbufs[0], mbufs[i]);
+ if (ret != 0) {
+ printf("rte_pktmbuf_chain() failed: %d\n", ret);
+ goto err;
+ }
+ mbufs[i] = NULL;
+ }
+ /* Free the mbuf chain containing all the mbufs. */
+ rte_pktmbuf_free_bulk(mbufs, 1);
+ /* Test that they have
[dpdk-dev] [PATCH v8 1/2] mbuf: add bulk free function
Add function for freeing a bulk of mbufs.
Signed-off-by: Morten Brørup
Acked-by: Konstantin Ananyev
Reviewed-by: Andrew Rybchenko
Acked-by: Stephen Hemminger
---
v8:
* Add unit test, covering both bulk alloc and bulk free.
v7:
* Squash multiple modifications into one.
v6:
* Remove __rte_always_inline from static function.
The compiler will inline anyway.
v5:
* Rename variables from "free" to "pending" for improved readability.
* Add prefix __ to rte_pktmbuf_free_seg_via_array().
* Add array size parameter to __rte_pktmbuf_free_seg_via_array().
The compiler will optimize the parameter away anyway.
* Add description to __rte_pktmbuf_free_seg_via_array().
* Minor description updates.
v4:
* Mark as experimental by adding __rte_experimental.
* Add function to experimental section of map file.
* Fix source code formatting regarding pointer to pointer.
* Squash multiple modifications into one.
v3:
* Bugfix: Handle pakets with multiple segments.
* Add inline helper function, mainly for readability.
* Fix source code formatting regarding indentation.
v2:
* Function is not inline.
* Optimize to free multible mbufs belonging to the same mempool in
bulk. Inspired by ixgbe_tx_free_bufs(), but allowing NULL pointers
in the array, just like rte_pktmbuf_free() can take a NULL pointer.
* Use unsigned int instead of unsigned. Passes checkpatch, but
mismatches the original coding style of the modified files.
* Fix a typo in the description headline: mempools is plural.
---
lib/librte_mbuf/rte_mbuf.c | 66
lib/librte_mbuf/rte_mbuf.h | 15 +++
lib/librte_mbuf/rte_mbuf_version.map | 1 +
3 files changed, 82 insertions(+)
diff --git a/lib/librte_mbuf/rte_mbuf.c b/lib/librte_mbuf/rte_mbuf.c
index 37718d49c..854af1104 100644
--- a/lib/librte_mbuf/rte_mbuf.c
+++ b/lib/librte_mbuf/rte_mbuf.c
@@ -245,6 +245,72 @@ int rte_mbuf_check(const struct rte_mbuf *m, int is_header,
return 0;
}
+/**
+ * @internal helper function for freeing a bulk of packet mbuf segments
+ * via an array holding the packet mbuf segments from the same mempool
+ * pending to be freed.
+ *
+ * @param m
+ * The packet mbuf segment to be freed.
+ * @param pending
+ * Pointer to the array of packet mbuf segments pending to be freed.
+ * @param nb_pending
+ * Pointer to the number of elements held in the array.
+ * @param pending_sz
+ * Number of elements the array can hold.
+ * Note: The compiler should optimize this parameter away when using a
+ * constant value, such as RTE_PKTMBUF_FREE_PENDING_SZ.
+ */
+static void
+__rte_pktmbuf_free_seg_via_array(struct rte_mbuf *m,
+ struct rte_mbuf ** const pending, unsigned int * const nb_pending,
+ const unsigned int pending_sz)
+{
+ m = rte_pktmbuf_prefree_seg(m);
+ if (likely(m != NULL)) {
+ if (*nb_pending == pending_sz ||
+ (*nb_pending > 0 && m->pool != pending[0]->pool)) {
+ rte_mempool_put_bulk(pending[0]->pool,
+ (void **)pending, *nb_pending);
+ *nb_pending = 0;
+ }
+
+ pending[(*nb_pending)++] = m;
+ }
+}
+
+/**
+ * Size of the array holding mbufs from the same membool pending to be freed
+ * in bulk.
+ */
+#define RTE_PKTMBUF_FREE_PENDING_SZ 64
+
+/* Free a bulk of packet mbufs back into their original mempools. */
+void rte_pktmbuf_free_bulk(struct rte_mbuf **mbufs, unsigned int count)
+{
+ struct rte_mbuf *m, *m_next, *pending[RTE_PKTMBUF_FREE_PENDING_SZ];
+ unsigned int idx, nb_pending = 0;
+
+ for (idx = 0; idx < count; idx++) {
+ m = mbufs[idx];
+ if (unlikely(m == NULL))
+ continue;
+
+ __rte_mbuf_sanity_check(m, 1);
+
+ do {
+ m_next = m->next;
+ __rte_pktmbuf_free_seg_via_array(m,
+ pending, &nb_pending,
+ RTE_PKTMBUF_FREE_PENDING_SZ);
+ m = m_next;
+ } while (m != NULL);
+ }
+
+ if (nb_pending > 0)
+ rte_mempool_put_bulk(pending[0]->pool, (void **)pending,
nb_pending);
+}
+
/* dump a mbuf on console */
void
rte_pktmbuf_dump(FILE *f, const struct rte_mbuf *m, unsigned dump_len)
diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h
index 98225ec80..a02c8b12c 100644
--- a/lib/librte_mbuf/rte_mbuf.h
+++ b/lib/librte_mbuf/rte_mbuf.h
@@ -1907,6 +1907,21 @@ static inline void rte_pktmbuf_free(struct rte_mbuf *m)
}
}
+/**
+ * Free a bulk of packet mbufs back into their original mempools.
+ *
+ * Free a bulk of mbufs, and all their segments in case of chained buffers.
+ * Each segment is added back into its original mempool.
+ *
+ * @param mbufs
+ *Array of pointers to packet mbufs.
+ *The array may contain NULL pointers.
+ * @param count
+ *
[dpdk-dev] [PATCH v8 0/2] mbuf: add bulk free function
Add function for freeing a bulk of mbufs. Add unit test for functions for allocating and freeing a bulk of mbufs. --- v8: * Add unit test, covering both bulk alloc and bulk free. v7: * Squash multiple modifications into one. v6: * Remove __rte_always_inline from static function. The compiler will inline anyway. v5: * Rename variables from "free" to "pending" for improved readability. * Add prefix __ to rte_pktmbuf_free_seg_via_array(). * Add array size parameter to __rte_pktmbuf_free_seg_via_array(). The compiler will optimize the parameter away anyway. * Add description to __rte_pktmbuf_free_seg_via_array(). * Minor description updates. v4: * Mark as experimental by adding __rte_experimental. * Add function to experimental section of map file. * Fix source code formatting regarding pointer to pointer. * Squash multiple modifications into one. v3: * Bugfix: Handle pakets with multiple segments. * Add inline helper function, mainly for readability. * Fix source code formatting regarding indentation. v2: * Function is not inline. * Optimize to free multible mbufs belonging to the same mempool in bulk. Inspired by ixgbe_tx_free_bufs(), but allowing NULL pointers in the array, just like rte_pktmbuf_free() can take a NULL pointer. * Use unsigned int instead of unsigned. Passes checkpatch, but mismatches the original coding style of the modified files. * Fix a typo in the description headline: mempools is plural. Morten Brørup (2): mbuf: add bulk free function mbuf: add unit test for bulk alloc/free functions app/test/test_mbuf.c | 171 +++ lib/librte_mbuf/rte_mbuf.c | 66 +++ lib/librte_mbuf/rte_mbuf.h | 15 +++ lib/librte_mbuf/rte_mbuf_version.map | 1 + 4 files changed, 253 insertions(+) -- 2.17.1
Re: [dpdk-dev] [PATCH v4 01/14] vhost: add single packet enqueue function
On 10/9/19 3:38 PM, Marvin Liu wrote: > Add vhost enqueue function for single packet and meanwhile left space > for flush used ring function. > > Signed-off-by: Marvin Liu > Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v2 0/3] examples/ipsec-secgw: set default
Hi All, This patchset would need ack from more vendors as it will impact user experience on a key example application which is normally demonstrated to customers. IPSec library is still evolving and there are new functionality added every release. Atleast from NXP side we are not OK with this change. I would hold this patch till RC2 atleast. Regards, Akhil > -Original Message- > From: Bernard Iremonger > Sent: Tuesday, October 1, 2019 8:48 PM > To: dev@dpdk.org; konstantin.anan...@intel.com; Akhil Goyal > > Cc: Bernard Iremonger > Subject: [PATCH v2 0/3] examples/ipsec-secgw: set default > > This patch set, sets the default code path in the ipsec-secgw > application to use the librte_ipsec. > The *_old test scripts have been modified to use the legacy code > path. > > Changes in v2: > - > The error messages for the -l option have been updated. > The pktest.sh script has been updated to drop the -l option. > > Bernard Iremonger (3): > examples/ipsec-secgw: set default to IPsec library mode > examples/ipsec-secgw: add -l 0 parameter to old scripts > examples/ipsec-secgw: update pktest.sh script > > doc/guides/rel_notes/release_19_11.rst | 8 > doc/guides/sample_app_ug/ipsec_secgw.rst | 6 ++- > examples/ipsec-secgw/ipsec-secgw.c | 46 > ++ > examples/ipsec-secgw/test/pkttest.sh | 1 - > .../ipsec-secgw/test/trs_3descbc_sha1_old_defs.sh | 2 +- > .../ipsec-secgw/test/trs_aescbc_sha1_old_defs.sh | 2 +- > .../ipsec-secgw/test/trs_aesctr_sha1_old_defs.sh | 2 +- > .../test/trs_aesgcm_inline_crypto_old_defs.sh | 2 +- > examples/ipsec-secgw/test/trs_aesgcm_old_defs.sh | 2 +- > .../ipsec-secgw/test/tun_3descbc_sha1_old_defs.sh | 2 +- > .../ipsec-secgw/test/tun_aescbc_sha1_old_defs.sh | 2 +- > .../ipsec-secgw/test/tun_aesctr_sha1_old_defs.sh | 2 +- > .../test/tun_aesgcm_inline_crypto_old_defs.sh | 2 +- > examples/ipsec-secgw/test/tun_aesgcm_old_defs.sh | 2 +- > 14 files changed, 52 insertions(+), 29 deletions(-) > > -- > 2.7.4
Re: [dpdk-dev] [PATCH v4 02/14] vhost: unify unroll pragma parameter
On 10/9/19 3:38 PM, Marvin Liu wrote:
> Add macro for unifying Clang/ICC/GCC unroll pragma format. Batch
> functions were contained of several small loops which optimized by
> compiler’s loop unrolling pragma.
>
> Signed-off-by: Marvin Liu
>
> diff --git a/lib/librte_vhost/Makefile b/lib/librte_vhost/Makefile
> index 8623e91c0..30839a001 100644
> --- a/lib/librte_vhost/Makefile
> +++ b/lib/librte_vhost/Makefile
> @@ -16,6 +16,24 @@ CFLAGS += -I vhost_user
> CFLAGS += -fno-strict-aliasing
> LDLIBS += -lpthread
>
> +ifeq ($(RTE_TOOLCHAIN), gcc)
> +ifeq ($(shell test $(GCC_VERSION) -ge 83 && echo 1), 1)
> +CFLAGS += -DSUPPORT_GCC_UNROLL_PRAGMA
> +endif
> +endif
> +
> +ifeq ($(RTE_TOOLCHAIN), clang)
> +ifeq ($(shell test $(CLANG_MAJOR_VERSION)$(CLANG_MINOR_VERSION) -ge 37 &&
> echo 1), 1)
> +CFLAGS += -DSUPPORT_CLANG_UNROLL_PRAGMA
> +endif
> +endif
> +
> +ifeq ($(RTE_TOOLCHAIN), icc)
> +ifeq ($(shell test $(ICC_MAJOR_VERSION) -ge 16 && echo 1), 1)
> +CFLAGS += -DSUPPORT_ICC_UNROLL_PRAGMA
> +endif
> +endif
> +
> ifeq ($(CONFIG_RTE_LIBRTE_VHOST_NUMA),y)
> LDLIBS += -lnuma
> endif
> diff --git a/lib/librte_vhost/meson.build b/lib/librte_vhost/meson.build
> index cb1123ae3..ddf0ee579 100644
> --- a/lib/librte_vhost/meson.build
> +++ b/lib/librte_vhost/meson.build
> @@ -8,6 +8,13 @@ endif
> if has_libnuma == 1
> dpdk_conf.set10('RTE_LIBRTE_VHOST_NUMA', true)
> endif
> +if (toolchain == 'gcc' and cc.version().version_compare('>=8.3.0'))
> + cflags += '-DSUPPORT_GCC_UNROLL_PRAGMA'
> +elif (toolchain == 'clang' and cc.version().version_compare('>=3.7.0'))
> + cflags += '-DSUPPORT_CLANG_UNROLL_PRAGMA'
> +elif (toolchain == 'icc' and cc.version().version_compare('>=16.0.0'))
> + cflags += '-DSUPPORT_ICC_UNROLL_PRAGMA'
> +endif
> dpdk_conf.set('RTE_LIBRTE_VHOST_POSTCOPY',
> cc.has_header('linux/userfaultfd.h'))
> version = 4
> diff --git a/lib/librte_vhost/vhost.h b/lib/librte_vhost/vhost.h
> index 884befa85..4cba8c5ef 100644
> --- a/lib/librte_vhost/vhost.h
> +++ b/lib/librte_vhost/vhost.h
> @@ -39,6 +39,24 @@
>
> #define VHOST_LOG_CACHE_NR 32
>
> +#ifdef SUPPORT_GCC_UNROLL_PRAGMA
> +#define UNROLL_PRAGMA_PARAM "GCC unroll 4"
Shouldn't al these defines be either prefixed with VHOST_, or being
declared in EAL headers, so that it can be used by other DPDK libs?
I will pick it as is for now, but please consider above comment and
and send a patch on top if it makes sense.
Thanks,
Maxime
> +#endif
> +
> +#ifdef SUPPORT_CLANG_UNROLL_PRAGMA
> +#define UNROLL_PRAGMA_PARAM "unroll 4"
> +#endif
> +
> +#ifdef SUPPORT_ICC_UNROLL_PRAGMA
> +#define UNROLL_PRAGMA_PARAM "unroll (4)"
> +#endif
> +
> +#ifdef UNROLL_PRAGMA_PARAM
> +#define UNROLL_PRAGMA(param) _Pragma(param)
> +#else
> +#define UNROLL_PRAGMA(param) do {} while (0);
> +#endif
> +
> /**
> * Structure contains buffer address, length and descriptor index
> * from vring to do scatter RX.
>
Re: [dpdk-dev] [PATCH v4 03/14] vhost: add batch enqueue function for packed ring
On 10/9/19 3:38 PM, Marvin Liu wrote: > Batch enqueue function will first check whether descriptors are cache > aligned. It will also check prerequisites in the beginning. Batch > enqueue function not support chained mbufs, single packet enqueue > function will handle it. > > Signed-off-by: Marvin Liu > Reviewed-by: Maxime Coquelin
[dpdk-dev] [PATCH v2 1/5] crypto/octeontx: add device type mailbox routine
From: Kanaka Durga Kotamarthy
Add mailbox communication to query symmetric or asymmetric device type
Signed-off-by: Anoob Joseph
Signed-off-by: Kanaka Durga Kotamarthy
Signed-off-by: Sunila Sahu
---
drivers/common/cpt/cpt_common.h | 3 ---
drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 12 -
drivers/crypto/octeontx/otx_cryptodev_mbox.c | 26 --
drivers/crypto/octeontx/otx_cryptodev_mbox.h | 20 ++
drivers/crypto/octeontx/otx_cryptodev_ops.c | 33 ++-
drivers/crypto/octeontx/otx_cryptodev_ops.h | 2 ++
6 files changed, 78 insertions(+), 18 deletions(-)
diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 32f23ac..7ef6b29 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -19,9 +19,6 @@
#define CPT_COUNT_THOLD32
#define CPT_TIMER_THOLD0x3F
-#define AE_TYPE 1
-#define SE_TYPE 2
-
#ifndef ROUNDUP4
#define ROUNDUP4(val) (((val) + 3) & 0xfffc)
#endif
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index eba6293..ad64bf4 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -386,6 +386,12 @@ otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void
*reg_base, char *name)
return -1;
}
+ /* Gets device type */
+ if (otx_cpt_get_dev_type(cptvf)) {
+ CPT_LOG_ERR("Failed to get device type");
+ return -1;
+ }
+
return 0;
}
@@ -653,12 +659,6 @@ otx_cpt_start_device(void *dev)
return -EFAULT;
}
- if ((cptvf->vftype != SE_TYPE) && (cptvf->vftype != AE_TYPE)) {
- CPT_LOG_ERR("Fatal error, unexpected vf type %u, for CPT VF "
- "device %s", cptvf->vftype, cptvf->dev_name);
- return -ENOENT;
- }
-
return 0;
}
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.c
b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
index daba776..a884ad6 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_mbox.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.c
@@ -42,11 +42,19 @@ otx_cpt_handle_mbox_intr(struct cpt_vf *cptvf)
case OTX_CPT_MSG_QBIND_GRP:
cptvf->pf_acked = true;
cptvf->vftype = mbx.data;
- CPT_LOG_DP_DEBUG("%s: VF %d type %s group %d",
+ CPT_LOG_DP_DEBUG("%s: VF %d group %d",
cptvf->dev_name, cptvf->vfid,
-((mbx.data == SE_TYPE) ? "SE" : "AE"),
cptvf->vfgrp);
break;
+ case OTX_CPT_MSG_PF_TYPE:
+ cptvf->pf_acked = true;
+ if (mbx.data == OTX_CPT_PF_TYPE_AE)
+ cptvf->vftype = OTX_CPT_VF_TYPE_AE;
+ else if (mbx.data == OTX_CPT_PF_TYPE_SE)
+ cptvf->vftype = OTX_CPT_VF_TYPE_SE;
+ else
+ cptvf->vftype = OTX_CPT_VF_TYPE_INVALID;
+ break;
case OTX_CPT_MBOX_MSG_TYPE_ACK:
cptvf->pf_acked = true;
break;
@@ -120,6 +128,20 @@ otx_cpt_check_pf_ready(struct cpt_vf *cptvf)
}
int
+otx_cpt_get_dev_type(struct cpt_vf *cptvf)
+{
+ struct cpt_mbox mbx = {0, 0};
+
+ mbx.msg = OTX_CPT_MSG_PF_TYPE;
+ if (otx_cpt_send_msg_to_pf_timeout(cptvf, &mbx)) {
+ CPT_LOG_ERR("%s: PF didn't respond to query msg",
+ cptvf->dev_name);
+ return 1;
+ }
+ return 0;
+}
+
+int
otx_cpt_send_vq_size_msg(struct cpt_vf *cptvf)
{
struct cpt_mbox mbx = {0, 0};
diff --git a/drivers/crypto/octeontx/otx_cryptodev_mbox.h
b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
index 2d2e0e6..508f3af 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_mbox.h
+++ b/drivers/crypto/octeontx/otx_cryptodev_mbox.h
@@ -23,6 +23,20 @@ struct cpt_mbox {
uint64_t data;
};
+/* CPT PF types */
+enum otx_cpt_pf_type {
+ OTX_CPT_PF_TYPE_INVALID = 0,
+ OTX_CPT_PF_TYPE_AE = 2,
+ OTX_CPT_PF_TYPE_SE,
+};
+
+/* CPT VF types */
+enum otx_cpt_vf_type {
+ OTX_CPT_VF_TYPE_AE = 1,
+ OTX_CPT_VF_TYPE_SE,
+ OTX_CPT_VF_TYPE_INVALID,
+};
+
/* PF-VF message opcodes */
enum otx_cpt_mbox_opcode {
OTX_CPT_MSG_VF_UP = 1,
@@ -63,6 +77,12 @@ int
otx_cpt_check_pf_ready(struct cpt_vf *cptvf);
/*
+ * Communicate to PF to get VF type
+ */
+int
+otx_cpt_get_dev_type(struct cpt_vf *cptvf);
+
+/*
* Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.
* Must be ACKed.
*/
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c
b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 118168a..4c6e266 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/
[dpdk-dev] [PATCH v2 0/5] add asym support in crypto_octeontx PMD
This series adds asymmetric crypto support in 'crypto_octoentx' PMD. Changes in v2: * Squashed patches as directed by Akhil * Split the doc patch and added documentation along with feature * Added check for ASYM SESSIONLESS (not supported currently) * Made separate enqueue & dequeue routines for sym & asym * Minor updates to documentation Kanaka Durga Kotamarthy (3): crypto/octeontx: add device type mailbox routine crypto/octeontx: add asymmetric session operations common/cpt: add helper functions for asymmetric crypto Sunila Sahu (2): crypto/octeontx: add asymmetric enqueue/dequeue ops app/test: register octeontx PMD to asym testsuite app/test/test_cryptodev_asym.c | 31 ++ doc/guides/cryptodevs/features/octeontx.ini| 6 +- doc/guides/cryptodevs/octeontx.rst | 29 +- drivers/common/cpt/cpt_common.h| 4 +- drivers/common/cpt/cpt_mcode_defines.h | 29 ++ drivers/common/cpt/cpt_pmd_ops_helper.c| 15 + drivers/common/cpt/cpt_pmd_ops_helper.h| 9 + drivers/common/cpt/cpt_ucode_asym.h| 453 + drivers/common/cpt/rte_common_cpt_version.map | 8 + .../crypto/octeontx/otx_cryptodev_capabilities.c | 47 ++- .../crypto/octeontx/otx_cryptodev_capabilities.h | 5 +- drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 51 ++- drivers/crypto/octeontx/otx_cryptodev_mbox.c | 26 +- drivers/crypto/octeontx/otx_cryptodev_mbox.h | 20 + drivers/crypto/octeontx/otx_cryptodev_ops.c| 338 +-- drivers/crypto/octeontx/otx_cryptodev_ops.h| 2 + 16 files changed, 1016 insertions(+), 57 deletions(-) create mode 100644 drivers/common/cpt/cpt_ucode_asym.h -- 2.7.4
[dpdk-dev] [PATCH v2 3/5] common/cpt: add helper functions for asymmetric crypto
From: Kanaka Durga Kotamarthy
Add helper functions to get meta len for asymmetric operations
Signed-off-by: Anoob Joseph
Signed-off-by: Kanaka Durga Kotamarthy
Signed-off-by: Sunila Sahu
---
drivers/common/cpt/cpt_pmd_ops_helper.c | 15 +
drivers/common/cpt/cpt_pmd_ops_helper.h | 9 ++
drivers/common/cpt/rte_common_cpt_version.map | 8 +
drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 39 ---
4 files changed, 60 insertions(+), 11 deletions(-)
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.c
b/drivers/common/cpt/cpt_pmd_ops_helper.c
index 1c18180..09b762f 100644
--- a/drivers/common/cpt/cpt_pmd_ops_helper.c
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.c
@@ -11,6 +11,8 @@
#define CPT_MAX_IV_LEN 16
#define CPT_OFFSET_CONTROL_BYTES 8
+#define CPT_MAX_ASYM_OP_NUM_PARAMS 5
+#define CPT_MAX_ASYM_OP_MOD_LEN 1024
int32_t
cpt_pmd_ops_helper_get_mlen_direct_mode(void)
@@ -39,3 +41,16 @@ cpt_pmd_ops_helper_get_mlen_sg_mode(void)
len += 2 * sizeof(cpt_res_s_t);
return len;
}
+
+int
+cpt_pmd_ops_helper_asym_get_mlen(void)
+{
+ uint32_t len;
+
+ /* Get meta len for linear buffer (direct) mode */
+ len = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+ /* Get meta len for asymmetric operations */
+ len += CPT_MAX_ASYM_OP_NUM_PARAMS * CPT_MAX_ASYM_OP_MOD_LEN;
+ return len;
+}
diff --git a/drivers/common/cpt/cpt_pmd_ops_helper.h
b/drivers/common/cpt/cpt_pmd_ops_helper.h
index dd32f9a..24c3559 100644
--- a/drivers/common/cpt/cpt_pmd_ops_helper.h
+++ b/drivers/common/cpt/cpt_pmd_ops_helper.h
@@ -31,4 +31,13 @@ cpt_pmd_ops_helper_get_mlen_direct_mode(void);
*/
int
cpt_pmd_ops_helper_get_mlen_sg_mode(void);
+
+/*
+ * Get size of meta buffer to be allocated for asymmetric crypto operations
+ *
+ * @return
+ * - length
+ */
+int
+cpt_pmd_ops_helper_asym_get_mlen(void);
#endif /* _CPT_PMD_OPS_HELPER_H_ */
diff --git a/drivers/common/cpt/rte_common_cpt_version.map
b/drivers/common/cpt/rte_common_cpt_version.map
index dec614f..382ec4b 100644
--- a/drivers/common/cpt/rte_common_cpt_version.map
+++ b/drivers/common/cpt/rte_common_cpt_version.map
@@ -4,3 +4,11 @@ DPDK_18.11 {
cpt_pmd_ops_helper_get_mlen_direct_mode;
cpt_pmd_ops_helper_get_mlen_sg_mode;
};
+
+DPDK_19.11 {
+ global:
+
+ cpt_pmd_ops_helper_asym_get_mlen;
+
+ local: *;
+};
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index ad64bf4..ce546c2 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -412,24 +412,41 @@ otx_cpt_metabuf_mempool_create(const struct rte_cryptodev
*dev,
int nb_elements)
{
char mempool_name[RTE_MEMPOOL_NAMESIZE];
- int sg_mlen, lb_mlen, max_mlen, ret;
struct cpt_qp_meta_info *meta_info;
struct rte_mempool *pool;
+ int max_mlen = 0;
+ int sg_mlen = 0;
+ int lb_mlen = 0;
+ int ret;
- /* Get meta len for scatter gather mode */
- sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
+ /*
+* Calculate metabuf length required. The 'crypto_octeontx' device
+* would be either SYMMETRIC or ASYMMETRIC.
+*/
- /* Extra 32B saved for future considerations */
- sg_mlen += 4 * sizeof(uint64_t);
+ if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
- /* Get meta len for linear buffer (direct) mode */
- lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+ /* Get meta len for scatter gather mode */
+ sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
- /* Extra 32B saved for future considerations */
- lb_mlen += 4 * sizeof(uint64_t);
+ /* Extra 32B saved for future considerations */
+ sg_mlen += 4 * sizeof(uint64_t);
- /* Check max requirement for meta buffer */
- max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+ /* Get meta len for linear buffer (direct) mode */
+ lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
+
+ /* Extra 32B saved for future considerations */
+ lb_mlen += 4 * sizeof(uint64_t);
+
+ /* Check max requirement for meta buffer */
+ max_mlen = RTE_MAX(lb_mlen, sg_mlen);
+ } else {
+
+ /* Asymmetric device */
+
+ /* Get meta len for asymmetric operations */
+ max_mlen = cpt_pmd_ops_helper_asym_get_mlen();
+ }
/* Allocate mempool */
--
2.7.4
[dpdk-dev] [PATCH v2 4/5] crypto/octeontx: add asymmetric enqueue/dequeue ops
From: Sunila Sahu
Add asymmetric crypto op enqueue & dequeue routines
Signed-off-by: Anoob Joseph
Signed-off-by: Kanaka Durga Kotamarthy
Signed-off-by: Sunila Sahu
---
drivers/common/cpt/cpt_common.h | 1 +
drivers/common/cpt/cpt_mcode_defines.h | 20 ++
drivers/common/cpt/cpt_ucode_asym.h | 282
drivers/crypto/octeontx/otx_cryptodev_ops.c | 236 +--
4 files changed, 522 insertions(+), 17 deletions(-)
diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index 7ef6b29..dff45f0 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -75,6 +75,7 @@ struct cpt_request_info {
uint64_t ei2;
uint64_t ei3;
} ist;
+ uint8_t *rptr;
/** Control path fields */
uint64_t time_out;
diff --git a/drivers/common/cpt/cpt_mcode_defines.h
b/drivers/common/cpt/cpt_mcode_defines.h
index d5b3c59..91d30a5 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -21,6 +21,18 @@
#define CPT_MAJOR_OP_KASUMI0x38
#define CPT_MAJOR_OP_MISC 0x01
+/* AE opcodes */
+#define CPT_MAJOR_OP_MODEX 0x03
+#define CPT_MINOR_OP_MODEX 0x01
+#define CPT_MINOR_OP_PKCS_ENC 0x02
+#define CPT_MINOR_OP_PKCS_ENC_CRT 0x03
+#define CPT_MINOR_OP_PKCS_DEC 0x04
+#define CPT_MINOR_OP_PKCS_DEC_CRT 0x05
+#define CPT_MINOR_OP_MODEX_CRT 0x06
+
+#define CPT_BLOCK_TYPE1 0
+#define CPT_BLOCK_TYPE2 1
+
#define CPT_BYTE_1616
#define CPT_BYTE_2424
#define CPT_BYTE_3232
@@ -367,6 +379,14 @@ typedef struct fc_params {
} fc_params_t;
/*
+ * Parameters for asymmetric operations
+ */
+struct asym_op_params {
+ struct cpt_request_info *req;
+ phys_addr_t meta_buf;
+};
+
+/*
* Parameters for digest
* generate requests
* Only src_iov, op, ctx_buf, mac_buf, prep_req
diff --git a/drivers/common/cpt/cpt_ucode_asym.h
b/drivers/common/cpt/cpt_ucode_asym.h
index e0311f1..00e01b5 100644
--- a/drivers/common/cpt/cpt_ucode_asym.h
+++ b/drivers/common/cpt/cpt_ucode_asym.h
@@ -9,6 +9,8 @@
#include
#include
+#include "cpt_common.h"
+#include "cpt_hw_types.h"
#include "cpt_mcode_defines.h"
static __rte_always_inline void
@@ -168,4 +170,284 @@ cpt_free_asym_session_parameters(struct
cpt_asym_sess_misc *sess)
}
}
+static __rte_always_inline void
+cpt_fill_req_comp_addr(struct cpt_request_info *req, buf_ptr_t addr)
+{
+ void *completion_addr = RTE_PTR_ALIGN(addr.vaddr, 16);
+
+ /* Pointer to cpt_res_s, updated by CPT */
+ req->completion_addr = (volatile uint64_t *)completion_addr;
+ req->comp_baddr = addr.dma_addr +
+ RTE_PTR_DIFF(completion_addr, addr.vaddr);
+ *(req->completion_addr) = COMPLETION_CODE_INIT;
+}
+
+static __rte_always_inline int
+cpt_modex_prep(struct asym_op_params *modex_params,
+ struct rte_crypto_modex_xform *mod)
+{
+ struct cpt_request_info *req = modex_params->req;
+ phys_addr_t mphys = modex_params->meta_buf;
+ uint32_t exp_len = mod->exponent.length;
+ uint32_t mod_len = mod->modulus.length;
+ struct rte_crypto_mod_op_param mod_op;
+ struct rte_crypto_op **op;
+ vq_cmd_word0_t vq_cmd_w0;
+ uint64_t total_key_len;
+ opcode_info_t opcode;
+ uint32_t dlen, rlen;
+ uint32_t base_len;
+ buf_ptr_t caddr;
+ uint8_t *dptr;
+
+ /* Extracting modex op form params->req->op[1]->asym->modex */
+ op = RTE_PTR_ADD(req->op, sizeof(uintptr_t));
+ mod_op = ((struct rte_crypto_op *)*op)->asym->modex;
+
+ base_len = mod_op.base.length;
+ if (unlikely(base_len > mod_len)) {
+ CPT_LOG_DP_ERR("Base length greater than modulus length is not
supported");
+ (*op)->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -ENOTSUP;
+ }
+
+ total_key_len = mod_len + exp_len;
+
+ /* Input buffer */
+ dptr = RTE_PTR_ADD(req, sizeof(struct cpt_request_info));
+ memcpy(dptr, mod->modulus.data, total_key_len);
+ dptr += total_key_len;
+ memcpy(dptr, mod_op.base.data, base_len);
+ dptr += base_len;
+ dlen = total_key_len + base_len;
+
+ /* Result buffer */
+ rlen = mod_len;
+
+ /* Setup opcodes */
+ opcode.s.major = CPT_MAJOR_OP_MODEX;
+ opcode.s.minor = CPT_MINOR_OP_MODEX;
+ vq_cmd_w0.s.opcode = opcode.flags;
+
+ /* GP op header */
+ vq_cmd_w0.s.param1 = mod_len;
+ vq_cmd_w0.s.param2 = exp_len;
+ vq_cmd_w0.s.dlen = dlen;
+
+ /* Filling cpt_request_info structure */
+ req->ist.ei0 = vq_cmd_w0.u64;
+ req->ist.ei1 = mphys;
+ req->ist.ei2 = mphys + dlen;
+
+ /* Result pointer to store result data */
+ req->rptr = dptr;
+
+ /* alternate_caddr to write completion status of the microcode
[dpdk-dev] [PATCH v2 5/5] app/test: register octeontx PMD to asym testsuite
From: Sunila Sahu
Updated asymmetric crypto unit-test application to test
asymmetric crypto operations in octeontx PMD
Signed-off-by: Anoob Joseph
Signed-off-by: Kanaka Durga Kotamarthy
Signed-off-by: Sunila Sahu
---
app/test/test_cryptodev_asym.c | 31 +++
doc/guides/cryptodevs/octeontx.rst | 19 +++
2 files changed, 50 insertions(+)
diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index e8177e7..241c384 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -1791,6 +1791,19 @@ static struct unit_test_suite
cryptodev_qat_asym_testsuite = {
}
};
+static struct unit_test_suite cryptodev_octeontx_asym_testsuite = {
+ .suite_name = "Crypto Device OCTEONTX ASYM Unit Test Suite",
+ .setup = testsuite_setup,
+ .teardown = testsuite_teardown,
+ .unit_test_cases = {
+ TEST_CASE_ST(ut_setup, ut_teardown, test_capability),
+ TEST_CASE_ST(ut_setup, ut_teardown, test_rsa_enc_dec_crt),
+ TEST_CASE_ST(ut_setup, ut_teardown, test_rsa_sign_verify_crt),
+ TEST_CASE_ST(ut_setup, ut_teardown, test_mod_exp),
+ TEST_CASES_END() /**< NULL terminate unit test array */
+ }
+};
+
static int
test_cryptodev_openssl_asym(void)
{
@@ -1823,7 +1836,25 @@ test_cryptodev_qat_asym(void)
return unit_test_suite_runner(&cryptodev_qat_asym_testsuite);
}
+static int
+test_cryptodev_octeontx_asym(void)
+{
+ gbl_driver_id = rte_cryptodev_driver_id_get(
+ RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));
+ if (gbl_driver_id == -1) {
+ RTE_LOG(ERR, USER1, "OCTEONTX PMD must be loaded. Check if "
+ "CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO is "
+ "enabled in config file to run this "
+ "testsuite.\n");
+ return TEST_FAILED;
+ }
+ return unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);
+}
+
REGISTER_TEST_COMMAND(cryptodev_openssl_asym_autotest,
test_cryptodev_openssl_asym);
REGISTER_TEST_COMMAND(cryptodev_qat_asym_autotest, test_cryptodev_qat_asym);
+
+REGISTER_TEST_COMMAND(cryptodev_octeontx_asym_autotest,
+ test_cryptodev_octeontx_asym);
diff --git a/doc/guides/cryptodevs/octeontx.rst
b/doc/guides/cryptodevs/octeontx.rst
index 8f8126b..4fa199e 100644
--- a/doc/guides/cryptodevs/octeontx.rst
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -126,3 +126,22 @@ OCTEON TX crypto PMD.
./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config
"(1,0,0),(0,0,0)" -f ep1.cfg
+
+Testing
+---
+
+The symmetric crypto operations on OCTEON TX crypto PMD may be verified by
running the test
+application:
+
+.. code-block:: console
+
+./test
+RTE>>cryptodev_octeontx_autotest
+
+The asymmetric crypto operations on OCTEON TX crypto PMD may be verified by
running the test
+application:
+
+.. code-block:: console
+
+./test
+RTE>>cryptodev_octeontx_asym_autotest
--
2.7.4
[dpdk-dev] [PATCH v2 2/5] crypto/octeontx: add asymmetric session operations
From: Kanaka Durga Kotamarthy
Add asymmetric session setup and free functions. RSA and modexp
operations are supported.
Signed-off-by: Anoob Joseph
Signed-off-by: Kanaka Durga Kotamarthy
Signed-off-by: Sunila Sahu
---
doc/guides/cryptodevs/features/octeontx.ini| 6 +-
doc/guides/cryptodevs/octeontx.rst | 10 +-
drivers/common/cpt/cpt_mcode_defines.h | 9 ++
drivers/common/cpt/cpt_ucode_asym.h| 171 +
.../crypto/octeontx/otx_cryptodev_capabilities.c | 47 +-
.../crypto/octeontx/otx_cryptodev_capabilities.h | 5 +-
drivers/crypto/octeontx/otx_cryptodev_ops.c| 71 -
7 files changed, 307 insertions(+), 12 deletions(-)
create mode 100644 drivers/common/cpt/cpt_ucode_asym.h
diff --git a/doc/guides/cryptodevs/features/octeontx.ini
b/doc/guides/cryptodevs/features/octeontx.ini
index 1735b8f..1c036c5 100644
--- a/doc/guides/cryptodevs/features/octeontx.ini
+++ b/doc/guides/cryptodevs/features/octeontx.ini
@@ -5,11 +5,13 @@
;
[Features]
Symmetric crypto = Y
+Asymmetric crypto = Y
Sym operation chaining = Y
HW Accelerated = Y
In Place SGL = Y
OOP SGL In LB Out = Y
OOP SGL In SGL Out = Y
+RSA PRIV OP KEY QT = Y
;
; Supported crypto algorithms of 'octeontx' crypto driver.
@@ -64,4 +66,6 @@ AES GCM (256) = Y
;
; Supported Asymmetric algorithms of the 'octeontx' crypto driver.
;
-[Asymmetric]
\ No newline at end of file
+[Asymmetric]
+RSA= Y
+Modular Exponentiation = Y
diff --git a/doc/guides/cryptodevs/octeontx.rst
b/doc/guides/cryptodevs/octeontx.rst
index 1600a56..8f8126b 100644
--- a/doc/guides/cryptodevs/octeontx.rst
+++ b/doc/guides/cryptodevs/octeontx.rst
@@ -10,8 +10,8 @@ cryptographic operations to cryptographic accelerator units on
poll mode driver enqueues the crypto request to this accelerator and dequeues
the response once the operation is completed.
-Supported Algorithms
-
+Supported Symmetric Crypto Algorithms
+-
Cipher Algorithms
~
@@ -53,6 +53,12 @@ AEAD Algorithms
* ``RTE_CRYPTO_AEAD_AES_GCM``
+Supported Asymmetric Crypto Algorithms
+--
+
+* ``RTE_CRYPTO_ASYM_XFORM_RSA``
+* ``RTE_CRYPTO_ASYM_XFORM_MODEX``
+
Config flags
diff --git a/drivers/common/cpt/cpt_mcode_defines.h
b/drivers/common/cpt/cpt_mcode_defines.h
index b7c3feb..d5b3c59 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -6,6 +6,7 @@
#define _CPT_MCODE_DEFINES_H_
#include
+#include
#include
/*
@@ -314,6 +315,14 @@ struct cpt_ctx {
uint8_t auth_key[64];
};
+struct cpt_asym_sess_misc {
+ enum rte_crypto_asym_xform_type xfrm_type;
+ union {
+ struct rte_crypto_rsa_xform rsa_ctx;
+ struct rte_crypto_modex_xform mod_ctx;
+ };
+};
+
/* Buffer pointer */
typedef struct buf_ptr {
void *vaddr;
diff --git a/drivers/common/cpt/cpt_ucode_asym.h
b/drivers/common/cpt/cpt_ucode_asym.h
new file mode 100644
index 000..e0311f1
--- /dev/null
+++ b/drivers/common/cpt/cpt_ucode_asym.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _CPT_UCODE_ASYM_H_
+#define _CPT_UCODE_ASYM_H_
+
+#include
+#include
+#include
+
+#include "cpt_mcode_defines.h"
+
+static __rte_always_inline void
+cpt_modex_param_normalize(uint8_t **data, size_t *len)
+{
+ size_t i;
+
+ /* Strip leading NUL bytes */
+
+ for (i = 0; i < *len; i++) {
+ if ((*data)[i] != 0)
+ break;
+ }
+
+ *data += i;
+ *len -= i;
+}
+
+static __rte_always_inline int
+cpt_fill_modex_params(struct cpt_asym_sess_misc *sess,
+ struct rte_crypto_asym_xform *xform)
+{
+ struct rte_crypto_modex_xform *ctx = &sess->mod_ctx;
+ size_t exp_len = xform->modex.exponent.length;
+ size_t mod_len = xform->modex.modulus.length;
+ uint8_t *exp = xform->modex.exponent.data;
+ uint8_t *mod = xform->modex.modulus.data;
+
+ cpt_modex_param_normalize(&mod, &mod_len);
+ cpt_modex_param_normalize(&exp, &exp_len);
+
+ if (unlikely(exp_len == 0 || mod_len == 0))
+ return -EINVAL;
+
+ if (unlikely(exp_len > mod_len)) {
+ CPT_LOG_DP_ERR("Exponent length greater than modulus length is
not supported");
+ return -ENOTSUP;
+ }
+
+ /* Allocate buffer to hold modexp params */
+ ctx->modulus.data = rte_malloc(NULL, mod_len + exp_len, 0);
+ if (ctx->modulus.data == NULL) {
+ CPT_LOG_DP_ERR("Could not allocate buffer for modex params");
+ return -ENOMEM;
+ }
+
+ /* Set up modexp prime modulus and private exponent */
+
+ memcpy(ctx->modulus.data, mod, mod_len);
+
Re: [dpdk-dev] [PATCH v4 04/14] vhost: add single packet dequeue function
On 10/9/19 3:38 PM, Marvin Liu wrote: > Add vhost single packet dequeue function for packed ring and meanwhile > left space for shadow used ring update function. > > Signed-off-by: Marvin Liu > Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH] doc: replace license text with SPDX tag in ARK nic
Thanks.Do not hesitate to message me directly about needed ACKs. Acked-by: Ed Czeck On Fri, Sep 27, 2019 at 5:06 AM Hemant Agrawal wrote: > Cc: Ed Czeck > Cc: John Miller > > Signed-off-by: Hemant Agrawal > --- > doc/guides/nics/ark.rst | 29 + > 1 file changed, 1 insertion(+), 28 deletions(-) > > diff --git a/doc/guides/nics/ark.rst b/doc/guides/nics/ark.rst > index 6c135eeba..06e8c3374 100644 > --- a/doc/guides/nics/ark.rst > +++ b/doc/guides/nics/ark.rst > @@ -1,34 +1,7 @@ > -.. BSD LICENSE > - > +.. SPDX-License-Identifier: BSD-3-Clause > Copyright (c) 2015-2017 Atomic Rules LLC > All rights reserved. > > -Redistribution and use in source and binary forms, with or without > -modification, are permitted provided that the following conditions > -are met: > - > -* Redistributions of source code must retain the above copyright > -notice, this list of conditions and the following disclaimer. > -* Redistributions in binary form must reproduce the above copyright > -notice, this list of conditions and the following disclaimer in > -the documentation and/or other materials provided with the > -distribution. > -* Neither the name of Atomic Rules LLC nor the names of its > -contributors may be used to endorse or promote products derived > -from this software without specific prior written permission. > - > -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR > -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT > -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > - > ARK Poll Mode Driver > > > -- > 2.17.1 > >
[dpdk-dev] [PATCH v5] eventdev: flag to identify same destined packets enqueue
This patch introduces a `flag` in the Eth TX adapter enqueue API.
Some drivers may support burst functionality only with the packets
having same destination device and queue.
The flag `RTE_EVENT_ETH_TX_ADAPTER_ENQUEUE_SAME_DEST` can be used
to indicate this so the underlying driver, for drivers to utilize
burst functionality appropriately.
Signed-off-by: Nipun Gupta
Acked-by: Jerin Jacob
---
Changes in v5:
- Assign 'txa_enqueue_same_dest' callback in octeontx drivers
Changes in v4:
- Update rel note specifying the API change
- Remove redundant rte_event_tx_adapter_enqueue_same_dest API
Changes in v3:
- remove flag from internal txa_enqueue_same_dest internal API
- ABI version update in makefile, meson and rel_notes
- Few comments update
Changes in v2:
- have separate internal API in tx adapter for sending burst packets to
same eth dev, queue pair on the basis of the passed flag
- fix compilation of examples/eventdev_pipeline/
app/test-eventdev/test_pipeline_common.h | 6 +++---
.../prog_guide/event_ethernet_tx_adapter.rst | 3 ++-
doc/guides/rel_notes/release_19_11.rst| 7 ++-
drivers/event/octeontx/ssovf_evdev.c | 1 +
drivers/event/octeontx2/otx2_evdev.c | 2 ++
.../eventdev_pipeline/pipeline_worker_tx.c| 2 +-
lib/librte_eventdev/Makefile | 2 +-
lib/librte_eventdev/meson.build | 2 +-
.../rte_event_eth_tx_adapter.h| 19 +--
lib/librte_eventdev/rte_eventdev.c| 1 +
lib/librte_eventdev/rte_eventdev.h| 10 ++
11 files changed, 45 insertions(+), 10 deletions(-)
diff --git a/app/test-eventdev/test_pipeline_common.h
b/app/test-eventdev/test_pipeline_common.h
index 0440b9e29..6e73c6ab2 100644
--- a/app/test-eventdev/test_pipeline_common.h
+++ b/app/test-eventdev/test_pipeline_common.h
@@ -106,7 +106,7 @@ pipeline_event_tx(const uint8_t dev, const uint8_t port,
struct rte_event * const ev)
{
rte_event_eth_tx_adapter_txq_set(ev->mbuf, 0);
- while (!rte_event_eth_tx_adapter_enqueue(dev, port, ev, 1))
+ while (!rte_event_eth_tx_adapter_enqueue(dev, port, ev, 1, 0))
rte_pause();
}
@@ -116,10 +116,10 @@ pipeline_event_tx_burst(const uint8_t dev, const uint8_t
port,
{
uint16_t enq;
- enq = rte_event_eth_tx_adapter_enqueue(dev, port, ev, nb_rx);
+ enq = rte_event_eth_tx_adapter_enqueue(dev, port, ev, nb_rx, 0);
while (enq < nb_rx) {
enq += rte_event_eth_tx_adapter_enqueue(dev, port,
- ev + enq, nb_rx - enq);
+ ev + enq, nb_rx - enq, 0);
}
}
diff --git a/doc/guides/prog_guide/event_ethernet_tx_adapter.rst
b/doc/guides/prog_guide/event_ethernet_tx_adapter.rst
index 192f9e1cf..a8c13e136 100644
--- a/doc/guides/prog_guide/event_ethernet_tx_adapter.rst
+++ b/doc/guides/prog_guide/event_ethernet_tx_adapter.rst
@@ -137,11 +137,12 @@ should use the ``rte_event_enqueue_burst()`` function.
if (cap & RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT) {
event.mbuf = m;
+ eq_flags = 0;
m->port = tx_port;
rte_event_eth_tx_adapter_txq_set(m, tx_queue_id);
- rte_event_eth_tx_adapter_enqueue(dev_id, ev_port, &event, 1);
+ rte_event_eth_tx_adapter_enqueue(dev_id, ev_port, &event, 1,
eq_flags);
} else {
event.queue_id = qid; /* event queue linked to adapter port */
diff --git a/doc/guides/rel_notes/release_19_11.rst
b/doc/guides/rel_notes/release_19_11.rst
index 27cfbd9e3..051ab26b8 100644
--- a/doc/guides/rel_notes/release_19_11.rst
+++ b/doc/guides/rel_notes/release_19_11.rst
@@ -94,6 +94,11 @@ API Changes
Also, make sure to start the actual text at the margin.
=
+* event: The function ``rte_event_eth_tx_adapter_enqueue`` takes an additional
+ input as ``flags``. Flag ``RTE_EVENT_ETH_TX_ADAPTER_ENQUEUE_SAME_DEST`` which
+ has been introduced in this release is used when used when all the packets
+ enqueued in the tx adapter are destined for the same Ethernet port & Tx
queue.
+
ABI Changes
---
@@ -146,7 +151,7 @@ The libraries prepended with a plus sign were incremented
in this version.
librte_eal.so.11
librte_efd.so.1
librte_ethdev.so.12
- librte_eventdev.so.7
+ librte_eventdev.so.8
librte_flow_classify.so.1
librte_gro.so.1
librte_gso.so.1
diff --git a/drivers/event/octeontx/ssovf_evdev.c
b/drivers/event/octeontx/ssovf_evdev.c
index a273d4c96..e4e7c44ed 100644
--- a/drivers/event/octeontx/ssovf_evdev.c
+++ b/drivers/event/octeontx/ssovf_evdev.c
@@ -147,6 +147,7 @@ ssovf_fastpath_fns_set(struct rte_eventdev *dev)
dev->dequeue = ssows_deq;
dev->dequeue_burst = ssows_deq_burst;
dev->txa_enqueue = sso_event_tx_adapter_enqueu
Re: [dpdk-dev] [RFC PATCH 1/9] security: introduce CPU Crypto action type and API
Hi Konstantin, > > Hi Akhil, > ..[snip] > > > > > > OK let us assume that you have a separate structure. But I have a > > > > > > few > > > queries: > > > > > > 1. how can multiple drivers use a same session > > > > > > > > > > As a short answer: they can't. > > > > > It is pretty much the same approach as with rte_security - each device > needs > > > to > > > > > create/init its own session. > > > > > So upper layer would need to maintain its own array (or so) for such > > > > > case. > > > > > Though the question is why would you like to have same session over > > > multiple > > > > > SW backed devices? > > > > > As it would be anyway just a synchronous function call that will be > executed > > > on > > > > > the same cpu. > > > > > > > > I may have single FAT tunnel which may be distributed over multiple > > > > Cores, and each core is affined to a different SW device. > > > > > > If it is pure SW, then we don't need multiple devices for such scenario. > > > Device in that case is pure abstraction that we can skip. > > > > Yes agreed, but that liberty is given to the application whether it need > > multiple > > devices with single queue or a single device with multiple queues. > > I think that independence should not be broken in this new API. > > > > > > > So a single session may be accessed by multiple devices. > > > > > > > > One more example would be depending on packet sizes, I may switch > between > > > > HW/SW PMDs with the same session. > > > > > > Sure, but then we'll have multiple sessions. > > > > No, the session will be same and it will have multiple private data for > > each of > the PMD. > > > > > BTW, we have same thing now - these private session pointers are just > stored > > > inside the same rte_crypto_sym_session. > > > And if user wants to support this model, he would also need to store > > > > > queue_id> > > > pair for each HW device anyway. > > > > Yes agreed, but how is that thing happening in your new struct, you cannot > support that. > > User can store all these info in his own struct. > That's exactly what we have right now. > Let say ipsec-secgw has to store for each IPsec SA: > pointer to crypto-session and/or pointer to security session > plus (for lookaside-devices) cdev_id_qp that allows it to extract > dev_id + queue_id information. > As I understand that works for now, as each ipsec_sa uses only one > dev+queue. Though if someone would like to use multiple devices/queues > for the same SA - he would need to have an array of these pairs. > So even right now rte_cryptodev_sym_session is not self-consistent and > requires extra information to be maintained by user. Why are you increasing the complexity for the user application. The new APIs and struct should be such that it need to do minimum changes in the stack so that stack is portable on multiple vendors. You should try to hide as much complexity in the driver or lib to give the user simple APIs. Having a same session for multiple devices was added by Intel only for some use cases. And we had split that session create API into 2. Now if those are not useful shall we move back to the single API. I think @Doherty, Declan and @De Lara Guarch, Pablo can comment on this. > > > > > > > > > > > > > > > > > > > > > 2. Can somebody use the scheduler pmd for scheduling the different > type > > > of > > > > > payloads for the same session? > > > > > > > > > > In theory yes. > > > > > Though for that scheduler pmd should have inside it's > > > > > rte_crypto_cpu_sym_session an array of pointers to > > > > > the underlying devices sessions. > > > > > > > > > > > > > > > > > With your proposal the APIs would be very specific to your use case > only. > > > > > > > > > > Yes in some way. > > > > > I consider that API specific for SW backed crypto PMDs. > > > > > I can hardly see how any 'real HW' PMDs (lksd-none, lksd-proto) will > benefit > > > > > from it. > > > > > Current crypto-op API is very much HW oriented. > > > > > Which is ok, that's for it was intended for, but I think we also need > > > > > one > that > > > > > would be designed > > > > > for SW backed implementation in mind. > > > > > > > > We may re-use your API for HW PMDs as well which do not have > requirement > > > of > > > > Crypto-op/mbuf etc. > > > > The return type of your new process API may have a status which say > > > 'processed' > > > > Or can be say 'enqueued'. So if it is 'enqueued', we may have a new > > > > API for > > > raw > > > > Bufs dequeue as well. > > > > > > > > This requirement can be for any hardware PMDs like QAT as well. > > > > > > I don't think it is a good idea to extend this API for async (lookaside) > > > devices. > > > You'll need to: > > > - provide dev_id and queue_id for each process(enqueue) and dequeuer > > > operation. > > > - provide IOVA for all buffers passing to that function (data buffers, > > > digest, > IV, > > > aad). > > > - On dequeue provide some way to associate dequed data and digest bu
Re: [dpdk-dev] [PATCH v2 1/2] examples/ipsec-secgw: fix SAD selection logic
Hi Akhil,
> > Ipsec-secgw example application fails to initialize when using default
> > configuration file (ep0.cfg) in library mode (librte_ipsec enabled).
> >
> > The reason is that two of SP rules in ep0.cfg, one for IPv4 and one
> > for IPv6, are using the same SPI number. When SA rules are initialized,
> > their SPI number is checked against SPIs stored in SPD. For library
> > mode, it is not allowed for the same SA to handle both IPv4 and IPv6.
> >
> > Solution is to split SAD into two separate parts - one for IPv4 and one
> > for IPv6. Usage of SAs stays the same. Only change is to pass correct
> > SAD (IPv4 or IPv6) in places where previously combined database was
> > passed.
>
> Can we have 2 different SAs with same SPI value and with different IPv4
> addresses?
>
> Will the IPSec library be able to handle this case. With Setkey it is
> possible in linux.
> Now that we have IPSEC library we should be compatible with what linux can do.
For sure, SADB implementation has to be inside librte_ipsec.
In fact Vladimir submitted patches for that:
http://patches.dpdk.org/cover/60910/
I think we already looked at them.
We also plan to integrate it into ipsec-secgw, it would be a separate patch.
We aim for 19.11 right now but might slip to 20.02.
This patch is not about improve/change ipsec-secgw SAD implementation,
see description below.
>
> So splitting the SADB with IPv4 and IPv6 will just avoid the issue for IPv4
> and IPv6 but the
> Issue will still be there.
> I believe this should be fixed in library rather than application maintaining
> Two different databases. Library's intent is to reduce the application
> overhead for maintaining
> IPSec specific stuff.
Probably we didn't put enough effort to describe the patch goals and methods.
Let me try again:
Right now there is an inconsistency in ipsec-secgw behavior.
In some cases it allows two different IPv4 and IPv6 SP rules to refer to the
same SPI (SA),
in other it doesn't.
So for same config-file ipsec-secgw can either fail or not depending on
- legacy/library mode
- selected security action type
As an example with config file:
sp ipv4 in esp protect 11 pri 2 src 192.168.0.0/16 dst 192.168.0.0/16 sport
0:65535 dport 0:65535
sp ipv6 in esp protect 11 pri 2 src fd12:3456:789a:0031::::0092/64
dst fd12:3456:789a:0031::::0014/64 sport 0:65535 dport 0:65535
sa out 11 cipher_algo null auth_algo null mode transport
sa in 11 aead_algo aes-128-gcm \
aead_key de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef \
mode transport port_id 0 type inline-crypto-offload
library mode would fail to start, legacy mode would start but wouldn't be able
to work correctly.
That is the issue that Lukasz reported:
https://bugs.dpdk.org/show_bug.cgi?id=239
The reason for that: in some cases we do need to know SA IP type (and SIP/DIP
values) at SA creation time.
The way ipsec-secgw obtains that information - search for given SPI value
across SPDs (IPv4 and IPv6).
So when it finds entries in both IPv4 and IPv6 it is not clear which one to use
and exits with an error.
To avoid such situation that patch does the following:
- search for given SPI value across both SPDs (IPv4 and IPv6)
- for each positive result create a new SA.
So if we have same SPI in both IPv4 and IPv6 SPDs instead of one SA that
would be referred by both SPD tables (current situation),
we will create 2 independent SAs - one for IPv4, second for IPv6.
For each one a separate rte_security/crypto session will be created and
programmed.
As side effect of that - we have to split ipsec-secgw SADB into two,
as right now it is just a raw array indexed by (SPI%N) value.
>
> >
> > Split of SA entries is done at initialization stage. Most of given SA
> > entries are checked against SPD. If matching entry is in IPv4 SPD, SA
> > rule is added to IPv4 SAD (respectively for IPv6). Different splitting
> > method is used only when SA entry is for tunnel in inbound direction.
> > In that case if IPv4 tunnel should be used, SA entry is added to IPv4
> > SAD (respectively for IPv6). Reasoning is that inner IP version can
> > be different than outer IP version for tunneled traffic.
> >
> > Bugzilla ID: 239
> > Fixes: 5a032a71c6d3 ("examples/ipsec-secgw: make app to use IPsec library")
> >
> > Reported-by: Lukasz Bartosik
> > Signed-off-by: Mariusz Drost
> > ---
> > examples/ipsec-secgw/ipsec-secgw.c | 48 ++--
> > examples/ipsec-secgw/ipsec.c | 5 +-
> > examples/ipsec-secgw/ipsec.h | 21 +-
> > examples/ipsec-secgw/sa.c | 396 -
> > 4 files changed, 312 insertions(+), 158 deletions(-)
> >
Re: [dpdk-dev] [PATCH 2/3] drivers: use RTE_DIM instead of ARRAY_SIZE
On 10/11/2019 10:32 AM, Ananyev, Konstantin wrote: > > >> Hi Pavan, >> >>> >>> From: Pavan Nikhilesh >>> >>> Use RTE_DIM instead of re-defining ARRAY_SIZE. >>> >>> Signed-off-by: Pavan Nikhilesh >>> --- >>> drivers/bus/dpaa/base/qbman/qman.c| 6 ++-- >>> drivers/bus/dpaa/include/compat.h | 5 >>> drivers/crypto/dpaa2_sec/hw/compat.h | 8 - >>> drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h| 6 ++-- >>> drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h | 2 +- >>> drivers/net/atlantic/atl_hw_regs.h| 1 - >>> drivers/net/atlantic/hw_atl/hw_atl_utils.c| 4 +-- >>> .../net/atlantic/hw_atl/hw_atl_utils_fw2x.c | 2 +- >>> drivers/net/axgbe/axgbe_common.h | 3 -- >>> drivers/net/axgbe/axgbe_dev.c | 2 +- >>> drivers/net/bnx2x/bnx2x.c | 6 ++-- >>> drivers/net/bnx2x/bnx2x.h | 6 >>> drivers/net/bnx2x/ecore_init.h| 8 ++--- >>> drivers/net/bnx2x/ecore_sp.c | 2 +- >>> drivers/net/bnx2x/elink.c | 14 - >>> drivers/net/bnx2x/elink.h | 1 - >>> drivers/net/cxgbe/base/t4_hw.c| 16 +- >>> drivers/net/cxgbe/base/t4vf_hw.c | 4 +-- >>> drivers/net/cxgbe/cxgbe_compat.h | 2 -- >>> drivers/net/cxgbe/cxgbe_flow.c| 4 +-- >>> drivers/net/cxgbe/cxgbe_main.c| 10 +++ >>> drivers/net/cxgbe/sge.c | 2 +- >>> drivers/net/ena/ena_ethdev.c | 8 ++--- >>> drivers/net/enic/base/vnic_dev.c | 4 +-- >>> drivers/net/enic/base/vnic_devcmd.h | 2 -- >>> drivers/net/hns3/hns3_cmd.c | 2 +- >>> drivers/net/hns3/hns3_ethdev.h| 2 -- >>> drivers/net/hns3/hns3_flow.c | 18 +-- >>> drivers/net/i40e/base/i40e_diag.c | 2 +- >>> drivers/net/i40e/base/i40e_osdep.h| 2 -- >>> drivers/net/iavf/base/iavf_osdep.h| 2 -- >>> drivers/net/ice/base/ice_fdir.c | 2 +- >>> drivers/net/ice/base/ice_flex_pipe.c | 2 +- >>> drivers/net/ice/base/ice_flow.c | 2 +- >>> drivers/net/ice/base/ice_osdep.h | 1 - >>> drivers/net/ice/base/ice_switch.c | 2 +- >>> .../net/nfp/nfpcore/nfp-common/nfp_platform.h | 4 --- >>> drivers/net/nfp/nfpcore/nfp_cppcore.c | 2 +- >>> drivers/net/nfp/nfpcore/nfp_nsp.c | 2 +- >>> drivers/net/nfp/nfpcore/nfp_nsp_eth.c | 4 +-- >>> drivers/net/sfc/base/ef10_ev.c| 4 +-- >>> drivers/net/sfc/base/ef10_filter.c| 12 >>> drivers/net/sfc/base/ef10_mac.c | 18 +-- >>> drivers/net/sfc/base/ef10_nic.c | 4 +-- >>> drivers/net/sfc/base/ef10_nvram.c | 6 ++-- >>> drivers/net/sfc/base/efx.h| 3 -- >>> drivers/net/sfc/base/efx_port.c | 2 +- >>> drivers/net/sfc/base/efx_rx.c | 2 +- >>> drivers/net/sfc/base/siena_mac.c | 2 +- >>> drivers/net/sfc/base/siena_nic.c | 20 ++--- >>> drivers/net/sfc/base/siena_nvram.c| 6 ++-- >>> drivers/net/thunderx/base/nicvf_hw.c | 30 +-- >>> drivers/net/thunderx/base/nicvf_hw.h | 2 -- >>> .../raw/ifpga/base/osdep_rte/osdep_generic.h | 2 -- >>> 54 files changed, 120 insertions(+), 170 deletions(-) >>> >>> diff --git a/drivers/bus/dpaa/base/qbman/qman.c >>> b/drivers/bus/dpaa/base/qbman/qman.c >>> index e43fc65ef..019be95e2 100644 >>> --- a/drivers/bus/dpaa/base/qbman/qman.c >>> +++ b/drivers/bus/dpaa/base/qbman/qman.c >>> @@ -1956,7 +1956,7 @@ int qman_query_wq(u8 query_dedicated, struct >>> qm_mcr_querywq *wq) >>> int i, array_len; >>> >>> wq->channel.id = be16_to_cpu(mcr->querywq.channel.id); >>> - array_len = ARRAY_SIZE(mcr->querywq.wq_len); >>> + array_len = RTE_DIM(mcr->querywq.wq_len); >> >> [Hemant] some of these files are common Flibs and they are shared with >> other projects (Linux/uboot) etc. It will be more appropriate to >> map the ARRAY_SIZE to RTE_DIM in compat.h instead of changing this code >> inline. >> This way we need not to maintain diff from the common HW lib codes. > > +1 to this suggestion > What about dropping the drivers patch form this patchset but continue with others?
Re: [dpdk-dev] [PATCH v2 1/2] examples/ipsec-secgw: fix SAD selection logic
Hi Konstantin, > > Hi Akhil, > > > > Ipsec-secgw example application fails to initialize when using default > > > configuration file (ep0.cfg) in library mode (librte_ipsec enabled). > > > > > > The reason is that two of SP rules in ep0.cfg, one for IPv4 and one > > > for IPv6, are using the same SPI number. When SA rules are initialized, > > > their SPI number is checked against SPIs stored in SPD. For library > > > mode, it is not allowed for the same SA to handle both IPv4 and IPv6. > > > > > > Solution is to split SAD into two separate parts - one for IPv4 and one > > > for IPv6. Usage of SAs stays the same. Only change is to pass correct > > > SAD (IPv4 or IPv6) in places where previously combined database was > > > passed. > > > > Can we have 2 different SAs with same SPI value and with different IPv4 > addresses? > > > > Will the IPSec library be able to handle this case. With Setkey it is > > possible in > linux. > > Now that we have IPSEC library we should be compatible with what linux can > do. > > For sure, SADB implementation has to be inside librte_ipsec. > In fact Vladimir submitted patches for that: > http://patches.dpdk.org/cover/60910/ > I think we already looked at them. > We also plan to integrate it into ipsec-secgw, it would be a separate patch. > We aim for 19.11 right now but might slip to 20.02. > > This patch is not about improve/change ipsec-secgw SAD implementation, > see description below. > > > > > So splitting the SADB with IPv4 and IPv6 will just avoid the issue for IPv4 > > and > IPv6 but the > > Issue will still be there. > > I believe this should be fixed in library rather than application > > maintaining > > Two different databases. Library's intent is to reduce the application > > overhead > for maintaining > > IPSec specific stuff. > > Probably we didn't put enough effort to describe the patch goals and methods. > Let me try again: > Right now there is an inconsistency in ipsec-secgw behavior. > In some cases it allows two different IPv4 and IPv6 SP rules to refer to the > same > SPI (SA), > in other it doesn't. > So for same config-file ipsec-secgw can either fail or not depending on > - legacy/library mode > - selected security action type > > As an example with config file: > > sp ipv4 in esp protect 11 pri 2 src 192.168.0.0/16 dst 192.168.0.0/16 sport > 0:65535 dport 0:65535 > sp ipv6 in esp protect 11 pri 2 src fd12:3456:789a:0031::::0092/64 > dst fd12:3456:789a:0031::::0014/64 sport 0:65535 dport 0:65535 > sa out 11 cipher_algo null auth_algo null mode transport > sa in 11 aead_algo aes-128-gcm \ > aead_key de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef \ > mode transport port_id 0 type inline-crypto-offload > > library mode would fail to start, legacy mode would start but wouldn't be > able to > work correctly. > > That is the issue that Lukasz reported: > https://bugs.dpdk.org/show_bug.cgi?id=239 > > The reason for that: in some cases we do need to know SA IP type (and SIP/DIP > values) at SA creation time. > The way ipsec-secgw obtains that information - search for given SPI value > across > SPDs (IPv4 and IPv6). > So when it finds entries in both IPv4 and IPv6 it is not clear which one to > use and > exits with an error. > To avoid such situation that patch does the following: > - search for given SPI value across both SPDs (IPv4 and IPv6) > - for each positive result create a new SA. > So if we have same SPI in both IPv4 and IPv6 SPDs instead of one SA that > would be referred by both SPD tables (current situation), > we will create 2 independent SAs - one for IPv4, second for IPv6. > For each one a separate rte_security/crypto session will be created and > programmed. > > As side effect of that - we have to split ipsec-secgw SADB into two, > as right now it is just a raw array indexed by (SPI%N) value. I got the intent of this patch in first place. I agree that there is a bug in the current application, but this patch is not fixing it. Rather it is just avoiding it. I have seen the patch for the SAD support in IPSEC. That is the correct solution and we should pursue that. When you have that logic in place You would be replacing this code entirely. You have time till RC2. Application patches are acceptable till RC2 which is close to 3 weeks from now. Regards, Akhil
[dpdk-dev] [PATCH 1/2] event/dpaa: fix number of supported atomic flows
The number of atomic flows supported was not returned correctly for
DPAA driver. This patch fixes the same.
Fixes: b08dc6430abd ("event/dpaa: add queue config get/set")
Cc: sta...@dpdk.org
Signed-off-by: Nipun Gupta
---
drivers/event/dpaa/dpaa_eventdev.c | 1 +
drivers/event/dpaa/dpaa_eventdev.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/event/dpaa/dpaa_eventdev.c
b/drivers/event/dpaa/dpaa_eventdev.c
index d02b8694e..570983251 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -471,6 +471,7 @@ dpaa_event_queue_def_conf(struct rte_eventdev *dev, uint8_t
queue_id,
RTE_SET_USED(queue_id);
memset(queue_conf, 0, sizeof(struct rte_event_queue_conf));
+ queue_conf->nb_atomic_flows = DPAA_EVENT_QUEUE_ATOMIC_FLOWS;
queue_conf->schedule_type = RTE_SCHED_TYPE_PARALLEL;
queue_conf->priority = RTE_EVENT_DEV_PRIORITY_HIGHEST;
}
diff --git a/drivers/event/dpaa/dpaa_eventdev.h
b/drivers/event/dpaa/dpaa_eventdev.h
index b8f247c61..5ce15a3db 100644
--- a/drivers/event/dpaa/dpaa_eventdev.h
+++ b/drivers/event/dpaa/dpaa_eventdev.h
@@ -32,7 +32,7 @@ do { \
RTE_EVENT_DEV_CAP_BURST_MODE; \
} while (0)
-#define DPAA_EVENT_QUEUE_ATOMIC_FLOWS 0
+#define DPAA_EVENT_QUEUE_ATOMIC_FLOWS 2048
#define DPAA_EVENT_QUEUE_ORDER_SEQUENCES 2048
#define RTE_EVENT_ETH_RX_ADAPTER_DPAA_CAP \
--
2.17.1
[dpdk-dev] [PATCH 2/2] event/dpaa: support Tx adapter
This patch adds the support of Tx adapter for DPAA1 platform
Signed-off-by: Nipun Gupta
---
drivers/event/dpaa/dpaa_eventdev.c | 75 --
1 file changed, 70 insertions(+), 5 deletions(-)
diff --git a/drivers/event/dpaa/dpaa_eventdev.c
b/drivers/event/dpaa/dpaa_eventdev.c
index 570983251..b8761c6a9 100644
--- a/drivers/event/dpaa/dpaa_eventdev.c
+++ b/drivers/event/dpaa/dpaa_eventdev.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -864,6 +865,66 @@ dpaa_eventdev_crypto_stop(const struct rte_eventdev *dev,
return 0;
}
+static int
+dpaa_eventdev_tx_adapter_create(uint8_t id,
+const struct rte_eventdev *dev)
+{
+ RTE_SET_USED(id);
+ RTE_SET_USED(dev);
+
+ /* Nothing to do. Simply return. */
+ return 0;
+}
+
+static int
+dpaa_eventdev_tx_adapter_caps(const struct rte_eventdev *dev,
+ const struct rte_eth_dev *eth_dev,
+ uint32_t *caps)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(eth_dev);
+
+ *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;
+ return 0;
+}
+
+static uint16_t
+dpaa_eventdev_txa_enqueue_same_dest(void *port,
+struct rte_event ev[],
+uint16_t nb_events)
+{
+ struct rte_mbuf *m[DPAA_EVENT_MAX_PORT_ENQUEUE_DEPTH], *m0;
+ uint8_t qid, i;
+
+ RTE_SET_USED(port);
+
+ m0 = (struct rte_mbuf *)ev[0].mbuf;
+ qid = rte_event_eth_tx_adapter_txq_get(m0);
+
+ for (i = 0; i < nb_events; i++)
+ m[i] = (struct rte_mbuf *)ev[i].mbuf;
+
+ return rte_eth_tx_burst(m0->port, qid, m, nb_events);
+}
+
+static uint16_t
+dpaa_eventdev_txa_enqueue(void *port,
+ struct rte_event ev[],
+ uint16_t nb_events)
+{
+ struct rte_mbuf *m = (struct rte_mbuf *)ev[0].mbuf;
+ uint8_t qid, i;
+
+ RTE_SET_USED(port);
+
+ for (i = 0; i < nb_events; i++) {
+ qid = rte_event_eth_tx_adapter_txq_get(m);
+ rte_eth_tx_burst(m->port, qid, &m, 1);
+ }
+
+ return nb_events;
+}
+
static struct rte_eventdev_ops dpaa_eventdev_ops = {
.dev_infos_get= dpaa_event_dev_info_get,
.dev_configure= dpaa_event_dev_configure,
@@ -879,11 +940,13 @@ static struct rte_eventdev_ops dpaa_eventdev_ops = {
.port_link= dpaa_event_port_link,
.port_unlink = dpaa_event_port_unlink,
.timeout_ticks= dpaa_event_dequeue_timeout_ticks,
- .eth_rx_adapter_caps_get = dpaa_event_eth_rx_adapter_caps_get,
- .eth_rx_adapter_queue_add = dpaa_event_eth_rx_adapter_queue_add,
- .eth_rx_adapter_queue_del = dpaa_event_eth_rx_adapter_queue_del,
- .eth_rx_adapter_start = dpaa_event_eth_rx_adapter_start,
- .eth_rx_adapter_stop = dpaa_event_eth_rx_adapter_stop,
+ .eth_rx_adapter_caps_get= dpaa_event_eth_rx_adapter_caps_get,
+ .eth_rx_adapter_queue_add = dpaa_event_eth_rx_adapter_queue_add,
+ .eth_rx_adapter_queue_del = dpaa_event_eth_rx_adapter_queue_del,
+ .eth_rx_adapter_start = dpaa_event_eth_rx_adapter_start,
+ .eth_rx_adapter_stop= dpaa_event_eth_rx_adapter_stop,
+ .eth_tx_adapter_caps_get= dpaa_eventdev_tx_adapter_caps,
+ .eth_tx_adapter_create = dpaa_eventdev_tx_adapter_create,
.crypto_adapter_caps_get= dpaa_eventdev_crypto_caps_get,
.crypto_adapter_queue_pair_add = dpaa_eventdev_crypto_queue_add,
.crypto_adapter_queue_pair_del = dpaa_eventdev_crypto_queue_del,
@@ -956,6 +1019,8 @@ dpaa_event_dev_create(const char *name, const char *params)
eventdev->dequeue = dpaa_event_dequeue_intr;
eventdev->dequeue_burst = dpaa_event_dequeue_burst_intr;
}
+ eventdev->txa_enqueue = dpaa_eventdev_txa_enqueue;
+ eventdev->txa_enqueue_same_dest = dpaa_eventdev_txa_enqueue_same_dest;
RTE_LOG(INFO, PMD, "%s eventdev added", name);
--
2.17.1
Re: [dpdk-dev] [PATCH v5 10/10] doc: add application usage guide for l2fwd-event
On Thu, Oct 3, 2019 at 2:29 AM wrote: > > From: Sunil Kumar Kori > > Add documentation for l2fwd-event example. > Update release notes. > > Signed-off-by: Sunil Kumar Kori # Please fix the typos through with the following command aspell --lang=en_US --check doc/guides/sample_app_ug/l2_forward_event.rst # Remove the following warning. $ make doc-guides-html doc/guides/sample_app_ug/l2_forward_real_virtual.rst:39: WARNING: duplicate label figure_l2_fwd_benchmark_setup, > --- > MAINTAINERS | 1 + > doc/guides/rel_notes/release_19_11.rst| 6 + > doc/guides/sample_app_ug/index.rst| 1 + > doc/guides/sample_app_ug/intro.rst| 5 + > doc/guides/sample_app_ug/l2_forward_event.rst | 755 ++ > 5 files changed, 768 insertions(+) > create mode 100644 doc/guides/sample_app_ug/l2_forward_event.rst > > diff --git a/MAINTAINERS b/MAINTAINERS > index 292ac10c3..94a49b812 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1461,6 +1461,7 @@ F: examples/l2fwd-cat/ > M: Sunil Kumar Kori > M: Pavan Nikhilesh > F: examples/l2fwd-event/ > +F: doc/guides/sample_app_ug/l2_forward_event.rst > T: git://dpdk.org/next/dpdk-next-eventdev > > F: examples/l3fwd/ > diff --git a/doc/guides/rel_notes/release_19_11.rst > b/doc/guides/rel_notes/release_19_11.rst > index 27cfbd9e3..071593e4d 100644 > --- a/doc/guides/rel_notes/release_19_11.rst > +++ b/doc/guides/rel_notes/release_19_11.rst > @@ -56,6 +56,12 @@ New Features > Also, make sure to start the actual text at the margin. > = > > +* **Added new example l2fwd-event** Added new example l2fwd-event application > + > + Added an example application `l2fwd-event` that adds event device support > to > + traditional l2fwd example. The default poll mode is also preserved for > + readability. Please change the last sentence to the following or something similar "It demonstrates usage of poll and event mode IO mechanism under a single application" > + > > Removed Items > - > diff --git a/doc/guides/sample_app_ug/index.rst > b/doc/guides/sample_app_ug/index.rst > index f23f8f59e..41388231a 100644 > --- a/doc/guides/sample_app_ug/index.rst > +++ b/doc/guides/sample_app_ug/index.rst > @@ -26,6 +26,7 @@ Sample Applications User Guides > l2_forward_crypto > l2_forward_job_stats > l2_forward_real_virtual > +l2_forward_event > l2_forward_cat > l3_forward > l3_forward_power_man > diff --git a/doc/guides/sample_app_ug/intro.rst > b/doc/guides/sample_app_ug/intro.rst > index 90704194a..84591c0a1 100644 > --- a/doc/guides/sample_app_ug/intro.rst > +++ b/doc/guides/sample_app_ug/intro.rst > @@ -87,6 +87,11 @@ examples are highlighted below. >forwarding, or ``l2fwd`` application does forwarding based on Ethernet MAC >addresses like a simple switch. > > +* :doc:`Network Layer 2 forwarding`: The Network Layer 2 > + forwarding, or ``l2fwd-event`` application does forwarding based on > Ethernet MAC > + addresses like a simple switch. It demonstrate usage of poll and event > mode Rx/Tx > + mechanism. Please change the last sentence to the following or something similar "It demonstrates usage of poll and event mode IO mechanism under a single application" > + > * :doc:`Network Layer 3 forwarding`: The Network Layer3 >forwarding, or ``l3fwd`` application does forwarding based on Internet >Protocol, IPv4 or IPv6 like a simple router. > diff --git a/doc/guides/sample_app_ug/l2_forward_event.rst > b/doc/guides/sample_app_ug/l2_forward_event.rst > new file mode 100644 > index 0..250d16887 > --- /dev/null > +++ b/doc/guides/sample_app_ug/l2_forward_event.rst > @@ -0,0 +1,755 @@ > +.. SPDX-License-Identifier: BSD-3-Clause > +Copyright(c) 2010-2014 Intel Corporation. > + > +.. _l2_fwd_event_app: > + > +L2 Forwarding Eventdev Sample Application > += > + > +The L2 Forwarding eventdev sample application is a simple example of packet > +processing using the Data Plane Development Kit (DPDK) to demonstrate usage > of > +poll and event mode packet I/O mechanism. > + > +Overview > + > + > +The L2 Forwarding eventdev sample application, performs L2 forwarding for > each > +packet that is received on an RX_PORT. The destination port is the adjacent > port > +from the enabled portmask, that is, if the first four ports are enabled > (portmask=0x0f), > +ports 1 and 2 forward into each other, and ports 3 and 4 forward into each > other. > +Also, if MAC addresses updating is enabled, the MAC addresses are affected > as follows: > + > +* The source MAC address is replaced by the TX_PORT MAC address > + > +* The destination MAC address is replaced by 02:00:00:00:00:TX_PORT_ID > + > +Appliation receives packets from RX_PORT using below mentioned methods: > + > +* Poll mode > + > +* Eventdev mode (defau
Re: [dpdk-dev] [PATCH v4 13/14] vhost: check whether disable software pre-fetch
On 10/9/19 3:38 PM, Marvin Liu wrote:
> Disable software pre-fetch actions on Skylake and later platforms.
> Hardware can fetch needed data for vhost, additional software pre-fetch
> will impact performance.
>
> Signed-off-by: Marvin Liu
>
> diff --git a/lib/librte_vhost/Makefile b/lib/librte_vhost/Makefile
> index 30839a001..5f3b42e56 100644
> --- a/lib/librte_vhost/Makefile
> +++ b/lib/librte_vhost/Makefile
> @@ -16,6 +16,12 @@ CFLAGS += -I vhost_user
> CFLAGS += -fno-strict-aliasing
> LDLIBS += -lpthread
>
> +AVX512_SUPPORT=$(shell $(CC) -march=native -dM -E - +
> +ifneq ($(AVX512_SUPPORT),)
> +CFLAGS += -DDISABLE_SWPREFETCH
> +endif
That's problematic I think, because the machine running the lib may be
different from the machine building it, for example distros.
In this case, a Skylake or later may be used to build the package, but
with passing "-march=haswell". It would end-up prefetching being
disabled whereas we would expect it to be enabled.
I see several solutions:
- Check for CONFIG_RTE_ENABLE_AVX512 flag.
- Keep prefetch instructions (what would be the impact on Skylake and
later?)
- Remove prefetch instructions (what would be the impact on pre-
Skylake?)
But really, I think we need some figures before applying such a patch.
What performance gain do you measure with this patch?
> ifeq ($(RTE_TOOLCHAIN), gcc)
> ifeq ($(shell test $(GCC_VERSION) -ge 83 && echo 1), 1)
> CFLAGS += -DSUPPORT_GCC_UNROLL_PRAGMA
> diff --git a/lib/librte_vhost/meson.build b/lib/librte_vhost/meson.build
> index ddf0ee579..5c6f0c0b4 100644
> --- a/lib/librte_vhost/meson.build
> +++ b/lib/librte_vhost/meson.build
> @@ -15,6 +15,10 @@ elif (toolchain == 'clang' and
> cc.version().version_compare('>=3.7.0'))
> elif (toolchain == 'icc' and cc.version().version_compare('>=16.0.0'))
> cflags += '-DSUPPORT_ICC_UNROLL_PRAGMA'
> endif
> +r = run_command(toolchain, '-march=native', '-dM', '-E', '-', ' '|', 'grep AVX512F')
> +if (r.stdout().strip() != '')
> + cflags += '-DDISABLE_SWPREFETCH'
> +endif
> dpdk_conf.set('RTE_LIBRTE_VHOST_POSTCOPY',
> cc.has_header('linux/userfaultfd.h'))
> version = 4
> diff --git a/lib/librte_vhost/virtio_net.c b/lib/librte_vhost/virtio_net.c
> index 56c2080fb..046e497c2 100644
> --- a/lib/librte_vhost/virtio_net.c
> +++ b/lib/librte_vhost/virtio_net.c
> @@ -1075,7 +1075,9 @@ virtio_dev_rx_batch_packed(struct virtio_net *dev,
> struct vhost_virtqueue *vq,
>
> UNROLL_PRAGMA(UNROLL_PRAGMA_PARAM)
> for (i = 0; i < PACKED_BATCH_SIZE; i++) {
> +#ifndef DISABLE_SWPREFETCH
> rte_prefetch0((void *)(uintptr_t)desc_addrs[i]);
> +#endif
> hdrs[i] = (struct virtio_net_hdr_mrg_rxbuf *)
> (uintptr_t)desc_addrs[i];
> lens[i] = pkts[i]->pkt_len + dev->vhost_hlen;
> @@ -1144,7 +1146,9 @@ virtio_dev_rx_packed(struct virtio_net *dev, struct
> vhost_virtqueue *vq,
> uint32_t remained = count;
>
> do {
> +#ifndef DISABLE_SWPREFETCH
> rte_prefetch0(&vq->desc_packed[vq->last_avail_idx]);
> +#endif
>
> if (remained >= PACKED_BATCH_SIZE) {
> if (!virtio_dev_rx_batch_packed(dev, vq, pkts)) {
> @@ -1790,7 +1794,9 @@ virtio_dev_tx_batch_packed(struct virtio_net *dev,
> struct vhost_virtqueue *vq,
>
> UNROLL_PRAGMA(UNROLL_PRAGMA_PARAM)
> for (i = 0; i < PACKED_BATCH_SIZE; i++) {
> +#ifndef DISABLE_SWPREFETCH
> rte_prefetch0((void *)(uintptr_t)desc_addrs[i]);
> +#endif
> rte_memcpy(rte_pktmbuf_mtod_offset(pkts[i], void *, 0),
> (void *)(uintptr_t)(desc_addrs[i] + buf_offset),
> pkts[i]->pkt_len);
> @@ -2046,7 +2052,9 @@ virtio_dev_tx_packed(struct virtio_net *dev, struct
> vhost_virtqueue *vq,
> uint32_t remained = count;
>
> do {
> +#ifndef DISABLE_SWPREFETCH
> rte_prefetch0(&vq->desc_packed[vq->last_avail_idx]);
> +#endif
>
> if (remained >= PACKED_BATCH_SIZE) {
> if (!virtio_dev_tx_batch_packed(dev, vq, mbuf_pool,
>
Re: [dpdk-dev] [PATCH 1/3] app/test: use RTE_DIM instead of ARRAY_SIZE
> -Original Message- > From: pbhagavat...@marvell.com [mailto:pbhagavat...@marvell.com] > Sent: Thursday, October 10, 2019 11:07 PM > To: Doherty, Declan ; Eads, Gage > ; Olivier Matz > Cc: dev@dpdk.org; Pavan Nikhilesh > Subject: [dpdk-dev] [PATCH 1/3] app/test: use RTE_DIM instead of > ARRAY_SIZE > > From: Pavan Nikhilesh > > Use RTE_DIM instead of re-defining ARRAY_SIZE. > > Signed-off-by: Pavan Nikhilesh > --- Acked-by: Gage Eads Thanks, Gage
Re: [dpdk-dev] [PATCH v4 03/14] vhost: add batch enqueue function for packed ring
On 10/9/19 3:38 PM, Marvin Liu wrote: > Batch enqueue function will first check whether descriptors are cache > aligned. It will also check prerequisites in the beginning. Batch > enqueue function not support chained mbufs, single packet enqueue > function will handle it. > > Signed-off-by: Marvin Liu > Thinking again about this patch and series in general... So this series improves performance by 40% in cases where: - descriptors are cache aligned - single mbuf But my understanding is that it will cause performance regression for the other cases, which may not be that uncommon, no? Do you have some number about the performance impact on these other cases? Thanks, Maxime
Re: [dpdk-dev] [PATCH v6 2/4] examples/ipsec-secgw: add fallback session feature
Hi All, > > Inline processing is limited to a specified subset of traffic. It is > often unable to handle more complicated situations, such as fragmented > traffic. When using inline processing such traffic is dropped. > > Introduce fallback session for inline processing allowing processing > packets that normally would be dropped. A fallback session is > configured by adding 'fallback' keyword with 'lookaside-none' or > 'lookaside-protocol' parameter to an SA configuration. > > Using IPsec anti-replay window or ESN feature with fallback session is > not yet supported when primary session is of type > 'inline-protocol-offload' or fallback session is 'lookaside-protocol' > because SA sequence number is not synchronized between software and > hardware sessions. Fallback sessions are also limited to ingress IPsec > traffic. > > Fallback session feature is not available in the legacy mode. > I started looking this patch, but some initial thoughts looking at the patch description. When you say a fallback session will be a lookaside none or lookaside protocol, the packet will be processed asynchronously and might as well reorder. The best possible solution for this would be the synchronous API which are in talks in another patchset or use a SW PMD(eg. Openssl etc.) session and wait till you get the packet dequeued. So effectively async APIs will be used to behave synchronously. You can not use hardware PMD session as it will perform very badly for fallback packets Because you have to wait till the packet is not getting dequeued back. Having said that, you won't find a device or a scenario where you can use Inline crypto as primary and lookaside proto as fallback. It can only be like inline crypto as primary and lookaside none as fallback. BTW, I am ok with Patch 1/4 and 3/4. If no objections from the community, I can pick those. -Akhil > Acked-by: Konstantin Ananyev > Tested-by: Bernard Iremonger > Signed-off-by: Marcin Smoczynski > ---
Re: [dpdk-dev] [PATCH v3 1/3] lib/ring: add peek API
> -Original Message-
> From: Honnappa Nagarahalli [mailto:honnappa.nagaraha...@arm.com]
> Sent: Friday, October 11, 2019 6:04 AM
> To: Ananyev, Konstantin ;
> step...@networkplumber.org; paul...@linux.ibm.com
> Cc: Wang, Yipeng1 ; Medvedkin, Vladimir
> ; Ruifeng Wang (Arm Technology
> China) ; Dharmik Thakkar ;
> dev@dpdk.org; nd ; nd
> ; nd
> Subject: RE: [PATCH v3 1/3] lib/ring: add peek API
>
> >
> > >
> > >
> > > >
> > > > >
> > > > > > > Subject: [PATCH v3 1/3] lib/ring: add peek API
> > > > > > >
> > > > > > > From: Ruifeng Wang
> > > > > > >
> > > > > > > The peek API allows fetching the next available object in the
> > > > > > > ring without dequeuing it. This helps in scenarios where
> > > > > > > dequeuing of objects depend on their value.
> > > > > > >
> > > > > > > Signed-off-by: Dharmik Thakkar
> > > > > > > Signed-off-by: Ruifeng Wang
> > > > > > > Reviewed-by: Honnappa Nagarahalli
> > > > > > >
> > > > > > > Reviewed-by: Gavin Hu
> > > > > > > ---
> > > > > > > lib/librte_ring/rte_ring.h | 30
> > > > > > > ++
> > > > > > > 1 file changed, 30 insertions(+)
> > > > > > >
> > > > > > > diff --git a/lib/librte_ring/rte_ring.h
> > > > > > > b/lib/librte_ring/rte_ring.h index 2a9f768a1..d3d0d5e18 100644
> > > > > > > --- a/lib/librte_ring/rte_ring.h
> > > > > > > +++ b/lib/librte_ring/rte_ring.h
> > > > > > > @@ -953,6 +953,36 @@ rte_ring_dequeue_burst(struct rte_ring
> > > > > > > *r, void
> > > > > > **obj_table,
> > > > > > > r->cons.single, available); }
> > > > > > >
> > > > > > > +/**
> > > > > > > + * Peek one object from a ring.
> > > > > > > + *
> > > > > > > + * The peek API allows fetching the next available object in
> > > > > > > +the ring
> > > > > > > + * without dequeuing it. This API is not multi-thread safe
> > > > > > > +with respect
> > > > > > > + * to other consumer threads.
> > > > > > > + *
> > > > > > > + * @param r
> > > > > > > + * A pointer to the ring structure.
> > > > > > > + * @param obj_p
> > > > > > > + * A pointer to a void * pointer (object) that will be filled.
> > > > > > > + * @return
> > > > > > > + * - 0: Success, object available
> > > > > > > + * - -ENOENT: Not enough entries in the ring.
> > > > > > > + */
> > > > > > > +__rte_experimental
> > > > > > > +static __rte_always_inline int rte_ring_peek(struct rte_ring
> > > > > > > +*r, void **obj_p)
> > > > > >
> > > > > > As it is not MT safe, then I think we need _sc_ in the name, to
> > > > > > follow other rte_ring functions naming conventions
> > > > > > (rte_ring_sc_peek() or so).
> > > > > Agree
> > > > >
> > > > > >
> > > > > > As a better alternative what do you think about introducing a
> > > > > > serialized versions of DPDK rte_ring dequeue functions?
> > > > > > Something like that:
> > > > > >
> > > > > > /* same as original ring dequeue, but:
> > > > > > * 1) move cons.head only if cons.head == const.tail
> > > > > > * 2) don't update cons.tail
> > > > > > */
> > > > > > unsigned int
> > > > > > rte_ring_serial_dequeue_bulk(struct rte_ring *r, void
> > > > > > **obj_table, unsigned int n,
> > > > > > unsigned int *available);
> > > > > >
> > > > > > /* sets both cons.head and cons.tail to cons.head + num */ void
> > > > > > rte_ring_serial_dequeue_finish(struct rte_ring *r, uint32_t
> > > > > > num);
> > > > > >
> > > > > > /* resets cons.head to const.tail value */ void
> > > > > > rte_ring_serial_dequeue_abort(struct rte_ring *r);
> > > > > >
> > > > > > Then your dq_reclaim cycle function will look like that:
> > > > > >
> > > > > > const uint32_t nb_elt = dq->elt_size/8 + 1; uint32_t avl, n;
> > > > > > uintptr_t elt[nb_elt]; ...
> > > > > >
> > > > > > do {
> > > > > >
> > > > > > /* read next elem from the queue */
> > > > > > n = rte_ring_serial_dequeue_bulk(dq->r, elt, nb_elt, &avl);
> > > > > > if (n == 0)
> > > > > > break;
> > > > > >
> > > > > > /* wrong period, keep elem in the queue */ if
> > > > > > (rte_rcu_qsbr_check(dr->v,
> > > > > > elt[0]) != 1) {
> > > > > > rte_ring_serial_dequeue_abort(dq->r);
> > > > > > break;
> > > > > > }
> > > > > >
> > > > > > /* can reclaim, remove elem from the queue */
> > > > > > rte_ring_serial_dequeue_finish(dr->q, nb_elt);
> > > > > >
> > > > > >/*call reclaim function */
> > > > > > dr->f(dr->p, elt);
> > > > > >
> > > > > > } while (avl >= nb_elt);
> > > > > >
> > > > > > That way, I think even rte_rcu_qsbr_dq_reclaim() can be MT safe.
> > > > > > As long as actual reclamation callback itself is MT safe of course.
> > > > >
> > > > > I think it is a great idea. The other writers would still be
> > > > > polling for the current writer to update the tail or update the
> > > > > head. This makes it a
> > > > blocking solution.
> > > >
> > > > Yep, it is a blocking one.
> > > >
> > > > > We can make the other threads not poll i.e. they will quit
> > > > > reclaiming if they
> > > > see that other w
Re: [dpdk-dev] [PATCH v5 01/10] examples/l2fwd-event: add default poll mode routines
On Thu, Oct 3, 2019 at 2:28 AM wrote: > > From: Pavan Nikhilesh > > Add the default l2fwd poll mode routines similar to examples/l2fwd. > > Signed-off-by: Sunil Kumar Kori > Signed-off-by: Pavan Nikhilesh > --- > MAINTAINERS | 5 + > examples/Makefile | 1 + examples/meson.build is not updated Please test the meson output. > examples/l2fwd-event/Makefile | 59 + > examples/l2fwd-event/l2fwd_common.c | 142 +++ > examples/l2fwd-event/l2fwd_common.h | 129 ++ > examples/l2fwd-event/l2fwd_poll.c | 197 +++ > examples/l2fwd-event/l2fwd_poll.h | 25 ++ > examples/l2fwd-event/main.c | 374 > examples/l2fwd-event/meson.build| 14 ++ > 9 files changed, 946 insertions(+) > create mode 100644 examples/l2fwd-event/Makefile > create mode 100644 examples/l2fwd-event/l2fwd_common.c > create mode 100644 examples/l2fwd-event/l2fwd_common.h > create mode 100644 examples/l2fwd-event/l2fwd_poll.c > create mode 100644 examples/l2fwd-event/l2fwd_poll.h > create mode 100644 examples/l2fwd-event/main.c > create mode 100644 examples/l2fwd-event/meson.build
Re: [dpdk-dev] [PATCH v1 6/6] crypto/ccp: updating ccp document
Hi, > > From: Amaranath Somalapuram > > Signed-off-by: Amaranath Somalapuram > --- Title should be "crypto/ccp: fix documentation" Please add an appropriate description to the patch. This patch is a fix and should also have fixes tag and also cc to sta...@dpdk.org > doc/guides/cryptodevs/ccp.rst | 32 > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/doc/guides/cryptodevs/ccp.rst b/doc/guides/cryptodevs/ccp.rst > index 034d20367..a43fe92de 100644 > --- a/doc/guides/cryptodevs/ccp.rst > +++ b/doc/guides/cryptodevs/ccp.rst > @@ -109,14 +109,14 @@ To validate ccp pmd, l2fwd-crypto example can be > used with following command: > > .. code-block:: console > > - sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 > - --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC > - --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f > - --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff > - --auth_op GENERATE --auth_algo SHA1_HMAC > - --auth_key > 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > - > :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:1 > 1:11:11 > - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > +sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 > +--chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo aes-cbc > +--cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f > +--cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff > +--auth_op GENERATE --auth_algo sha1-hmac > +--auth_key > 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > + > :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:1 > 1:11 > +:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > > The CCP PMD also supports computing authentication over CPU with cipher > offloaded to CCP. > To enable this feature, pass an additional argument as ccp_auth_opt=1 to -- > vdev parameters as > @@ -124,14 +124,14 @@ following: > > .. code-block:: console > > - sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp,ccp_auth_opt=1" > -- -p 0x1 > - --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC > - --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f > - --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff > - --auth_op GENERATE --auth_algo SHA1_HMAC > - --auth_key > 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > - > :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:1 > 1:11:11 > - :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > +sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev > "crypto_ccp,ccp_auth_opt=1" -- - > p 0x1 > +--chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo aes-cbc > +--cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f > +--cipher_iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff > +--auth_op GENERATE --auth_algo sha1-hmac > +--auth_key > 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > + > :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:1 > 1:11 > +:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 > > Limitations > --- > -- > 2.17.1
Re: [dpdk-dev] [PATCH v5 08/10] examples/l2fwd-event: add eventdev main loop
On Thu, Oct 3, 2019 at 2:29 AM wrote:
>
> From: Pavan Nikhilesh
>
> Add event dev main loop based on enabled l2fwd options and eventdev
> capabilities.
>
> Signed-off-by: Pavan Nikhilesh
> ---
> examples/l2fwd-event/l2fwd_common.c | 6 +
> examples/l2fwd-event/l2fwd_common.h | 2 +
> examples/l2fwd-event/l2fwd_event.c | 294
> examples/l2fwd-event/l2fwd_event.h | 2 +
> examples/l2fwd-event/main.c | 6 +-
> 5 files changed, 309 insertions(+), 1 deletion(-)
>
> diff --git a/examples/l2fwd-event/l2fwd_common.c
> b/examples/l2fwd-event/l2fwd_common.c
> index 213652d72..40e933c91 100644
> --- a/examples/l2fwd-event/l2fwd_common.c
> +++ b/examples/l2fwd-event/l2fwd_common.c
> @@ -65,6 +65,12 @@ l2fwd_event_init_ports(struct l2fwd_resources *l2fwd_rsrc)
> uint16_t port_id;
> int ret;
>
> + if (l2fwd_rsrc->event_mode) {
> + port_conf.rxmode.mq_mode = ETH_MQ_RX_RSS;
> + port_conf.rx_adv_conf.rss_conf.rss_key = NULL;
> + port_conf.rx_adv_conf.rss_conf.rss_hf = ETH_RSS_IP;
> + }
> +
> /* Initialise each port */
> RTE_ETH_FOREACH_DEV(port_id) {
> struct rte_eth_conf local_port_conf = port_conf;
> diff --git a/examples/l2fwd-event/l2fwd_common.h
> b/examples/l2fwd-event/l2fwd_common.h
> index cdafa52c7..852c6d321 100644
> --- a/examples/l2fwd-event/l2fwd_common.h
> +++ b/examples/l2fwd-event/l2fwd_common.h
> @@ -114,7 +114,9 @@ l2fwd_get_rsrc(void)
>
> memset(l2fwd_rsrc, 0, sizeof(struct l2fwd_resources));
> l2fwd_rsrc->mac_updating = true;
> + l2fwd_rsrc->event_mode = true;
> l2fwd_rsrc->rx_queue_per_lcore = 1;
> + l2fwd_rsrc->sched_type = RTE_SCHED_TYPE_ATOMIC;
> l2fwd_rsrc->timer_period = 10 * rte_get_timer_hz();
>
> return mz->addr;
> diff --git a/examples/l2fwd-event/l2fwd_event.c
> b/examples/l2fwd-event/l2fwd_event.c
> index adba40069..df0b56773 100644
> --- a/examples/l2fwd-event/l2fwd_event.c
> +++ b/examples/l2fwd-event/l2fwd_event.c
> @@ -17,6 +17,12 @@
>
> #include "l2fwd_event.h"
>
> +#define L2FWD_EVENT_SINGLE 0x1
> +#define L2FWD_EVENT_BURST 0x2
> +#define L2FWD_EVENT_TX_DIRECT 0x4
> +#define L2FWD_EVENT_TX_ENQ 0x8
> +#define L2FWD_EVENT_UPDT_MAC 0x10
> +
> static inline int
> l2fwd_event_service_enable(uint32_t service_id)
> {
> @@ -128,11 +134,289 @@ l2fwd_event_capability_setup(struct
> l2fwd_event_resources *event_rsrc)
> l2fwd_event_set_internal_port_ops(&event_rsrc->ops);
> }
>
> +static __rte_noinline int
> +l2fwd_get_free_event_port(struct l2fwd_event_resources *event_rsrc)
> +{
> + static int index;
> + int port_id;
> +
> + rte_spinlock_lock(&event_rsrc->evp.lock);
> + if (index >= event_rsrc->evp.nb_ports) {
> + printf("No free event port is available\n");
> + return -1;
> + }
> +
> + port_id = event_rsrc->evp.event_p_id[index];
> + index++;
> + rte_spinlock_unlock(&event_rsrc->evp.lock);
> +
> + return port_id;
> +}
> +
> +static __rte_always_inline void
> +l2fwd_event_loop_single(struct l2fwd_resources *l2fwd_rsrc,
> + const uint32_t flags)
> +{
> + const uint8_t is_master = rte_get_master_lcore() == rte_lcore_id();
> + struct l2fwd_event_resources *event_rsrc = l2fwd_rsrc->event_rsrc;
> + const int port_id = l2fwd_get_free_event_port(event_rsrc);
> + uint64_t prev_tsc = 0, diff_tsc, cur_tsc, timer_tsc = 0;
> + const uint64_t timer_period = l2fwd_rsrc->timer_period;
> + const uint8_t tx_q_id = event_rsrc->evq.event_q_id[
> + event_rsrc->evq.nb_queues - 1];
See below
> + const uint8_t event_d_id = event_rsrc->event_d_id;
> + struct rte_mbuf *mbuf;
> + uint16_t dst_port;
> + struct rte_event ev;
> +
> + if (port_id < 0)
> + return;
> +
> + printf("%s(): entering eventdev main loop on lcore %u\n", __func__,
> + rte_lcore_id());
> +
> + while (!l2fwd_rsrc->force_quit) {
> + /* if timer is enabled */
> + if (is_master && timer_period > 0) {
> + cur_tsc = rte_rdtsc();
> + diff_tsc = cur_tsc - prev_tsc;
> +
> + /* advance the timer */
> + timer_tsc += diff_tsc;
> +
> + /* if timer has reached its timeout */
> + if (unlikely(timer_tsc >= timer_period)) {
> + print_stats(l2fwd_rsrc);
> + /* reset the timer */
> + timer_tsc = 0;
> + }
> + prev_tsc = cur_tsc;
> + }
> +
> + /* Read packet from eventdev */
> + if (!rte_event_dequeue_
Re: [dpdk-dev] [PATCH v6 2/4] examples/ipsec-secgw: add fallback session feature
Hi Akhil, > > > > Inline processing is limited to a specified subset of traffic. It is > > often unable to handle more complicated situations, such as fragmented > > traffic. When using inline processing such traffic is dropped. > > > > Introduce fallback session for inline processing allowing processing > > packets that normally would be dropped. A fallback session is > > configured by adding 'fallback' keyword with 'lookaside-none' or > > 'lookaside-protocol' parameter to an SA configuration. > > > > Using IPsec anti-replay window or ESN feature with fallback session is > > not yet supported when primary session is of type > > 'inline-protocol-offload' or fallback session is 'lookaside-protocol' > > because SA sequence number is not synchronized between software and > > hardware sessions. Fallback sessions are also limited to ingress IPsec > > traffic. > > > > Fallback session feature is not available in the legacy mode. > > > I started looking this patch, but some initial thoughts looking at the patch > description. > > When you say a fallback session will be a lookaside none or lookaside > protocol, > the packet will be processed asynchronously and might as well reorder. Yes, we documented it as one of limitations. Though as I already mentioned for some use-cases some reordering it is acceptable. > The best possible solution for this would be the synchronous API which are > in talks Agree, that would be a way to avoid reordering, but it is not there yet. > in another patchset or use a SW PMD(eg. Openssl etc.) session and wait till > you get the packet dequeued. > So effectively async APIs will be used to behave synchronously. > You can not use hardware PMD session as it will perform very badly for > fallback packets > Because you have to wait till the packet is not getting dequeued back. We don't plan to support that model because of great performance penalty you mentioned. > > Having said that, you won't find a device or a scenario where you can use > Inline crypto as primary and lookaside proto as fallback. > It can only be like inline crypto as primary and lookaside none as fallback. Yes, correct. I thought that we already removed lookaside-proto from supported types. If we didn't - will certainly do that. > > BTW, I am ok with Patch 1/4 and 3/4. If no objections from the community, I > can pick those. Great to hear. What obstacles do you see with others two? Konstantin > > -Akhil > > > Acked-by: Konstantin Ananyev > > Tested-by: Bernard Iremonger > > Signed-off-by: Marcin Smoczynski > > ---
Re: [dpdk-dev] [PATCH v2 0/3] examples/ipsec-secgw: set default
Hi Akhil, With this patch applied the legacy code path in the ipsec-secgw application is still available. The default code path is now to use librte_ipsec. The "-l 0" option at startup allows the legacy code path to be used. Both code paths are still available. Regards, Bernard > -Original Message- > From: Akhil Goyal [mailto:akhil.go...@nxp.com] > Sent: Friday, October 11, 2019 1:40 PM > To: Iremonger, Bernard ; dev@dpdk.org; > Ananyev, Konstantin ; > ano...@marvell.com; jer...@marvell.com; 'Thomas Monjalon' > > Subject: RE: [PATCH v2 0/3] examples/ipsec-secgw: set default > > Hi All, > > This patchset would need ack from more vendors as it will impact user > experience on a key example application which is normally demonstrated to > customers. > > IPSec library is still evolving and there are new functionality added every > release. > Atleast from NXP side we are not OK with this change. > > I would hold this patch till RC2 atleast. > > Regards, > Akhil > > > -Original Message- > > From: Bernard Iremonger > > Sent: Tuesday, October 1, 2019 8:48 PM > > To: dev@dpdk.org; konstantin.anan...@intel.com; Akhil Goyal > > > > Cc: Bernard Iremonger > > Subject: [PATCH v2 0/3] examples/ipsec-secgw: set default > > > > This patch set, sets the default code path in the ipsec-secgw > > application to use the librte_ipsec. > > The *_old test scripts have been modified to use the legacy code path. > > > > Changes in v2: > > - > > The error messages for the -l option have been updated. > > The pktest.sh script has been updated to drop the -l option. > > > > Bernard Iremonger (3): > > examples/ipsec-secgw: set default to IPsec library mode > > examples/ipsec-secgw: add -l 0 parameter to old scripts > > examples/ipsec-secgw: update pktest.sh script > > > > doc/guides/rel_notes/release_19_11.rst | 8 > > doc/guides/sample_app_ug/ipsec_secgw.rst | 6 ++- > > examples/ipsec-secgw/ipsec-secgw.c | 46 > > ++--- > - > > examples/ipsec-secgw/test/pkttest.sh | 1 - > > .../ipsec-secgw/test/trs_3descbc_sha1_old_defs.sh | 2 +- > > .../ipsec-secgw/test/trs_aescbc_sha1_old_defs.sh | 2 +- > > .../ipsec-secgw/test/trs_aesctr_sha1_old_defs.sh | 2 +- > > .../test/trs_aesgcm_inline_crypto_old_defs.sh | 2 +- > > examples/ipsec-secgw/test/trs_aesgcm_old_defs.sh | 2 +- > > .../ipsec-secgw/test/tun_3descbc_sha1_old_defs.sh | 2 +- > > .../ipsec-secgw/test/tun_aescbc_sha1_old_defs.sh | 2 +- > > .../ipsec-secgw/test/tun_aesctr_sha1_old_defs.sh | 2 +- > > .../test/tun_aesgcm_inline_crypto_old_defs.sh | 2 +- > > examples/ipsec-secgw/test/tun_aesgcm_old_defs.sh | 2 +- > > 14 files changed, 52 insertions(+), 29 deletions(-) > > > > -- > > 2.7.4
Re: [dpdk-dev] [PATCH v6 1/3] vhost: translate incoming log address to gpa
On 10/9/19 1:54 PM, Adrian Moreno wrote:
> When IOMMU is enabled the incoming log address is in IOVA space. In that
> case, look in IOTLB table and translate the resulting HVA to GPA.
>
> If IOMMU is not enabled, the incoming log address is already a GPA so no
> transformation is needed.
>
> Fixes: 69c90e98f483 ("vhost: enable IOMMU support")
> Cc: maxime.coque...@redhat.com
> Cc: sta...@dpdk.org
> Signed-off-by: Adrian Moreno
>
> ---
> v6 changes: use PRIx64 macro to fix UB1604-32 build
> v5 changes: Rebase on top of dpdk-next-virtio
> ---
> lib/librte_vhost/vhost.c | 1 +
> lib/librte_vhost/vhost.h | 20 +
> lib/librte_vhost/vhost_user.c | 42 ++-
> 3 files changed, 62 insertions(+), 1 deletion(-)
>
Reviewed-by: Maxime Coquelin
Thanks,
Maxime
Re: [dpdk-dev] [PATCH v6 2/3] vhost: convert buffer addresses to GPA for logging
On 10/9/19 1:54 PM, Adrian Moreno wrote:
> Add IOVA versions of dirty page logging functions.
>
> Note that the API facing rte_vhost_log_write is not modified.
> So, make explicit that it expects the address in GPA space.
>
> Fixes: 69c90e98f483 ("vhost: enable IOMMU support")
> Cc: maxime.coque...@redhat.com
> Cc: sta...@dpdk.org
> Signed-off-by: Adrian Moreno
>
> --
> v4 Changes: Add vhost_log_write_iova (in adition to _cache_ version)
> and use it in vdpa (non-batched) dirty page logging
> ---
> lib/librte_vhost/rte_vhost.h | 2 +-
> lib/librte_vhost/vdpa.c | 3 ++-
> lib/librte_vhost/vhost.c | 40 +++
> lib/librte_vhost/vhost.h | 31 +++
> lib/librte_vhost/virtio_net.c | 12 ++-
> 5 files changed, 81 insertions(+), 7 deletions(-)
Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v6 3/3] vhost: prevent zero copy mode if iommu is on
On 10/9/19 1:54 PM, Adrian Moreno wrote:
> The simultaneous use of dequeue_zero_copy and IOMMU is problematic.
> Not only because IOVA_VA mode is not supported but also because the
> potential invalidation of guest pages while the buffers are in use,
> is not handled.
>
> Prevent these two features to be enabled simultaneously.
>
> Fixes: 69c90e98f483 ("vhost: enable IOMMU support")
> Cc: maxime.coque...@redhat.com
> Cc: sta...@dpdk.org
>
> Reviewed-by: Tiwei Bie
> Signed-off-by: Adrian Moreno
>
> ---
> lib/librte_vhost/socket.c | 8
> 1 file changed, 8 insertions(+)
Reviewed-by: Maxime Coquelin
Re: [dpdk-dev] [PATCH v2 0/3] examples/ipsec-secgw: set default
11/10/2019 14:40, Akhil Goyal: > Hi All, > > This patchset would need ack from more vendors as it will impact user > experience > on a key example application which is normally demonstrated to customers. > > IPSec library is still evolving and there are new functionality added every > release. > Atleast from NXP side we are not OK with this change. What can be changed in the library to make it acceptable as a default in this example?
Re: [dpdk-dev] [PATCH v3] net/bonding: fix selection logic
This looks better. While reviewing this I noticed that a few lines:
case AGG_STABLE:
if (default_slave == slaves_count)
new_agg_id = slave_id; <
else
new_agg_id = slaves[default_slave];
break;
default:
if (default_slave == slaves_count)
new_agg_id = slave_id; <
else
new_agg_id = slaves[default_slave];
break;
}
I don't think the new_agg_id should be the slave_id directly but rather
slaves[slave_id]. Would you mind fixing that as well here if that is
the case?
On 10/11/19 2:34 AM, kka...@marvell.com wrote:
From: Krzysztof Kanas
Arrays agg_count and agg_bandwidth should be indexed by slave_id not by
aggregator port_id.
Fixes: 6d72657ce379 ("net/bonding: add other aggregator modes")
Cc: danielx.t.mrzyg...@intel.com
Signed-off-by: Krzysztof Kanas
---
v3:
* fix incorrect reabse
v2:
* rebase patch to latest master
drivers/net/bonding/rte_eth_bond_8023ad.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
--
diff --git a/drivers/net/bonding/rte_eth_bond_8023ad.c
b/drivers/net/bonding/rte_eth_bond_8023ad.c
index 7d8da2b318f5..698311e15c31 100644
--- a/drivers/net/bonding/rte_eth_bond_8023ad.c
+++ b/drivers/net/bonding/rte_eth_bond_8023ad.c
@@ -673,9 +673,8 @@ selection_logic(struct bond_dev_private *internals,
uint16_t slave_id)
uint64_t agg_bandwidth[RTE_MAX_ETHPORTS] = {0};
uint64_t agg_count[RTE_MAX_ETHPORTS] = {0};
uint16_t default_slave = 0;
- uint16_t mode_count_id;
- uint16_t mode_band_id;
struct rte_eth_link link_info;
+ uint16_t agg_new_idx = 0;
int ret;
slaves = internals->active_slaves;
@@ -696,8 +695,8 @@ selection_logic(struct bond_dev_private *internals,
uint16_t slave_id)
slaves[i], rte_strerror(-ret));
continue;
}
- agg_count[agg->aggregator_port_id] += 1;
- agg_bandwidth[agg->aggregator_port_id] += link_info.link_speed;
+ agg_count[i] += 1;
+ agg_bandwidth[i] += link_info.link_speed;
/* Actors system ID is not checked since all slave device have the same
* ID (MAC address). */
@@ -718,12 +717,12 @@ selection_logic(struct bond_dev_private *internals,
uint16_t slave_id)
switch (internals->mode4.agg_selection) {
case AGG_COUNT:
- mode_count_id = max_index(agg_count, slaves_count);
- new_agg_id = mode_count_id;
+ agg_new_idx = max_index(agg_count, slaves_count);
+ new_agg_id = slaves[agg_new_idx];
break;
case AGG_BANDWIDTH:
- mode_band_id = max_index(agg_bandwidth, slaves_count);
- new_agg_id = mode_band_id;
+ agg_new_idx = max_index(agg_bandwidth, slaves_count);
+ new_agg_id = slaves[agg_new_idx];
break;
case AGG_STABLE:
if (default_slave == slaves_count)
Re: [dpdk-dev] [PATCH v2 8/9] net/qede/base: update the FW to 8.40.25.0
On 10/6/2019 9:14 PM, Rasesh Mody wrote:
> This patch updates the FW to 8.40.25.0 and corresponding base driver
> changes. It also updates the PMD version to 2.11.0.1. The FW updates
> consists of enhancements and fixes as described below.
>
> - VF RX queue start ramrod can get stuck due to completion error.
>Return EQ completion with error, when fail to load VF data. Use VF
>FID in RX queue start ramrod
> - Fix big receive buffer initialization for 100G to address failure
>leading to BRB hardware assertion
> - GRE tunnel traffic doesn't run when non-L2 ethernet protocol is enabled,
>fix FW to not forward tunneled SYN packets to LL2.
> - Fix the FW assert that is caused during vport_update when
>tx-switching is enabled
> - Add initial FW support for VF Representors
> - Add ecore_get_hsi_def_val() API to get default HSI values
> - Move following from .c to .h files:
>TSTORM_QZONE_START and MSTORM_QZONE_START
>enum ilt_clients
>renamed struct ecore_dma_mem to phys_mem_desc and moved
> - Add ecore_cxt_set_cli() and ecore_cxt_set_blk() APIs to set client
>config and block details
> - Use SET_FIELD() macro where appropriate
> - Address spell check and code alignment issues
>
> Signed-off-by: Rasesh Mody
<...>
> -void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size,
> +void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn,
> +void *p_ctx_mem, u16 ctx_size,
> u8 ctx_type, u32 cid)
> {
> u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
>
> - p_ctx = (u8 *)p_ctx_mem;
> + p_ctx = (u8 * const)p_ctx_mem;
This is causing build error with icc [1], I will remove 'const' while merging.
[1]
error #191: type qualifier is meaningless on cast type
<...>
> -void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
> +void ecore_memset_session_ctx(struct ecore_hwfn *p_hwfn, void *p_ctx_mem,
> + u32 ctx_size, u8 ctx_type)
> {
> u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
> u8 x_val, t_val, u_val;
>
> - p_ctx = (u8 *)p_ctx_mem;
> + p_ctx = (u8 * const)p_ctx_mem;
Ditto
Re: [dpdk-dev] [PATCH] kni: add ability to set min/max MTU
On 9/19/2019 12:22 PM, Igor Ryzhov wrote: > Starting with kernel version 4.10, there are new min/max MTU values in > net_device structure, which are set to ETH_MIN_MTU and ETH_DATA_LEN by > default. We should be able to change these values to allow MTU more than > 1500 to be set on KNI. > > Signed-off-by: Igor Ryzhov Acked-by: Ferruh Yigit
Re: [dpdk-dev] [PATCH v2 8/9] net/qede/base: update the FW to 8.40.25.0
>From: Ferruh Yigit
>Sent: Friday, October 11, 2019 9:14 AM
>
>On 10/6/2019 9:14 PM, Rasesh Mody wrote:
>> This patch updates the FW to 8.40.25.0 and corresponding base driver
>> changes. It also updates the PMD version to 2.11.0.1. The FW updates
>> consists of enhancements and fixes as described below.
>>
>> - VF RX queue start ramrod can get stuck due to completion error.
>>Return EQ completion with error, when fail to load VF data. Use VF
>>FID in RX queue start ramrod
>> - Fix big receive buffer initialization for 100G to address failure
>>leading to BRB hardware assertion
>> - GRE tunnel traffic doesn't run when non-L2 ethernet protocol is enabled,
>>fix FW to not forward tunneled SYN packets to LL2.
>> - Fix the FW assert that is caused during vport_update when
>>tx-switching is enabled
>> - Add initial FW support for VF Representors
>> - Add ecore_get_hsi_def_val() API to get default HSI values
>> - Move following from .c to .h files:
>>TSTORM_QZONE_START and MSTORM_QZONE_START
>>enum ilt_clients
>>renamed struct ecore_dma_mem to phys_mem_desc and moved
>> - Add ecore_cxt_set_cli() and ecore_cxt_set_blk() APIs to set client
>>config and block details
>> - Use SET_FIELD() macro where appropriate
>> - Address spell check and code alignment issues
>>
>> Signed-off-by: Rasesh Mody
>
><...>
>
>> -void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size,
>> +void ecore_calc_session_ctx_validation(struct ecore_hwfn *p_hwfn,
>> + void *p_ctx_mem, u16 ctx_size,
>> u8 ctx_type, u32 cid)
>> {
>> u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
>>
>> -p_ctx = (u8 *)p_ctx_mem;
>> +p_ctx = (u8 * const)p_ctx_mem;
>
>This is causing build error with icc [1], I will remove 'const' while merging.
Sure thanks.
>[1]
>error #191: type qualifier is meaningless on cast type
>
><...>
>
>> -void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8
>> ctx_type)
>> +void ecore_memset_session_ctx(struct ecore_hwfn *p_hwfn, void
>*p_ctx_mem,
>> + u32 ctx_size, u8 ctx_type)
>> {
>> u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
>> u8 x_val, t_val, u_val;
>>
>> -p_ctx = (u8 *)p_ctx_mem;
>> +p_ctx = (u8 * const)p_ctx_mem;
>
>Ditto
Re: [dpdk-dev] 18.11.3 (LTS) patches review and test
Is there any other partners have done DPDK performance test with different OS distro? I wonder if this is distro-specific or Azure-specific. Ju -Original Message- From: Abhishek Marathe Sent: Friday, October 11, 2019 9:30 AM To: Kevin Traynor ; sta...@dpdk.org Cc: dev@dpdk.org; Akhil Goyal ; Ali Alnubani ; benjamin.wal...@intel.com; David Christensen ; Hemant Agrawal ; Ian Stokes ; Jerin Jacob ; John McNamara ; Ju-Hyoung Lee ; Luca Boccassi ; Pei Zhang ; pingx...@intel.com; qian.q...@intel.com; Raslan Darawsheh ; Thomas Monjalon ; yuan.p...@intel.com; zhaoyan.c...@intel.com Subject: RE: 18.11.3 (LTS) patches review and test Hi All, Our Findings while testing DPDK 18.11.3-rc2 release: 1. PERF-DPDK-MULTICORE-PPS-F32: This testcase is failing for almost all the distros. I can reproduce the problem but there are no errors in the Kernel logs / Test Execution logs. It seems that failure is due to lower performance than threshold. As this testcase was not failing for the previous releases, we are going to investigate it further. 2. We are getting low performance for Ubuntu distribution failed testcases. Test Result: DPDK v18.11.3-rc2 was validated on Azure for Canonical UbuntuServer 16.04-LTS latest, Canonical UbuntuServer 18.04-DAILY-LTS latest, RedHat RHEL 7-RAW latest, RedHat RHEL 7.5 latest, Openlogic CentOS 7.5 latest, SUSE SLES 15 latest. Tested with Mellanox and netvsc poll-mode drivers. The tests were executed using LISAv2 framework (https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2FLIS%2FLISAv2&data=02%7C01%7Cjuhlee%40microsoft.com%7C8ad50d4d779c486a550e08d74e68350b%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C637064081778210151&sdata=vcX1Tnc4v8w2RbdL4xNOQbkrvba4R5lyymiznEYj4Dk%3D&reserved=0). Test case description: * VERIFY-DPDK-COMPLIANCE - verifies kernel is supported and that the build is successful * VERIFY-DPDK-BUILD-AND-TESTPMD-TEST - verifies using testpmd that packets can be sent from a VM to another VM * VERIFY-SRIOV-FAILSAFE-FOR-DPDK - disables/enables Accelerated Networking for the NICs under test and makes sure DPDK works in both scenarios * VERIFY-DPDK-FAILSAFE-DURING-TRAFFIC - disables/enables Accelerated Networking for the NICs while generating traffic using testpmd * PERF-DPDK-FWD-PPS-DS15 - verifies DPDK forwarding performance using testpmd on 2, 4, 8 cores, rx and io mode on size Standard_DS15_v2 * PERF-DPDK-SINGLE-CORE-PPS-DS4 - verifies DPDK performance using testpmd on 1 core, rx and io mode on size Standard_DS4_v2 * PERF-DPDK-SINGLE-CORE-PPS-DS15 - verifies DPDK performance using testpmd on 1 core, rx and io mode on size Standard_DS15_v2 * PERF-DPDK-MULTICORE-PPS-DS15 - verifies DPDK performance using testpmd on 2, 4, 8 cores, rx and io mode on size Standard_DS15_v2 * PERF-DPDK-MULTICORE-PPS-F32 - verifies DPDK performance using testpmd on 2, 4, 8, 16 cores, rx and io mode on size Standard_F32s_v2 * DPDK-RING-LATENCY - verifies DPDK CPU latency using https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fshemminger%2Fdpdk-ring-ping.git&data=02%7C01%7Cjuhlee%40microsoft.com%7C8ad50d4d779c486a550e08d74e68350b%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C637064081778210151&sdata=w1ShwRLxHcqibCZKwDmyxWjH5AIlz096gLsek4J1zGY%3D&reserved=0 * VERIFY-DPDK-PRIMARY-SECONDARY-PROCESSES - verifies primary / secondary processes support for DPDK. Runs only on RHEL and Ubuntu distros with Linux kernel >= 4.20 * VERIFY-DPDK-OVS - builds OVS with DPDK support and tests if the OVS DPDK ports can be created. Runs only on Ubuntu distro. * VERIFY-DPDK-VPP - builds VPP with DPDK support and tests if the VPP ports are present. Runs only on RHEL and Ubuntu distros. * VERIFY-DPDK-NFF-GO - builds NFF-GO with DPDK support and runs the functional tests from the NFF-GO repository. Runs only on Ubuntu distro. DPDK job exited with status: UNSTABLE - https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Flinuxpipeline.westus2.cloudapp.azure.com%2Fjob%2FDPDK%2Fjob%2Fpipeline-dpdk-validation%2Fjob%2Fmaster%2F252%2F&data=02%7C01%7Cjuhlee%40microsoft.com%7C8ad50d4d779c486a550e08d74e68350b%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C637064081778210151&sdata=jy8T4kTBur4KpeCWFix4s5Pr8KiYFnSW9RPS9Cbjz4I%3D&reserved=0. Test results for DPDK 'v18.11.3-rc2' and Azure image: 'Canonical UbuntuServer 16.04-LTS latest': * PERF-DPDK-SINGLE-CORE-PPS-DS4: FAILED * VERIFY-DPDK-OVS: PASSED * VERIFY-DPDK-BUILD-AND-TESTPMD-TEST: PASSED * VERIFY-SRIOV-FAILSAFE-FOR-DPDK: PASSED * PERF-DPDK-MULTICORE-PPS-F32: FAILED * VERIFY-DPDK-FAILSAFE-DURING-TRAFFIC: ABORTED * PERF-DPDK-FWD-PPS-DS15: FAILED * PERF-DPDK-SINGLE-CORE-PPS-DS15: FAILED * PERF-DPDK-MULTICORE-PPS-DS15: FAILED * VERIFY-DPDK-COMPLIANCE: PASSED * VERIFY-DPDK-RING-LATENCY: PASSED Test results for DPDK 'v18.11.3-rc2' and Azure image: 'Canonical UbuntuServer 18.04-DAILY-LTS latest': * PERF-DPDK-SINGLE-CORE-PPS-DS4: FAILED * VERIFY-DPDK-OVS
[dpdk-dev] [PATCH 01/10] test/crypto: fix PDCP test support
use session_priv_mpool instead of session pool
Fixes: d883e6e7131b ("test/crypto: add PDCP C-Plane encap cases")
Signed-off-by: Hemant Agrawal
---
app/test/test_cryptodev.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index ffed298fd..879b31ceb 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -7144,7 +7144,7 @@ test_pdcp_proto(int i, int oop,
/* Create security session */
ut_params->sec_session = rte_security_session_create(ctx,
- &sess_conf, ts_params->session_mpool);
+ &sess_conf, ts_params->session_priv_mpool);
if (!ut_params->sec_session) {
printf("TestCase %s()-%d line %d failed %s: ",
@@ -7393,7 +7393,7 @@ test_pdcp_proto_SGL(int i, int oop,
/* Create security session */
ut_params->sec_session = rte_security_session_create(ctx,
- &sess_conf, ts_params->session_mpool);
+ &sess_conf, ts_params->session_priv_mpool);
if (!ut_params->sec_session) {
printf("TestCase %s()-%d line %d failed %s: ",
--
2.17.1
[dpdk-dev] [PATCH 00/10] NXP DPAAx crypto fixes
This patch series largely content 1. fixes in crypto drivers 2. supprot ESN like cases 3. enabling snow/ZUC for dpaa_sec Hemant Agrawal (7): test/crypto: fix PDCP test support crypto/dpaa2_sec: fix ipv6 support test/crypto: increase test cases support for dpaax test/crypto: add test to test ESN like case crypto/dpaa_sec: add support for snow3G and ZUC test/crypto: enable snow3G and zuc cases for dpaa crypto/dpaa_sec: code reorg for better session mgmt Vakul Garg (3): crypto/dpaa_sec: fix to check for aead as well crypto/dpaa2_sec: enhance gcm descs to not skip aadt crypto/dpaa2_sec: add support of auth trailer in cipher-auth app/test/test_cryptodev.c | 483 ++- app/test/test_cryptodev_aes_test_vectors.h | 67 ++ doc/guides/cryptodevs/dpaa_sec.rst | 4 + doc/guides/cryptodevs/features/dpaa_sec.ini | 4 + drivers/crypto/caam_jr/caam_jr.c| 24 +- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 47 +- drivers/crypto/dpaa2_sec/hw/desc/algo.h | 10 - drivers/crypto/dpaa2_sec/hw/desc/ipsec.h| 167 ++-- drivers/crypto/dpaa_sec/dpaa_sec.c | 844 +--- drivers/crypto/dpaa_sec/dpaa_sec.h | 109 ++- 10 files changed, 1319 insertions(+), 440 deletions(-) -- 2.17.1
[dpdk-dev] [PATCH 02/10] crypto/dpaa2_sec: fix ipv6 support
HW PDB Option was being overwritten.
Fixes: 53982ba2805d ("crypto/dpaa2_sec: support IPv6 tunnel for protocol
offload")
Signed-off-by: Hemant Agrawal
---
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 2ab34a00f..14f0c523c 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -2819,13 +2819,12 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev,
RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {
flc->dhr = SEC_FLC_DHR_INBOUND;
memset(&decap_pdb, 0, sizeof(struct ipsec_decap_pdb));
- decap_pdb.options = sizeof(struct ip) << 16;
- if (ipsec_xform->options.esn)
- decap_pdb.options |= PDBOPTS_ESP_ESN;
decap_pdb.options = (ipsec_xform->tunnel.type ==
RTE_SECURITY_IPSEC_TUNNEL_IPV4) ?
sizeof(struct ip) << 16 :
sizeof(struct rte_ipv6_hdr) << 16;
+ if (ipsec_xform->options.esn)
+ decap_pdb.options |= PDBOPTS_ESP_ESN;
session->dir = DIR_DEC;
bufsize = cnstr_shdsc_ipsec_new_decap(priv->flc_desc[0].desc,
1, 0, SHR_SERIAL,
--
2.17.1
[dpdk-dev] [PATCH 03/10] crypto/dpaa_sec: fix to check for aead as well
From: Vakul Garg
The code shall also check aead as non auth-cipher case
Fixes: 1f14d500bce1 ("crypto/dpaa_sec: support IPsec protocol offload")
Cc: sta...@dpdk.org
Signed-off-by: Vakul Garg
---
drivers/crypto/dpaa_sec/dpaa_sec.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c
b/drivers/crypto/dpaa_sec/dpaa_sec.c
index 38cfdd378..e89cbcefb 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.c
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
@@ -266,7 +266,8 @@ static inline int is_auth_cipher(dpaa_sec_session *ses)
return ((ses->cipher_alg != RTE_CRYPTO_CIPHER_NULL) &&
(ses->auth_alg != RTE_CRYPTO_AUTH_NULL) &&
(ses->proto_alg != RTE_SECURITY_PROTOCOL_PDCP) &&
- (ses->proto_alg != RTE_SECURITY_PROTOCOL_IPSEC));
+ (ses->proto_alg != RTE_SECURITY_PROTOCOL_IPSEC) &&
+ (ses->aead_alg == 0));
}
static inline int is_proto_ipsec(dpaa_sec_session *ses)
--
2.17.1
[dpdk-dev] [PATCH 04/10] crypto/dpaa2_sec: enhance gcm descs to not skip aadt
From: Vakul Garg
The GCM descriptors needlessly skip auth_only_len bytes from output
buffer. Due to this, workarounds have to be made in dpseci driver code.
Also this leads to failing of one cryptodev test case for gcm. In this
patch, we change the descriptor construction and adjust dpseci driver
accordingly. The test_AES_GCM_auth_encrypt_SGL_out_of_place_400B_1seg
now passes.
Signed-off-by: Vakul Garg
---
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 25 -
drivers/crypto/dpaa2_sec/hw/desc/algo.h | 10 -
drivers/crypto/dpaa_sec/dpaa_sec.c | 14 +---
3 files changed, 15 insertions(+), 34 deletions(-)
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 14f0c523c..8803e8d3c 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -350,14 +350,13 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess,
DPAA2_SET_FLE_INTERNAL_JD(op_fle, auth_only_len);
op_fle->length = (sess->dir == DIR_ENC) ?
- (sym_op->aead.data.length + icv_len + auth_only_len) :
- sym_op->aead.data.length + auth_only_len;
+ (sym_op->aead.data.length + icv_len) :
+ sym_op->aead.data.length;
/* Configure Output SGE for Encap/Decap */
DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf));
- DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off +
- RTE_ALIGN_CEIL(auth_only_len, 16) - auth_only_len);
- sge->length = mbuf->data_len - sym_op->aead.data.offset + auth_only_len;
+ DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off + sym_op->aead.data.offset);
+ sge->length = mbuf->data_len - sym_op->aead.data.offset;
mbuf = mbuf->next;
/* o/p segs */
@@ -510,24 +509,21 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,
if (auth_only_len)
DPAA2_SET_FLE_INTERNAL_JD(fle, auth_only_len);
fle->length = (sess->dir == DIR_ENC) ?
- (sym_op->aead.data.length + icv_len + auth_only_len) :
- sym_op->aead.data.length + auth_only_len;
+ (sym_op->aead.data.length + icv_len) :
+ sym_op->aead.data.length;
DPAA2_SET_FLE_SG_EXT(fle);
/* Configure Output SGE for Encap/Decap */
DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(dst));
- DPAA2_SET_FLE_OFFSET(sge, dst->data_off +
- RTE_ALIGN_CEIL(auth_only_len, 16) - auth_only_len);
- sge->length = sym_op->aead.data.length + auth_only_len;
+ DPAA2_SET_FLE_OFFSET(sge, dst->data_off + sym_op->aead.data.offset);
+ sge->length = sym_op->aead.data.length;
if (sess->dir == DIR_ENC) {
sge++;
DPAA2_SET_FLE_ADDR(sge,
DPAA2_VADDR_TO_IOVA(sym_op->aead.digest.data));
sge->length = sess->digest_length;
- DPAA2_SET_FD_LEN(fd, (sym_op->aead.data.length +
- sess->iv.length + auth_only_len));
}
DPAA2_SET_FLE_FIN(sge);
@@ -566,10 +562,6 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,
sess->digest_length);
DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(old_icv));
sge->length = sess->digest_length;
- DPAA2_SET_FD_LEN(fd, (sym_op->aead.data.length +
-sess->digest_length +
-sess->iv.length +
-auth_only_len));
}
DPAA2_SET_FLE_FIN(sge);
@@ -578,6 +570,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess,
DPAA2_SET_FD_INTERNAL_JD(fd, auth_only_len);
}
+ DPAA2_SET_FD_LEN(fd, fle->length);
return 0;
}
diff --git a/drivers/crypto/dpaa2_sec/hw/desc/algo.h
b/drivers/crypto/dpaa2_sec/hw/desc/algo.h
index 32ce787fa..c41cb2292 100644
--- a/drivers/crypto/dpaa2_sec/hw/desc/algo.h
+++ b/drivers/crypto/dpaa2_sec/hw/desc/algo.h
@@ -649,11 +649,6 @@ cnstr_shdsc_gcm_encap(uint32_t *descbuf, bool ps, bool
swap,
MATHB(p, ZERO, ADD, MATH3, VSEQINSZ, 4, 0);
pzeroassocjump1 = JUMP(p, zeroassocjump1, LOCAL_JUMP, ALL_TRUE, MATH_Z);
- MATHB(p, ZERO, ADD, MATH3, VSEQOUTSZ, 4, 0);
-
- /* skip assoc data */
- SEQFIFOSTORE(p, SKIP, 0, 0, VLF);
-
/* cryptlen = seqinlen - assoclen */
MATHB(p, SEQINSZ, SUB, MATH3, VSEQOUTSZ, 4, 0);
@@ -756,11 +751,6 @@ cnstr_shdsc_gcm_decap(uint32_t *descbuf, bool ps, bool
swap,
MATHB(p, ZERO, ADD, MATH3, VSEQINSZ, 4, 0);
pzeroassocjump1 = JUMP(p, zeroassocjump1, LOCAL_JUMP, ALL_TRUE, MATH_Z);
- MATHB(p, ZERO, ADD, MATH3, VSEQOUTSZ, 4, 0);
-
- /* skip assoc data */
- SEQFIFOSTORE(p, SKIP, 0, 0, VLF);
-
/* read assoc data */
SEQFIFOLOAD(p, AAD1, 0
[dpdk-dev] [PATCH 06/10] test/crypto: increase test cases support for dpaax
Signed-off-by: Hemant Agrawal
---
app/test/test_cryptodev.c | 132 --
1 file changed, 113 insertions(+), 19 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 879b31ceb..c4c730495 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -12294,6 +12294,14 @@ static struct unit_test_suite
cryptodev_dpaa_sec_testsuite = {
test_PDCP_PROTO_SGL_oop_128B_32B),
#endif
/** AES GCM Authenticated Encryption */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encrypt_SGL_in_place_1500B),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encrypt_SGL_out_of_place_400B_400B),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encrypt_SGL_out_of_place_1500B_2000B),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encrypt_SGL_out_of_place_400B_1seg),
TEST_CASE_ST(ut_setup, ut_teardown,
test_AES_GCM_authenticated_encryption_test_case_1),
TEST_CASE_ST(ut_setup, ut_teardown,
@@ -12308,6 +12316,8 @@ static struct unit_test_suite
cryptodev_dpaa_sec_testsuite = {
test_AES_GCM_authenticated_encryption_test_case_6),
TEST_CASE_ST(ut_setup, ut_teardown,
test_AES_GCM_authenticated_encryption_test_case_7),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_encryption_test_case_8),
/** AES GCM Authenticated Decryption */
TEST_CASE_ST(ut_setup, ut_teardown,
@@ -12324,6 +12334,40 @@ static struct unit_test_suite
cryptodev_dpaa_sec_testsuite = {
test_AES_GCM_authenticated_decryption_test_case_6),
TEST_CASE_ST(ut_setup, ut_teardown,
test_AES_GCM_authenticated_decryption_test_case_7),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_authenticated_decryption_test_case_8),
+
+ /** AES GCM Authenticated Encryption 192 bits key */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encryption_test_case_192_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encryption_test_case_192_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encryption_test_case_192_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encryption_test_case_192_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encryption_test_case_192_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encryption_test_case_192_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_encryption_test_case_192_7),
+
+ /** AES GCM Authenticated Decryption 192 bits key */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_decryption_test_case_192_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_decryption_test_case_192_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_decryption_test_case_192_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_decryption_test_case_192_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_decryption_test_case_192_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_decryption_test_case_192_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_AES_GCM_auth_decryption_test_case_192_7),
/** AES GCM Authenticated Encryption 256 bits key */
TEST_CASE_ST(ut_setup, ut_teardown,
@@ -12363,17 +12407,31 @@ static struct unit_test_suite
cryptodev_dpaa_sec_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_AES_GCM_authenticated_decryption_oop_test_case_1),
- /** Scatter-Gather */
+ /** Negative tests */
TEST_CASE_ST(ut_setup, ut_teardown,
- test_AES_GCM_auth_encrypt_SGL_in_place_1500B),
+ test_AES_GCM_auth_encryption_fail_iv_corrupt),
TEST_CASE_ST(ut_setup, ut_teardown,
- test_AES_GCM_auth_encrypt_SGL_out_of_place_400B_400B),
+ test_AES_GCM_auth_encryption_fail_in_data_corrupt),
TEST_CASE_ST(ut_setup, ut_teardown,
- test_AES_GCM_auth_encrypt_SGL_out_of_place_40
