from:"Fan Zhang"

[dpdk-dev] doc: update dependency requirement for some PMDs

2021-06-23 Thread Fan Zhang

This patch updates the dependency requirement information
for aesni-gcm, aesni-mb, snow3g, zuc, and kasumi PMDs. Previously
building these PMDs with Make will fail when the system is
installed inte-ipsec-mb library version 1.0 or newer.

Since Make build system is deprecated already, instead of fixing
the issue the documentation is updated to state it.

Signed-off-by: Fan Zhang 
---
 doc/guides/cryptodevs/aesni_gcm.rst | 3 ++-
 doc/guides/cryptodevs/aesni_mb.rst  | 3 ++-
 doc/guides/cryptodevs/kasumi.rst| 3 ++-
 doc/guides/cryptodevs/snow3g.rst| 3 ++-
 doc/guides/cryptodevs/zuc.rst   | 3 ++-
 5 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/doc/guides/cryptodevs/aesni_gcm.rst 
b/doc/guides/cryptodevs/aesni_gcm.rst
index 19f95bde8e..11b23958d5 100644
--- a/doc/guides/cryptodevs/aesni_gcm.rst
+++ b/doc/guides/cryptodevs/aesni_gcm.rst
@@ -83,9 +83,10 @@ and the external crypto libraries supported by them:
17.02 - 17.05  ISA-L Crypto v2.18
17.08 - 18.02  Multi-buffer library 0.46 - 0.48
18.05 - 19.02  Multi-buffer library 0.49 - 0.52
-   19.05+ Multi-buffer library 0.52 - 1.0
+   19.05+ Multi-buffer library 0.52 - 1.0*
=  
 
+\* Multi-buffer library 1.0 or newer only works for Meson but not Make build 
system.
 
 Initialization
 --
diff --git a/doc/guides/cryptodevs/aesni_mb.rst 
b/doc/guides/cryptodevs/aesni_mb.rst
index 20076b829c..a466d0ab48 100644
--- a/doc/guides/cryptodevs/aesni_mb.rst
+++ b/doc/guides/cryptodevs/aesni_mb.rst
@@ -130,9 +130,10 @@ and the Multi-Buffer library version supported by them:
18.02   0.48
18.05 - 19.02   0.49 - 0.52
19.05 - 19.08   0.52
-   19.11+  0.52 - 1.0
+   19.11+  0.52 - 1.0*
==  
 
+\* Multi-buffer library 1.0 or newer only works for Meson but not Make build 
system.
 
 Initialization
 --
diff --git a/doc/guides/cryptodevs/kasumi.rst b/doc/guides/cryptodevs/kasumi.rst
index 14ecb74241..35c5941317 100644
--- a/doc/guides/cryptodevs/kasumi.rst
+++ b/doc/guides/cryptodevs/kasumi.rst
@@ -78,9 +78,10 @@ and the external crypto libraries supported by them:
DPDK version   Crypto library version
=  
16.11 - 19.11  LibSSO KASUMI
-   20.02+ Multi-buffer library 0.53 - 1.0
+   20.02+ Multi-buffer library 0.53 - 1.0*
=  
 
+\* Multi-buffer library 1.0 or newer only works for Meson but not Make build 
system.
 
 Initialization
 --
diff --git a/doc/guides/cryptodevs/snow3g.rst b/doc/guides/cryptodevs/snow3g.rst
index e318d65d4e..0258b71bb4 100644
--- a/doc/guides/cryptodevs/snow3g.rst
+++ b/doc/guides/cryptodevs/snow3g.rst
@@ -77,9 +77,10 @@ and the external crypto libraries supported by them:
DPDK version   Crypto library version
=  
16.04 - 19.11  LibSSO SNOW3G
-   20.02+ Multi-buffer library 0.53 - 1.0
+   20.02+ Multi-buffer library 0.53 - 1.0*
=  
 
+\* Multi-buffer library 1.0 or newer only works for Meson but not Make build 
system.
 
 Initialization
 --
diff --git a/doc/guides/cryptodevs/zuc.rst b/doc/guides/cryptodevs/zuc.rst
index 94bf71ba90..988a79bc26 100644
--- a/doc/guides/cryptodevs/zuc.rst
+++ b/doc/guides/cryptodevs/zuc.rst
@@ -77,9 +77,10 @@ and the external crypto libraries supported by them:
DPDK version   Crypto library version
=  
16.11 - 19.11  LibSSO ZUC
-   20.02+ Multi-buffer library 0.53 - 1.0
+   20.02+ Multi-buffer library 0.53 - 1.0*
=  
 
+\* Multi-buffer library 1.0 or newer only works for Meson but not Make build 
system.
 
 Initialization
 --
-- 
2.25.1

[PATCH] vhost/crypto: fix out of bound access

2022-07-08 Thread Fan Zhang

Coverity issue: 379211

Fixes: 4414bb67010d ("vhost/crypto: fix build with GCC 12")
Cc: david.march...@redhat.com

Signed-off-by: Fan Zhang 
---
 lib/vhost/vhost_crypto.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/lib/vhost/vhost_crypto.c b/lib/vhost/vhost_crypto.c
index 54946f46d9..e9c3322d20 100644
--- a/lib/vhost/vhost_crypto.c
+++ b/lib/vhost/vhost_crypto.c
@@ -574,12 +574,11 @@ copy_data_from_desc(void *dst, struct 
vhost_crypto_data_req *vc_req,
 
remain = RTE_MIN(desc->len, size);
addr = desc->addr;
-   do {
-   uint64_t len;
-   void *src;
 
-   len = remain;
-   src = IOVA_TO_VVA(void *, vc_req, addr, &len, VHOST_ACCESS_RO);
+while (remain) {
+uint64_t len = remain;
+   void *src = IOVA_TO_VVA(void *, vc_req, addr, &len, 
VHOST_ACCESS_RO);
+
if (unlikely(src == NULL || len == 0))
return 0;
 
@@ -588,7 +587,7 @@ copy_data_from_desc(void *dst, struct vhost_crypto_data_req 
*vc_req,
/* cast is needed for 32-bit architecture */
dst = RTE_PTR_ADD(dst, (size_t)len);
addr += len;
-   } while (unlikely(remain != 0));
+}
 
return RTE_MIN(desc->len, size);
 }
-- 
2.34.1

[PATCH v2] vhost/crypto: fix out of bound access

2022-07-08 Thread Fan Zhang

Coverity issue: 379211

Fixes: 4414bb67010d ("vhost/crypto: fix build with GCC 12")
Cc: david.march...@redhat.com

Signed-off-by: Fan Zhang 
---
v2: 
  fix format-warning

 lib/vhost/vhost_crypto.c | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/lib/vhost/vhost_crypto.c b/lib/vhost/vhost_crypto.c
index 54946f46d9..bf899d2a50 100644
--- a/lib/vhost/vhost_crypto.c
+++ b/lib/vhost/vhost_crypto.c
@@ -574,12 +574,11 @@ copy_data_from_desc(void *dst, struct 
vhost_crypto_data_req *vc_req,
 
remain = RTE_MIN(desc->len, size);
addr = desc->addr;
-   do {
-   uint64_t len;
-   void *src;
 
-   len = remain;
-   src = IOVA_TO_VVA(void *, vc_req, addr, &len, VHOST_ACCESS_RO);
+   while (remain) {
+   uint64_t len = remain;
+   void *src = IOVA_TO_VVA(void *, vc_req, addr, &len, 
VHOST_ACCESS_RO);
+
if (unlikely(src == NULL || len == 0))
return 0;
 
@@ -588,7 +587,7 @@ copy_data_from_desc(void *dst, struct vhost_crypto_data_req 
*vc_req,
/* cast is needed for 32-bit architecture */
dst = RTE_PTR_ADD(dst, (size_t)len);
addr += len;
-   } while (unlikely(remain != 0));
+   }
 
return RTE_MIN(desc->len, size);
 }
-- 
2.34.1

[dpdk-dev] [dpdk-dev v2] cryptodev: change raw data path dequeue API

2021-03-31 Thread Fan Zhang

This patch changes the experimental raw data path dequeue burst API.
Originally the API enforces the user to provide callback function
to get maximum dequeue count. This change gives the user one more
option to pass directly the expected dequeue count.

Signed-off-by: Fan Zhang 
---
 app/test/test_cryptodev.c  |  8 +---
 doc/guides/rel_notes/release_21_05.rst |  3 +++
 drivers/crypto/qat/qat_sym_hw_dp.c | 21 ++---
 lib/librte_cryptodev/rte_cryptodev.c   |  5 +++--
 lib/librte_cryptodev/rte_cryptodev.h   |  8 
 5 files changed, 33 insertions(+), 12 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index f91debc168..a910547423 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -162,12 +162,6 @@ ceil_byte_length(uint32_t num_bits)
return (num_bits >> 3);
 }
 
-static uint32_t
-get_raw_dp_dequeue_count(void *user_data __rte_unused)
-{
-   return 1;
-}
-
 static void
 post_process_raw_dp_op(void *user_data,uint32_t index __rte_unused,
uint8_t is_op_success)
@@ -345,7 +339,7 @@ process_sym_raw_dp_op(uint8_t dev_id, uint16_t qp_id,
n = n_success = 0;
while (count++ < MAX_RAW_DEQUEUE_COUNT && n == 0) {
n = rte_cryptodev_raw_dequeue_burst(ctx,
-   get_raw_dp_dequeue_count, post_process_raw_dp_op,
+   NULL, 1, post_process_raw_dp_op,
(void **)&ret_op, 0, &n_success,
&dequeue_status);
if (dequeue_status < 0) {
diff --git a/doc/guides/rel_notes/release_21_05.rst 
b/doc/guides/rel_notes/release_21_05.rst
index 8e686cc627..943f1596c5 100644
--- a/doc/guides/rel_notes/release_21_05.rst
+++ b/doc/guides/rel_notes/release_21_05.rst
@@ -130,6 +130,9 @@ API Changes
Also, make sure to start the actual text at the margin.
===
 
+* cryptodev: the function ``rte_cryptodev_raw_dequeue_burst`` is added a
+  parameter ``max_nb_to_dequeue`` to give user a more flexible dequeue control.
+
 
 ABI Changes
 ---
diff --git a/drivers/crypto/qat/qat_sym_hw_dp.c 
b/drivers/crypto/qat/qat_sym_hw_dp.c
index 01afb883e3..2f64de44a1 100644
--- a/drivers/crypto/qat/qat_sym_hw_dp.c
+++ b/drivers/crypto/qat/qat_sym_hw_dp.c
@@ -707,6 +707,7 @@ qat_sym_dp_enqueue_chain_jobs(void *qp_data, uint8_t 
*drv_ctx,
 static __rte_always_inline uint32_t
 qat_sym_dp_dequeue_burst(void *qp_data, uint8_t *drv_ctx,
rte_cryptodev_raw_get_dequeue_count_t get_dequeue_count,
+   uint32_t max_nb_to_dequeue,
rte_cryptodev_raw_post_dequeue_t post_dequeue,
void **out_user_data, uint8_t is_user_data_array,
uint32_t *n_success_jobs, int *return_status)
@@ -736,9 +737,23 @@ qat_sym_dp_dequeue_burst(void *qp_data, uint8_t *drv_ctx,
 
resp_opaque = (void *)(uintptr_t)resp->opaque_data;
/* get the dequeue count */
-   n = get_dequeue_count(resp_opaque);
-   if (unlikely(n == 0))
-   return 0;
+   if (get_dequeue_count) {
+   n = get_dequeue_count(resp_opaque);
+   if (unlikely(n == 0))
+   return 0;
+   else if (n > 1) {
+   head = (head + rx_queue->msg_size * (n - 1)) &
+   rx_queue->modulo_mask;
+   resp = (struct icp_qat_fw_comn_resp *)(
+   (uint8_t *)rx_queue->base_addr + head);
+   if (*(uint32_t *)resp == ADF_RING_EMPTY_SIG)
+   return 0;
+   }
+   } else {
+   if (unlikely(max_nb_to_dequeue == 0))
+   return 0;
+   n = max_nb_to_dequeue;
+   }
 
out_user_data[0] = resp_opaque;
status = QAT_SYM_DP_IS_RESP_SUCCESS(resp);
diff --git a/lib/librte_cryptodev/rte_cryptodev.c 
b/lib/librte_cryptodev/rte_cryptodev.c
index 40f55a3cd0..0c16b04f80 100644
--- a/lib/librte_cryptodev/rte_cryptodev.c
+++ b/lib/librte_cryptodev/rte_cryptodev.c
@@ -2232,13 +2232,14 @@ rte_cryptodev_raw_enqueue_done(struct 
rte_crypto_raw_dp_ctx *ctx,
 uint32_t
 rte_cryptodev_raw_dequeue_burst(struct rte_crypto_raw_dp_ctx *ctx,
rte_cryptodev_raw_get_dequeue_count_t get_dequeue_count,
+   uint32_t max_nb_to_dequeue,
rte_cryptodev_raw_post_dequeue_t post_dequeue,
void **out_user_data, uint8_t is_user_data_array,
uint32_t *n_success_jobs, int *status)
 {
return (*ctx->dequeue_burst)(ctx->qp_data, ctx->drv_ctx_data,
-   get_dequeue_count, post_dequeue, out_user_data,
-   is_user_data_array, n_success_jobs, status);
+   get_dequeue_count, max_nb_to_dequeue, post_dequeue,
+   out_user_data, is_user_data_array, n_success_jobs, status);
 }

[PATCH v4] maintainers: update for crypto api/crypto perf/sw crypto pmds using ipsec-mb

2022-01-18 Thread Fan Zhang

Add myself as Crypto API, QAT, SW PMDs based on ipsec-mb,
NULL PMD, and crypto perf test maintainer. Also remove
Declan, Deepak, and John from the maintainers of these
areas.

Signed-off-by: Fan Zhang 
Acked-by: Declan Doherty 
Acked-by: Fiona Trahe 
Acked-by: John Griffin 
Acked-by: Pablo de Lara 
---
v4:
Removed Fan from rte_security maintainer.

 MAINTAINERS | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 18d9edaf88..edf67506e1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -425,7 +425,7 @@ F: doc/guides/sample_app_ug/bbdev_app.rst

 Crypto API
 M: Akhil Goyal 
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/cryptodev/
 F: app/test/test_cryptodev*
@@ -433,7 +433,6 @@ F: examples/l2fwd-crypto/

 Security API
 M: Akhil Goyal 
-M: Declan Doherty 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/security/
 F: doc/guides/prog_guide/rte_security.rst
@@ -1067,9 +1066,7 @@ F: drivers/crypto/scheduler/
 F: doc/guides/cryptodevs/scheduler.rst

 Intel QuickAssist
-M: John Griffin 
-M: Fiona Trahe 
-M: Deepak Kumar Jain 
+M: Fan Zhang 
 F: drivers/crypto/qat/
 F: drivers/common/qat/
 F: doc/guides/cryptodevs/qat.rst
@@ -1129,7 +1126,7 @@ F: doc/guides/cryptodevs/mlx5.rst
 F: doc/guides/cryptodevs/features/mlx5.ini

 Null Crypto
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/null/
 F: doc/guides/cryptodevs/null.rst
 F: doc/guides/cryptodevs/features/null.ini
@@ -1156,7 +1153,7 @@ F: doc/guides/cryptodevs/dpaa2_sec.rst
 F: doc/guides/cryptodevs/features/dpaa2_sec.ini

 OpenSSL
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/openssl/
 F: doc/guides/cryptodevs/openssl.rst
 F: doc/guides/cryptodevs/features/openssl.ini
@@ -1179,7 +1176,7 @@ F: doc/guides/compressdevs/octeontx.rst
 F: doc/guides/compressdevs/features/octeontx.ini

 Intel QuickAssist
-M: Fiona Trahe 
+M: Fan Zhang 
 F: drivers/compress/qat/
 F: drivers/common/qat/

@@ -1709,8 +1706,8 @@ F: app/test-compress-perf/
 F: doc/guides/tools/comp_perf.rst

 Crypto performance test application
-M: Declan Doherty 
 M: Ciara Power 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: app/test-crypto-perf/
 F: doc/guides/tools/cryptoperf.rst
--
2.25.1

[PATCH v5] maintainers: update for crypto api/crypto perf/sw crypto pmds using ipsec-mb

2022-01-24 Thread Fan Zhang

Add myself as Crypto API, QAT, SW PMDs based on ipsec-mb,
NULL PMD, and crypto perf test maintainer. Also remove
Declan, Deepak, and John from the maintainers of these
areas.

Signed-off-by: Fan Zhang 
Acked-by: Declan Doherty 
Acked-by: Fiona Trahe 
Acked-by: John Griffin 
Acked-by: Pablo de Lara 
Acked-by: Akhil Goyal 
---
v5:
Removed Fan from crypto perf maintainer.

v4:
Removed Fan from rte_security maintainer.

 MAINTAINERS | 14 +-
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 18d9edaf88..2ee5f65f83 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -425,7 +425,7 @@ F: doc/guides/sample_app_ug/bbdev_app.rst
 
 Crypto API
 M: Akhil Goyal 
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/cryptodev/
 F: app/test/test_cryptodev*
@@ -433,7 +433,6 @@ F: examples/l2fwd-crypto/
 
 Security API
 M: Akhil Goyal 
-M: Declan Doherty 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/security/
 F: doc/guides/prog_guide/rte_security.rst
@@ -1067,9 +1066,7 @@ F: drivers/crypto/scheduler/
 F: doc/guides/cryptodevs/scheduler.rst
 
 Intel QuickAssist
-M: John Griffin 
-M: Fiona Trahe 
-M: Deepak Kumar Jain 
+M: Fan Zhang 
 F: drivers/crypto/qat/
 F: drivers/common/qat/
 F: doc/guides/cryptodevs/qat.rst
@@ -1129,7 +1126,7 @@ F: doc/guides/cryptodevs/mlx5.rst
 F: doc/guides/cryptodevs/features/mlx5.ini
 
 Null Crypto
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/null/
 F: doc/guides/cryptodevs/null.rst
 F: doc/guides/cryptodevs/features/null.ini
@@ -1156,7 +1153,7 @@ F: doc/guides/cryptodevs/dpaa2_sec.rst
 F: doc/guides/cryptodevs/features/dpaa2_sec.ini
 
 OpenSSL
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/openssl/
 F: doc/guides/cryptodevs/openssl.rst
 F: doc/guides/cryptodevs/features/openssl.ini
@@ -1179,7 +1176,7 @@ F: doc/guides/compressdevs/octeontx.rst
 F: doc/guides/compressdevs/features/octeontx.ini
 
 Intel QuickAssist
-M: Fiona Trahe 
+M: Fan Zhang 
 F: drivers/compress/qat/
 F: drivers/common/qat/
 
@@ -1709,7 +1706,6 @@ F: app/test-compress-perf/
 F: doc/guides/tools/comp_perf.rst
 
 Crypto performance test application
-M: Declan Doherty 
 M: Ciara Power 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: app/test-crypto-perf/
-- 
2.25.1

[dpdk-dev] [dpdk-dev v3 00/10] drivers/qat: isolate implementations of qat generations

2021-10-14 Thread Fan Zhang

This patchset introduces new qat driver structure and updates
existing symmetric crypto qat PMD.

The purpose of the change is to isolate QAT generation specific
implementations from one to another.

It is expected the changes to the specific generation driver
code does minimum impact to other generations' implementations.
Also adding the support to new features or new qat generation
hardware will have zero impact to existing functionalities.

v3:
- removed release note update.
- updated with more unified naming conventions.

v2:
- unified asym and sym data structures for qat.
- more refined per gen code split.

Arek Kusztal (1):
  common/qat: unify naming conventions in qat functions

Fan Zhang (9):
  common/qat: add gen specific data and function
  common/qat: add gen specific device implementation
  common/qat: add gen specific queue pair function
  common/qat: add gen specific queue implementation
  compress/qat: add gen specific data and function
  compress/qat: add gen specific implementation
  crypto/qat: unified device private data structure
  crypto/qat: add gen specific data and function
  crypto/qat: add gen specific implementation

 drivers/common/qat/dev/qat_dev_gen1.c |  255 
 drivers/common/qat/dev/qat_dev_gen2.c |   37 +
 drivers/common/qat/dev/qat_dev_gen3.c |   83 ++
 drivers/common/qat/dev/qat_dev_gen4.c |  305 
 drivers/common/qat/dev/qat_dev_gens.h |   58 +
 drivers/common/qat/meson.build|   15 +-
 .../qat/qat_adf/adf_transport_access_macros.h |2 +
 .../common/qat/qat_adf/icp_qat_hw_gen4_comp.h |  195 +++
 .../qat/qat_adf/icp_qat_hw_gen4_comp_defs.h   |  300 
 drivers/common/qat/qat_common.c   |   41 +-
 drivers/common/qat/qat_common.h   |   21 +-
 drivers/common/qat/qat_device.c   |  204 ++-
 drivers/common/qat/qat_device.h   |   71 +-
 drivers/common/qat/qat_logs.h |6 +-
 drivers/common/qat/qat_qp.c   |  667 -
 drivers/common/qat/qat_qp.h   |  121 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen1.c  |  177 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen2.c  |   30 +
 drivers/compress/qat/dev/qat_comp_pmd_gen3.c  |   30 +
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c  |  213 +++
 drivers/compress/qat/dev/qat_comp_pmd_gens.h  |   30 +
 drivers/compress/qat/qat_comp.c   |  101 +-
 drivers/compress/qat/qat_comp.h   |8 +-
 drivers/compress/qat/qat_comp_pmd.c   |  159 +--
 drivers/compress/qat/qat_comp_pmd.h   |   76 +
 drivers/crypto/qat/README |7 -
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c|   76 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c  |  224 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c  |  164 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c  |  125 ++
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h  |   36 +
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c |  283 
 drivers/crypto/qat/meson.build|   26 -
 drivers/crypto/qat/qat_asym_capabilities.h|   63 -
 drivers/crypto/qat/qat_asym_pmd.c |  294 +---
 drivers/crypto/qat/qat_asym_pmd.h |   56 +-
 drivers/crypto/qat/qat_crypto.c   |  172 +++
 drivers/crypto/qat/qat_crypto.h   |   91 ++
 drivers/crypto/qat/qat_sym_capabilities.h | 1248 -
 drivers/crypto/qat/qat_sym_pmd.c  |  448 +-
 drivers/crypto/qat/qat_sym_pmd.h  |   71 +-
 drivers/crypto/qat/qat_sym_session.c  | 1058 +++---
 42 files changed, 4327 insertions(+), 3320 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen1.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen2.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen3.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen4.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gens.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen1.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen2.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen3.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen4.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gens.h
 delete mode 100644 drivers/crypto/qat/README
 create mode 100644 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
 create mode 100644 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
 delete mode 100644 drivers/crypto/qat/meson.build
 delete mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
 create mode 100644 drivers/c

[dpdk-dev] [dpdk-dev v3 01/10] common/qat: add gen specific data and function

2021-10-14 Thread Fan Zhang

This patch adds the data structure and function prototypes for
different QAT generations.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/qat_common.h | 14 --
 drivers/common/qat/qat_device.c |  4 
 drivers/common/qat/qat_device.h | 23 +++
 3 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index 23715085f4..1889ec4e88 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -15,20 +15,24 @@
 /* Intel(R) QuickAssist Technology device generation is enumerated
  * from one according to the generation of the device
  */
+
 enum qat_device_gen {
-   QAT_GEN1 = 1,
+   QAT_GEN1,
QAT_GEN2,
QAT_GEN3,
-   QAT_GEN4
+   QAT_GEN4,
+   QAT_N_GENS
 };
 
 enum qat_service_type {
-   QAT_SERVICE_ASYMMETRIC = 0,
+   QAT_SERVICE_ASYMMETRIC,
QAT_SERVICE_SYMMETRIC,
QAT_SERVICE_COMPRESSION,
-   QAT_SERVICE_INVALID
+   QAT_MAX_SERVICES
 };
 
+#define QAT_SERVICE_INVALID(QAT_MAX_SERVICES)
+
 enum qat_svc_list {
QAT_SVC_UNUSED = 0,
QAT_SVC_CRYPTO = 1,
@@ -37,8 +41,6 @@ enum qat_svc_list {
QAT_SVC_ASYM = 4,
 };
 
-#define QAT_MAX_SERVICES   (QAT_SERVICE_INVALID)
-
 /**< Common struct for scatter-gather list operations */
 struct qat_flat_buf {
uint32_t len;
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 1b967cbcf7..e6b43c541f 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -13,6 +13,10 @@
 #include "adf_pf2vf_msg.h"
 #include "qat_pf2vf.h"
 
+/* Hardware device information per generation */
+struct qat_gen_hw_data qat_gen_config[QAT_N_GENS];
+struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[QAT_N_GENS];
+
 /* pv2vf data Gen 4*/
 struct qat_pf2vf_dev qat_pf2vf_gen4 = {
.pf2vf_offset = ADF_4XXXIOV_PF2VM_OFFSET,
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 228c057d1e..b8b5c387a3 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -21,6 +21,29 @@
 #define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
 #define MAX_QP_THRESHOLD_SIZE  32
 
+/**
+ * Function prototypes for GENx specific device operations.
+ **/
+typedef int (*qat_dev_reset_ring_pairs_t)
+   (struct qat_pci_device *);
+typedef const struct rte_mem_resource* (*qat_dev_get_transport_bar_t)
+   (struct rte_pci_device *);
+typedef int (*qat_dev_get_misc_bar_t)
+   (struct rte_mem_resource **, struct rte_pci_device *);
+typedef int (*qat_dev_read_config_t)
+   (struct qat_pci_device *);
+typedef int (*qat_dev_get_extra_size_t)(void);
+
+struct qat_dev_hw_spec_funcs {
+   qat_dev_reset_ring_pairs_t  qat_dev_reset_ring_pairs;
+   qat_dev_get_transport_bar_t qat_dev_get_transport_bar;
+   qat_dev_get_misc_bar_t  qat_dev_get_misc_bar;
+   qat_dev_read_config_t   qat_dev_read_config;
+   qat_dev_get_extra_size_tqat_dev_get_extra_size;
+};
+
+extern struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[];
+
 struct qat_dev_cmd_param {
const char *name;
uint16_t val;
-- 
2.25.1

[dpdk-dev] [dpdk-dev v3 02/10] common/qat: add gen specific device implementation

2021-10-14 Thread Fan Zhang

This patch replaces the mixed QAT device configuration
implementation by separate files with shared or
individual implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c |  66 +
 drivers/common/qat/dev/qat_dev_gen2.c |  23 +++
 drivers/common/qat/dev/qat_dev_gen3.c |  23 +++
 drivers/common/qat/dev/qat_dev_gen4.c | 152 +++
 drivers/common/qat/dev/qat_dev_gens.h |  34 +
 drivers/common/qat/meson.build|   4 +
 drivers/common/qat/qat_device.c   | 204 +++---
 drivers/common/qat/qat_device.h   |   5 +-
 drivers/common/qat/qat_qp.c   |   3 +-
 9 files changed, 390 insertions(+), 124 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen1.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen2.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen3.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen4.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gens.h

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
new file mode 100644
index 00..d9e75fe9e2
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+#define ADF_ARB_REG_SLOT   0x1000
+
+int
+qat_reset_ring_pairs_gen1(struct qat_pci_device *qat_pci_dev __rte_unused)
+{
+   /*
+* Ring pairs reset not supported on base, continue
+*/
+   return 0;
+}
+
+const struct rte_mem_resource *
+qat_dev_get_transport_bar_gen1(struct rte_pci_device *pci_dev)
+{
+   return &pci_dev->mem_resource[0];
+}
+
+int
+qat_dev_get_misc_bar_gen1(struct rte_mem_resource **mem_resource __rte_unused,
+   struct rte_pci_device *pci_dev __rte_unused)
+{
+   return -1;
+}
+
+int
+qat_dev_read_config_gen1(struct qat_pci_device *qat_dev __rte_unused)
+{
+   /*
+* Base generations do not have configuration,
+* but set this pointer anyway that we can
+* distinguish higher generations faulty set to NULL
+*/
+   return 0;
+}
+
+int
+qat_dev_get_extra_size_gen1(void)
+{
+   return 0;
+}
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen1 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen1_init)
+{
+   qat_dev_hw_spec[QAT_GEN1] = &qat_dev_hw_spec_gen1;
+   qat_gen_config[QAT_GEN1].dev_gen = QAT_GEN1;
+   qat_gen_config[QAT_GEN1].comp_num_im_bufs_required =
+   QAT_NUM_INTERM_BUFS_GEN1;
+}
diff --git a/drivers/common/qat/dev/qat_dev_gen2.c 
b/drivers/common/qat/dev/qat_dev_gen2.c
new file mode 100644
index 00..d3470ed6b8
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen2.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen2 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen2_init)
+{
+   qat_dev_hw_spec[QAT_GEN2] = &qat_dev_hw_spec_gen2;
+   qat_gen_config[QAT_GEN2].dev_gen = QAT_GEN2;
+}
diff --git a/drivers/common/qat/dev/qat_dev_gen3.c 
b/drivers/common/qat/dev/qat_dev_gen3.c
new file mode 100644
index 00..e4a66869d2
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen3.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen3 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen3_init)
+{
+   qat_dev_hw_spec[QAT_GEN3] = &qat_dev_hw_spec_gen3;
+

[dpdk-dev] [dpdk-dev v3 03/10] common/qat: add gen specific queue pair function

2021-10-14 Thread Fan Zhang

This patch adds the queue pair data structure and function
prototypes for different QAT generations.

Signed-off-by: Fan Zhang 
---
 drivers/common/qat/qat_qp.c |   3 ++
 drivers/common/qat/qat_qp.h | 103 
 2 files changed, 71 insertions(+), 35 deletions(-)

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index b8c6000e86..27994036b8 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -34,6 +34,9 @@
ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
(ADF_ARB_REG_SLOT * index), value)
 
+struct qat_qp_hw_spec_funcs*
+   qat_qp_hw_spec[QAT_N_GENS];
+
 __extension__
 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index e1627197fa..726cd2ef61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -7,8 +7,6 @@
 #include "qat_common.h"
 #include "adf_transport_access_macros.h"
 
-struct qat_pci_device;
-
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */
 
@@ -24,37 +22,7 @@ struct qat_pci_device;
 #define QAT_GEN4_BUNDLE_NUM 4
 #define QAT_GEN4_QPS_PER_BUNDLE_NUM 1
 
-/**
- * Structure with data needed for creation of queue pair.
- */
-struct qat_qp_hw_data {
-   enum qat_service_type service_type;
-   uint8_t hw_bundle_num;
-   uint8_t tx_ring_num;
-   uint8_t rx_ring_num;
-   uint16_t tx_msg_size;
-   uint16_t rx_msg_size;
-};
-
-/**
- * Structure with data needed for creation of queue pair on gen4.
- */
-struct qat_qp_gen4_data {
-   struct qat_qp_hw_data qat_qp_hw_data;
-   uint8_t reserved;
-   uint8_t valid;
-};
-
-/**
- * Structure with data needed for creation of queue pair.
- */
-struct qat_qp_config {
-   const struct qat_qp_hw_data *hw;
-   uint32_t nb_descriptors;
-   uint32_t cookie_size;
-   int socket_id;
-   const char *service_str;
-};
+struct qat_pci_device;
 
 /**
  * Structure associated with each queue.
@@ -96,8 +64,28 @@ struct qat_qp {
uint16_t min_enq_burst_threshold;
 } __rte_cache_aligned;
 
-extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
-extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
+/**
+ * Structure with data needed for creation of queue pair.
+ */
+struct qat_qp_hw_data {
+   enum qat_service_type service_type;
+   uint8_t hw_bundle_num;
+   uint8_t tx_ring_num;
+   uint8_t rx_ring_num;
+   uint16_t tx_msg_size;
+   uint16_t rx_msg_size;
+};
+
+/**
+ * Structure with data needed for creation of queue pair.
+ */
+struct qat_qp_config {
+   const struct qat_qp_hw_data *hw;
+   uint32_t nb_descriptors;
+   uint32_t cookie_size;
+   int socket_id;
+   const char *service_str;
+};
 
 uint16_t
 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
@@ -136,4 +124,49 @@ qat_select_valid_queue(struct qat_pci_device *qat_dev, int 
qp_id,
 int
 qat_read_qp_config(struct qat_pci_device *qat_dev);
 
+/**
+ * Function prototypes for GENx specific queue pair operations.
+ **/
+typedef int (*qat_qp_rings_per_service_t)
+   (struct qat_pci_device *, enum qat_service_type);
+
+typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
+
+typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
+   rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
+   rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
+
+typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue 
*q);
+
+typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
+   uint32_t new_head);
+
+typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
+   struct qat_qp *);
+
+typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
+   struct qat_pci_device *dev, enum qat_service_type service_type,
+   uint16_t qp_id);
+
+struct qat_qp_hw_spec_funcs {
+   qat_qp_rings_per_service_t  qat_qp_rings_per_service;
+   qat_qp_build_ring_base_tqat_qp_build_ring_base;
+   qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable;
+   qat_qp_adf_arb_disable_tqat_qp_adf_arb_disable;
+   qat_qp_adf_configure_queues_t   qat_qp_adf_configure_queues;
+   qat_qp_csr_write_tail_t qat_qp_csr_write_tail;
+   qat_qp_csr_write_head_t qat_qp_csr_write_head;
+   qat_qp_csr_setup_t  qat_qp_csr_setup;
+   qat_qp_get_hw_data_tqat_qp_get_hw_data;
+};
+
+extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
+
+extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];

[dpdk-dev] [dpdk-dev v3 04/10] common/qat: add gen specific queue implementation

2021-10-14 Thread Fan Zhang

This patch replaces the mixed QAT queue pair configuration
implementation by separate files with shared or individual
implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c | 193 -
 drivers/common/qat/dev/qat_dev_gen2.c |  14 +
 drivers/common/qat/dev/qat_dev_gen3.c |  60 ++
 drivers/common/qat/dev/qat_dev_gen4.c | 161 -
 drivers/common/qat/dev/qat_dev_gens.h |  30 +-
 .../qat/qat_adf/adf_transport_access_macros.h |   2 +
 drivers/common/qat/qat_device.h   |   3 -
 drivers/common/qat/qat_qp.c   | 667 +++---
 drivers/common/qat/qat_qp.h   |  24 +-
 drivers/crypto/qat/qat_sym_pmd.c  |  32 +-
 10 files changed, 710 insertions(+), 476 deletions(-)

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
index d9e75fe9e2..f1f43c17b1 100644
--- a/drivers/common/qat/dev/qat_dev_gen1.c
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -3,6 +3,7 @@
  */
 
 #include "qat_device.h"
+#include "qat_qp.h"
 #include "adf_transport_access_macros.h"
 #include "qat_dev_gens.h"
 
@@ -10,6 +11,195 @@
 
 #define ADF_ARB_REG_SLOT   0x1000
 
+#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
+   ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
+   (ADF_ARB_REG_SLOT * index), value)
+
+__extension__
+const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
+[ADF_MAX_QPS_ON_ANY_SERVICE] = {
+   /* queue pairs which provide an asymmetric crypto service */
+   [QAT_SERVICE_ASYMMETRIC] = {
+   {
+   .service_type = QAT_SERVICE_ASYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 0,
+   .rx_ring_num = 8,
+   .tx_msg_size = 64,
+   .rx_msg_size = 32,
+
+   }, {
+   .service_type = QAT_SERVICE_ASYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 1,
+   .rx_ring_num = 9,
+   .tx_msg_size = 64,
+   .rx_msg_size = 32,
+   }
+   },
+   /* queue pairs which provide a symmetric crypto service */
+   [QAT_SERVICE_SYMMETRIC] = {
+   {
+   .service_type = QAT_SERVICE_SYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 2,
+   .rx_ring_num = 10,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   },
+   {
+   .service_type = QAT_SERVICE_SYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 3,
+   .rx_ring_num = 11,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }
+   },
+   /* queue pairs which provide a compression service */
+   [QAT_SERVICE_COMPRESSION] = {
+   {
+   .service_type = QAT_SERVICE_COMPRESSION,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 6,
+   .rx_ring_num = 14,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }, {
+   .service_type = QAT_SERVICE_COMPRESSION,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 7,
+   .rx_ring_num = 15,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }
+   }
+};
+
+const struct qat_qp_hw_data *
+qat_qp_get_hw_data_gen1(struct qat_pci_device *dev __rte_unused,
+   enum qat_service_type service_type, uint16_t qp_id)
+{
+   return qat_gen1_qps[service_type] + qp_id;
+}
+
+int
+qat_qp_rings_per_service_gen1(struct qat_pci_device *qat_dev,
+   enum qat_service_type service)
+{
+   int i = 0, count = 0;
+
+   for (i = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++) {
+   const struct qat_qp_hw_data *hw_qps =
+   qat_qp_get_hw_data(qat_dev, service, i);
+   if (hw_qps->service_type == service)
+   count++;
+   }
+
+   return count;
+}
+
+void
+qat_qp_csr_build_ring_base_gen1(void *io_addr,
+   struct qat_queue *queue)
+{
+   uint64_t queue_base;
+
+   queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
+   queue->queue_size);
+   WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
+   queue->hw_queue_number, queue_base);
+}
+
+void
+qat_qp_adf_arb_enable_gen1(const stru

[dpdk-dev] [dpdk-dev v3 05/10] compress/qat: add gen specific data and function

2021-10-14 Thread Fan Zhang

This patch adds the compression data structure and function
prototypes for different QAT generations.

Signed-off-by: Adam Dybkowski 
Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c |   2 -
 .../common/qat/qat_adf/icp_qat_hw_gen4_comp.h | 195 
 .../qat/qat_adf/icp_qat_hw_gen4_comp_defs.h   | 300 ++
 drivers/common/qat/qat_device.h   |   7 -
 drivers/compress/qat/qat_comp.c   | 101 +++---
 drivers/compress/qat/qat_comp.h   |   8 +-
 drivers/compress/qat/qat_comp_pmd.c   | 159 --
 drivers/compress/qat/qat_comp_pmd.h   |  76 +
 8 files changed, 674 insertions(+), 174 deletions(-)
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
index f1f43c17b1..ed4c4a2c03 100644
--- a/drivers/common/qat/dev/qat_dev_gen1.c
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -252,6 +252,4 @@ RTE_INIT(qat_dev_gen_gen1_init)
qat_qp_hw_spec[QAT_GEN1] = &qat_qp_hw_spec_gen1;
qat_dev_hw_spec[QAT_GEN1] = &qat_dev_hw_spec_gen1;
qat_gen_config[QAT_GEN1].dev_gen = QAT_GEN1;
-   qat_gen_config[QAT_GEN1].comp_num_im_bufs_required =
-   QAT_NUM_INTERM_BUFS_GEN1;
 }
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h 
b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
new file mode 100644
index 00..ec69dc7105
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#ifndef _ICP_QAT_HW_GEN4_COMP_H_
+#define _ICP_QAT_HW_GEN4_COMP_H_
+
+#include "icp_qat_fw.h"
+#include "icp_qat_hw_gen4_comp_defs.h"
+
+struct icp_qat_hw_comp_20_config_csr_lower {
+   icp_qat_hw_comp_20_extended_delay_match_mode_t edmm;
+   icp_qat_hw_comp_20_hw_comp_format_t algo;
+   icp_qat_hw_comp_20_search_depth_t sd;
+   icp_qat_hw_comp_20_hbs_control_t hbs;
+   icp_qat_hw_comp_20_abd_t abd;
+   icp_qat_hw_comp_20_lllbd_ctrl_t lllbd;
+   icp_qat_hw_comp_20_min_match_control_t mmctrl;
+   icp_qat_hw_comp_20_skip_hash_collision_t hash_col;
+   icp_qat_hw_comp_20_skip_hash_update_t hash_update;
+   icp_qat_hw_comp_20_byte_skip_t skip_ctrl;
+};
+
+static inline uint32_t ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(
+   struct icp_qat_hw_comp_20_config_csr_lower csr)
+{
+   uint32_t val32 = 0;
+
+   QAT_FIELD_SET(val32, csr.algo,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
+
+   QAT_FIELD_SET(val32, csr.sd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
+
+   QAT_FIELD_SET(val32, csr.edmm,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
+
+   QAT_FIELD_SET(val32, csr.hbs,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
+
+   QAT_FIELD_SET(val32, csr.lllbd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
+
+   QAT_FIELD_SET(val32, csr.mmctrl,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
+
+   QAT_FIELD_SET(val32, csr.hash_col,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
+
+   QAT_FIELD_SET(val32, csr.hash_update,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
+
+   QAT_FIELD_SET(val32, csr.skip_ctrl,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
+
+   QAT_FIELD_SET(val32, csr.abd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
+
+   QAT_FIELD_SET(val32, csr.lllbd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
+
+   return rte_bswap32(val32);
+}
+
+struct icp_qat_hw_comp_20_config_csr_upper {
+   icp_qat_hw_comp_20_scb_control_t scb_ctrl;
+   icp_qat_hw_comp_20_rmb_control_t rmb_ctrl;
+   icp_qat_hw_comp_20_som_control_t som_ctrl;
+   icp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl;
+   icp_qat_hw_comp_20_scb_unlo

[dpdk-dev] [dpdk-dev v3 06/10] compress/qat: add gen specific implementation

2021-10-14 Thread Fan Zhang

This patch replaces the mixed QAT compression support
implementation by separate files with shared or individual
implementation for specific QAT generation.

Signed-off-by: Adam Dybkowski 
Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   4 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen1.c | 177 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen2.c |  30 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen3.c |  30 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 213 +++
 drivers/compress/qat/dev/qat_comp_pmd_gens.h |  30 +++
 6 files changed, 483 insertions(+), 1 deletion(-)
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen1.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen2.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen3.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen4.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gens.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 532e0fabb3..8a1c6d64e8 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -62,7 +62,9 @@ includes += include_directories(
 )
 
 if qat_compress
-foreach f: ['qat_comp_pmd.c', 'qat_comp.c']
+foreach f: ['qat_comp_pmd.c', 'qat_comp.c',
+'dev/qat_comp_pmd_gen1.c', 'dev/qat_comp_pmd_gen2.c',
+'dev/qat_comp_pmd_gen3.c', 'dev/qat_comp_pmd_gen4.c']
 sources += files(join_paths(qat_compress_relpath, f))
 endforeach
 endif
diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen1.c 
b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c
new file mode 100644
index 00..0e1afe544a
--- /dev/null
+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include "qat_comp_pmd.h"
+#include "qat_comp.h"
+#include "qat_comp_pmd_gens.h"
+
+#define QAT_NUM_INTERM_BUFS_GEN1 12
+
+const struct rte_compressdev_capabilities qat_gen1_comp_capabilities[] = {
+   {/* COMPRESSION - deflate */
+.algo = RTE_COMP_ALGO_DEFLATE,
+.comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+   RTE_COMP_FF_CRC32_CHECKSUM |
+   RTE_COMP_FF_ADLER32_CHECKSUM |
+   RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+   RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+   RTE_COMP_FF_HUFFMAN_FIXED |
+   RTE_COMP_FF_HUFFMAN_DYNAMIC |
+   RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
+   RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
+   RTE_COMP_FF_OOP_LB_IN_SGL_OUT |
+   RTE_COMP_FF_STATEFUL_DECOMPRESSION,
+.window_size = {.min = 15, .max = 15, .increment = 0} },
+   {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
+static int
+qat_comp_dev_config_gen1(struct rte_compressdev *dev,
+   struct rte_compressdev_config *config)
+{
+   struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+   if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+   QAT_LOG(WARNING,
+   "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+   " QAT device can't be used for Dynamic Deflate. "
+   "Did you really intend to do this?");
+   } else {
+   comp_dev->interm_buff_mz =
+   qat_comp_setup_inter_buffers(comp_dev,
+   RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+   if (comp_dev->interm_buff_mz == NULL)
+   return -ENOMEM;
+   }
+
+   return qat_comp_dev_config(dev, config);
+}
+
+struct rte_compressdev_ops qat_comp_ops_gen1 = {
+
+   /* Device related operations */
+   .dev_configure  = qat_comp_dev_config_gen1,
+   .dev_start  = qat_comp_dev_start,
+   .dev_stop   = qat_comp_dev_stop,
+   .dev_close  = qat_comp_dev_close,
+   .dev_infos_get  = qat_comp_dev_info_get,
+
+   .stats_get  = qat_comp_stats_get,
+   .stats_reset= qat_comp_stats_reset,
+   .queue_pair_setup   = qat_comp_qp_setup,
+   .queue_pair_release = qat_comp_qp_release,
+
+   /* Compression related operations */
+   .private_xform_create   = qat_comp_private_xform_create,
+   .private_xform_free = qat_comp_private_xform_free,
+   .stream_create  = qat_comp_stream_create,
+   .stream_free= qat_comp_stream_free
+};
+
+struct qat_comp_capabilit

[dpdk-dev] [dpdk-dev v3 07/10] crypto/qat: unified device private data structure

2021-10-14 Thread Fan Zhang

This patch unifies the QAT symmetric and asymmetric device
private data structures and functions.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   2 +-
 drivers/common/qat/qat_common.c  |  15 ++
 drivers/common/qat/qat_common.h  |   3 +
 drivers/common/qat/qat_device.h  |   7 +-
 drivers/crypto/qat/qat_asym_pmd.c| 216 ---
 drivers/crypto/qat/qat_asym_pmd.h|  29 +---
 drivers/crypto/qat/qat_crypto.c  | 172 ++
 drivers/crypto/qat/qat_crypto.h  |  78 +
 drivers/crypto/qat/qat_sym_pmd.c | 250 +--
 drivers/crypto/qat/qat_sym_pmd.h |  21 +--
 drivers/crypto/qat/qat_sym_session.c |  15 +-
 11 files changed, 361 insertions(+), 447 deletions(-)
 create mode 100644 drivers/crypto/qat/qat_crypto.c
 create mode 100644 drivers/crypto/qat/qat_crypto.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 8a1c6d64e8..29fd0168ea 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -71,7 +71,7 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c']
+'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']
 sources += files(join_paths(qat_crypto_relpath, f))
 endforeach
 deps += ['security']
diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c
index 5343a1451e..59e7e02622 100644
--- a/drivers/common/qat/qat_common.c
+++ b/drivers/common/qat/qat_common.c
@@ -6,6 +6,21 @@
 #include "qat_device.h"
 #include "qat_logs.h"
 
+const char *
+qat_service_get_str(enum qat_service_type type)
+{
+   switch (type) {
+   case QAT_SERVICE_SYMMETRIC:
+   return "sym";
+   case QAT_SERVICE_ASYMMETRIC:
+   return "asym";
+   case QAT_SERVICE_COMPRESSION:
+   return "comp";
+   default:
+   return "invalid";
+   }
+}
+
 int
 qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,
void *list_in, uint32_t data_len,
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index 1889ec4e88..0d488c9611 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -91,4 +91,7 @@ void
 qat_stats_reset(struct qat_pci_device *dev,
enum qat_service_type service);
 
+const char *
+qat_service_get_str(enum qat_service_type type);
+
 #endif /* _QAT_COMMON_H_ */
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index e7c7e9af95..85fae7b7c7 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -76,8 +76,7 @@ struct qat_device_info {
 
 extern struct qat_device_info qat_pci_devs[];
 
-struct qat_sym_dev_private;
-struct qat_asym_dev_private;
+struct qat_cryptodev_private;
 struct qat_comp_dev_private;
 
 /*
@@ -106,14 +105,14 @@ struct qat_pci_device {
/**< links to qps set up for each service, index same as on API */
 
/* Data relating to symmetric crypto service */
-   struct qat_sym_dev_private *sym_dev;
+   struct qat_cryptodev_private *sym_dev;
/**< link back to cryptodev private data */
 
int qat_sym_driver_id;
/**< Symmetric driver id used by this device */
 
/* Data relating to asymmetric crypto service */
-   struct qat_asym_dev_private *asym_dev;
+   struct qat_cryptodev_private *asym_dev;
/**< link back to cryptodev private data */
 
int qat_asym_driver_id;
diff --git a/drivers/crypto/qat/qat_asym_pmd.c 
b/drivers/crypto/qat/qat_asym_pmd.c
index e91bb0d317..b03d8acbac 100644
--- a/drivers/crypto/qat/qat_asym_pmd.c
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -6,6 +6,7 @@
 
 #include "qat_logs.h"
 
+#include "qat_crypto.h"
 #include "qat_asym.h"
 #include "qat_asym_pmd.h"
 #include "qat_sym_capabilities.h"
@@ -18,190 +19,45 @@ static const struct rte_cryptodev_capabilities 
qat_gen1_asym_capabilities[] = {
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-static int qat_asym_qp_release(struct rte_cryptodev *dev,
-  uint16_t queue_pair_id);
-
-static int qat_asym_dev_config(__rte_unused struct rte_cryptodev *dev,
-  __rte_unused struct rte_cryptodev_config *config)
-{
-   return 0;
-}
-
-static int qat_asym_dev_start(__rte_unused struct rte_cryptodev *dev)
-{
-   return 0;
-}
-
-static void qat_asym_dev_stop(__rte_unused struct rte_cryptodev *dev)
-{
-
-}
-
-static int qat_asym_dev_close(struct rte_cryptodev *dev)
-{
-   int i, ret;
-
-   for (i = 0

[dpdk-dev] [dpdk-dev v3 08/10] crypto/qat: add gen specific data and function

2021-10-14 Thread Fan Zhang

This patch adds the symmetric and asymmetric crypto data
structure and function prototypes for different QAT
generations.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/crypto/qat/README  |7 -
 drivers/crypto/qat/meson.build |   26 -
 drivers/crypto/qat/qat_asym_capabilities.h |   63 -
 drivers/crypto/qat/qat_asym_pmd.c  |   60 +-
 drivers/crypto/qat/qat_asym_pmd.h  |   25 +
 drivers/crypto/qat/qat_crypto.h|   16 +
 drivers/crypto/qat/qat_sym_capabilities.h  | 1248 
 drivers/crypto/qat/qat_sym_pmd.c   |  186 +--
 drivers/crypto/qat/qat_sym_pmd.h   |   52 +-
 9 files changed, 160 insertions(+), 1523 deletions(-)
 delete mode 100644 drivers/crypto/qat/README
 delete mode 100644 drivers/crypto/qat/meson.build
 delete mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
 delete mode 100644 drivers/crypto/qat/qat_sym_capabilities.h

diff --git a/drivers/crypto/qat/README b/drivers/crypto/qat/README
deleted file mode 100644
index 444ae605f0..00
--- a/drivers/crypto/qat/README
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2015-2018 Intel Corporation
-
-Makefile for crypto QAT PMD is in common/qat directory.
-The build for the QAT driver is done from there as only one library is built 
for the
-whole QAT pci device and that library includes all the services (crypto, 
compression)
-which are enabled on the device.
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
deleted file mode 100644
index b3b2d17258..00
--- a/drivers/crypto/qat/meson.build
+++ /dev/null
@@ -1,26 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017-2018 Intel Corporation
-
-# this does not build the QAT driver, instead that is done in the compression
-# driver which comes later. Here we just add our sources files to the list
-build = false
-reason = '' # sentinal value to suppress printout
-dep = dependency('libcrypto', required: false, method: 'pkg-config')
-qat_includes += include_directories('.')
-qat_deps += 'cryptodev'
-qat_deps += 'net'
-qat_deps += 'security'
-if dep.found()
-# Add our sources files to the list
-qat_sources += files(
-'qat_asym.c',
-'qat_asym_pmd.c',
-'qat_sym.c',
-'qat_sym_hw_dp.c',
-'qat_sym_pmd.c',
-'qat_sym_session.c',
-   )
-qat_ext_deps += dep
-qat_cflags += '-DBUILD_QAT_SYM'
-qat_cflags += '-DBUILD_QAT_ASYM'
-endif
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h 
b/drivers/crypto/qat/qat_asym_capabilities.h
deleted file mode 100644
index 523b4da6d3..00
--- a/drivers/crypto/qat/qat_asym_capabilities.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019 Intel Corporation
- */
-
-#ifndef _QAT_ASYM_CAPABILITIES_H_
-#define _QAT_ASYM_CAPABILITIES_H_
-
-#define QAT_BASE_GEN1_ASYM_CAPABILITIES
\
-   {   /* modexp */
\
-   .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
\
-   {.asym = {  
\
-   .xform_capa = { 
\
-   .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,  
\
-   .op_types = 0,  
\
-   {   
\
-   .modlen = { 
\
-   .min = 1,   
\
-   .max = 512, 
\
-   .increment = 1  
\
-   }, }
\
-   }   
\
-   },  
\
-   }   
\
-   },  
\
-   {   /* modinv */
\
-   .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
\
-   {.asym = {  
\
-   .xform_capa = {

[dpdk-dev] [dpdk-dev v3 09/10] crypto/qat: add gen specific implementation

2021-10-14 Thread Fan Zhang

This patch replaces the mixed QAT symmetric and asymmetric
support implementation by separate files with shared or
individual implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   7 +-
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   |  76 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 224 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 164 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 125 
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  36 +++
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 283 +++
 drivers/crypto/qat/qat_asym_pmd.h|   1 +
 drivers/crypto/qat/qat_crypto.h  |   3 -
 9 files changed, 915 insertions(+), 4 deletions(-)
 create mode 100644 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
 create mode 100644 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 29fd0168ea..ce9959d103 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -71,7 +71,12 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']
+'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',
+   'dev/qat_sym_pmd_gen1.c',
+'dev/qat_asym_pmd_gen1.c',
+'dev/qat_crypto_pmd_gen2.c',
+'dev/qat_crypto_pmd_gen3.c',
+'dev/qat_crypto_pmd_gen4.c']
 sources += files(join_paths(qat_crypto_relpath, f))
 endforeach
 deps += ['security']
diff --git a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c 
b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
new file mode 100644
index 00..61250fe433
--- /dev/null
+++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017-2021 Intel Corporation
+ */
+
+#include 
+#include 
+#include "qat_asym.h"
+#include "qat_crypto.h"
+#include "qat_crypto_pmd_gens.h"
+#include "qat_pke_functionality_arrays.h"
+
+struct rte_cryptodev_ops qat_asym_crypto_ops_gen1 = {
+   /* Device related operations */
+   .dev_configure  = qat_cryptodev_config,
+   .dev_start  = qat_cryptodev_start,
+   .dev_stop   = qat_cryptodev_stop,
+   .dev_close  = qat_cryptodev_close,
+   .dev_infos_get  = qat_cryptodev_info_get,
+
+   .stats_get  = qat_cryptodev_stats_get,
+   .stats_reset= qat_cryptodev_stats_reset,
+   .queue_pair_setup   = qat_cryptodev_qp_setup,
+   .queue_pair_release = qat_cryptodev_qp_release,
+
+   /* Crypto related operations */
+   .asym_session_get_size  = qat_asym_session_get_private_size,
+   .asym_session_configure = qat_asym_session_configure,
+   .asym_session_clear = qat_asym_session_clear
+};
+
+static struct rte_cryptodev_capabilities qat_asym_crypto_caps_gen1[] = {
+   QAT_ASYM_CAP(MODEX, \
+   0, 1, 512, 1), \
+   QAT_ASYM_CAP(MODINV, \
+   0, 1, 512, 1), \
+   QAT_ASYM_CAP(RSA, \
+   ((1 << RTE_CRYPTO_ASYM_OP_SIGN) | \
+   (1 << RTE_CRYPTO_ASYM_OP_VERIFY) | \
+   (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) | \
+   (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)), \
+   64, 512, 64),
+   RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+
+struct qat_capabilities_info
+qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)
+{
+   struct qat_capabilities_info capa_info;
+   capa_info.data = qat_asym_crypto_caps_gen1;
+   capa_info.size = sizeof(qat_asym_crypto_caps_gen1);
+   return capa_info;
+}
+
+uint64_t
+qat_asym_crypto_feature_flags_get_gen1(
+   struct qat_pci_device *qat_dev __rte_unused)
+{
+   uint64_t feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+   RTE_CRYPTODEV_FF_HW_ACCELERATED |
+   RTE_CRYPTODEV_FF_ASYM_SESSIONLESS |
+   RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_EXP |
+   RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
+
+   return feature_flags;
+}
+
+RTE_INIT(qat_asym_crypto_gen1_init)
+{
+   qat_asym_gen_dev_ops[QAT_GEN1].c

[dpdk-dev] [dpdk-dev v3 10/10] common/qat: unify naming conventions in qat functions

2021-10-14 Thread Fan Zhang

From: Arek Kusztal 

This patch unifies naming conventions across QAT PMD
files. It will help maintaining code and further
development.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/qat_common.c  |   30 +-
 drivers/common/qat/qat_common.h  |4 +-
 drivers/common/qat/qat_device.h  |   76 +-
 drivers/common/qat/qat_logs.h|6 +-
 drivers/crypto/qat/qat_asym_pmd.c|   28 +-
 drivers/crypto/qat/qat_asym_pmd.h|7 +-
 drivers/crypto/qat/qat_crypto.c  |   52 +-
 drivers/crypto/qat/qat_sym_pmd.c |   28 +-
 drivers/crypto/qat/qat_sym_session.c | 1057 +-
 9 files changed, 643 insertions(+), 645 deletions(-)

diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c
index 59e7e02622..774becee2e 100644
--- a/drivers/common/qat/qat_common.c
+++ b/drivers/common/qat/qat_common.c
@@ -7,9 +7,9 @@
 #include "qat_logs.h"
 
 const char *
-qat_service_get_str(enum qat_service_type type)
+qat_service_get_str(enum qat_service_type qat_service)
 {
-   switch (type) {
+   switch (qat_service) {
case QAT_SERVICE_SYMMETRIC:
return "sym";
case QAT_SERVICE_ASYMMETRIC:
@@ -84,24 +84,24 @@ qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,
return res;
 }
 
-void qat_stats_get(struct qat_pci_device *dev,
+void qat_stats_get(struct qat_pci_device *qat_dev,
struct qat_common_stats *stats,
-   enum qat_service_type service)
+   enum qat_service_type qat_service)
 {
int i;
struct qat_qp **qp;
 
-   if (stats == NULL || dev == NULL || service >= QAT_SERVICE_INVALID) {
+   if (stats == NULL || qat_dev == NULL || qat_service >= 
QAT_SERVICE_INVALID) {
QAT_LOG(ERR, "invalid param: stats %p, dev %p, service %d",
-   stats, dev, service);
+   stats, qat_dev, qat_service);
return;
}
 
-   qp = dev->qps_in_use[service];
+   qp = qat_dev->qps_in_use[qat_service];
for (i = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++) {
if (qp[i] == NULL) {
QAT_LOG(DEBUG, "Service %d Uninitialised qp %d",
-   service, i);
+   qat_service, i);
continue;
}
 
@@ -115,27 +115,27 @@ void qat_stats_get(struct qat_pci_device *dev,
}
 }
 
-void qat_stats_reset(struct qat_pci_device *dev,
-   enum qat_service_type service)
+void qat_stats_reset(struct qat_pci_device *qat_dev,
+   enum qat_service_type qat_service)
 {
int i;
struct qat_qp **qp;
 
-   if (dev == NULL || service >= QAT_SERVICE_INVALID) {
+   if (qat_dev == NULL || qat_service >= QAT_SERVICE_INVALID) {
QAT_LOG(ERR, "invalid param: dev %p, service %d",
-   dev, service);
+   qat_dev, qat_service);
return;
}
 
-   qp = dev->qps_in_use[service];
+   qp = qat_dev->qps_in_use[qat_service];
for (i = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++) {
if (qp[i] == NULL) {
QAT_LOG(DEBUG, "Service %d Uninitialised qp %d",
-   service, i);
+   qat_service, i);
continue;
}
memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
}
 
-   QAT_LOG(DEBUG, "QAT: %d stats cleared", service);
+   QAT_LOG(DEBUG, "QAT: %d stats cleared", qat_service);
 }
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index 0d488c9611..92cc584c67 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -84,11 +84,11 @@ qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,
void *list_in, uint32_t data_len,
const uint16_t max_segs);
 void
-qat_stats_get(struct qat_pci_device *dev,
+qat_stats_get(struct qat_pci_device *qat_dev,
struct qat_common_stats *stats,
enum qat_service_type service);
 void
-qat_stats_reset(struct qat_pci_device *dev,
+qat_stats_reset(struct qat_pci_device *qat_dev,
enum qat_service_type service);
 
 const char *
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 85fae7b7c7..9cd2236fb7 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -21,33 +21,8 @@
 #define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
 #define MAX_QP_THRESHOLD_SIZE  32
 
-/**
- * Function prototypes for GENx specific device operations.
- **/
-typedef int (*qat_dev_re

[PATCH] vhost/crypto: fix failed compile

2022-05-19 Thread Fan Zhang

Fixes: 3c79609fda7c ("vhost/crypto: handle virtually non-contiguous buffers")
Cc: roy.fan.zh...@intel.com

This patch fixes the vhost crypto compile file on GCC12.
Ref. https://bugs.dpdk.org/show_bug.cgi?id=1011

The fix involves replacing rte_memcpy to memcpy.

Signed-off-by: Fan Zhang 
---
 lib/vhost/vhost_crypto.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/vhost/vhost_crypto.c b/lib/vhost/vhost_crypto.c
index b1c0eb6a0f..278f990280 100644
--- a/lib/vhost/vhost_crypto.c
+++ b/lib/vhost/vhost_crypto.c
@@ -585,7 +585,7 @@ copy_data(void *dst_data, struct vhost_crypto_data_req 
*vc_req,
if (unlikely(!src || !dlen))
return -1;
 
-   rte_memcpy((uint8_t *)data, src, dlen);
+   memcpy((uint8_t *)data, src, dlen);
data += dlen;
 
if (unlikely(dlen < to_copy)) {
-- 
2.34.1

[dpdk-dev] [dpdk-dev v4 0/9] drivers/qat: isolate implementations of qat generations

2021-10-22 Thread Fan Zhang

This patchset introduces new qat driver structure and updates
existing symmetric crypto qat PMD.

The purpose of the change is to isolate QAT generation specific
implementations from one to another.

It is expected the changes to the specific generation driver
code does minimum impact to other generations' implementations.
Also adding the support to new features or new qat generation
hardware will have zero impact to existing functionalities.

v4:
- rebased on top of latest master.
- updated comments.
- removed naming convention patch.

v3:
- removed release note update.
- updated with more unified naming conventions.

v2:
- unified asym and sym data structures for qat.
- more refined per gen code split.

Fan Zhang (9):
  common/qat: add gen specific data and function
  common/qat: add gen specific device implementation
  common/qat: add gen specific queue pair function
  common/qat: add gen specific queue implementation
  compress/qat: add gen specific data and function
  compress/qat: add gen specific implementation
  crypto/qat: unified device private data structure
  crypto/qat: add gen specific data and function
  crypto/qat: add gen specific implementation

 drivers/common/qat/dev/qat_dev_gen1.c |  254 
 drivers/common/qat/dev/qat_dev_gen2.c |   37 +
 drivers/common/qat/dev/qat_dev_gen3.c |   83 ++
 drivers/common/qat/dev/qat_dev_gen4.c |  305 
 drivers/common/qat/dev/qat_dev_gens.h |   65 +
 drivers/common/qat/meson.build|   15 +-
 .../qat/qat_adf/adf_transport_access_macros.h |2 +
 .../common/qat/qat_adf/icp_qat_hw_gen4_comp.h |  195 +++
 .../qat/qat_adf/icp_qat_hw_gen4_comp_defs.h   |  299 
 drivers/common/qat/qat_common.c   |   15 +
 drivers/common/qat/qat_common.h   |   19 +-
 drivers/common/qat/qat_device.c   |  205 ++-
 drivers/common/qat/qat_device.h   |   45 +-
 drivers/common/qat/qat_qp.c   |  677 -
 drivers/common/qat/qat_qp.h   |  121 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen1.c  |  175 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen2.c  |   30 +
 drivers/compress/qat/dev/qat_comp_pmd_gen3.c  |   30 +
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c  |  213 +++
 drivers/compress/qat/dev/qat_comp_pmd_gens.h  |   30 +
 drivers/compress/qat/qat_comp.c   |  101 +-
 drivers/compress/qat/qat_comp.h   |8 +-
 drivers/compress/qat/qat_comp_pmd.c   |  159 +--
 drivers/compress/qat/qat_comp_pmd.h   |   76 +
 drivers/crypto/qat/README |7 -
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c|   76 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c  |  224 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c  |  164 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c  |  124 ++
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h  |   36 +
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c |  283 
 drivers/crypto/qat/meson.build|   26 -
 drivers/crypto/qat/qat_asym_capabilities.h|   63 -
 drivers/crypto/qat/qat_asym_pmd.c |  276 +---
 drivers/crypto/qat/qat_asym_pmd.h |   54 +-
 drivers/crypto/qat/qat_crypto.c   |  172 +++
 drivers/crypto/qat/qat_crypto.h   |   91 ++
 drivers/crypto/qat/qat_sym_capabilities.h | 1248 -
 drivers/crypto/qat/qat_sym_pmd.c  |  428 +-
 drivers/crypto/qat/qat_sym_pmd.h  |   76 +-
 drivers/crypto/qat/qat_sym_session.c  |   15 +-
 41 files changed, 3772 insertions(+), 2750 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen1.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen2.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen3.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen4.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gens.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen1.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen2.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen3.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen4.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gens.h
 delete mode 100644 drivers/crypto/qat/README
 create mode 100644 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
 create mode 100644 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
 delete mode 100644 drivers/crypto/qat/meson.build
 delete mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
 create mode 100644 drivers/crypto/qat/qat_crypto.c
 create mode 100644 drivers/c

[dpdk-dev] [dpdk-dev v4 1/9] common/qat: add gen specific data and function

2021-10-22 Thread Fan Zhang

This patch adds the data structure and function prototypes for
different QAT generations.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/qat_common.h | 14 --
 drivers/common/qat/qat_device.c |  4 
 drivers/common/qat/qat_device.h | 23 +++
 3 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index 23715085f4..1889ec4e88 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -15,20 +15,24 @@
 /* Intel(R) QuickAssist Technology device generation is enumerated
  * from one according to the generation of the device
  */
+
 enum qat_device_gen {
-   QAT_GEN1 = 1,
+   QAT_GEN1,
QAT_GEN2,
QAT_GEN3,
-   QAT_GEN4
+   QAT_GEN4,
+   QAT_N_GENS
 };
 
 enum qat_service_type {
-   QAT_SERVICE_ASYMMETRIC = 0,
+   QAT_SERVICE_ASYMMETRIC,
QAT_SERVICE_SYMMETRIC,
QAT_SERVICE_COMPRESSION,
-   QAT_SERVICE_INVALID
+   QAT_MAX_SERVICES
 };
 
+#define QAT_SERVICE_INVALID(QAT_MAX_SERVICES)
+
 enum qat_svc_list {
QAT_SVC_UNUSED = 0,
QAT_SVC_CRYPTO = 1,
@@ -37,8 +41,6 @@ enum qat_svc_list {
QAT_SVC_ASYM = 4,
 };
 
-#define QAT_MAX_SERVICES   (QAT_SERVICE_INVALID)
-
 /**< Common struct for scatter-gather list operations */
 struct qat_flat_buf {
uint32_t len;
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 1b967cbcf7..e6b43c541f 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -13,6 +13,10 @@
 #include "adf_pf2vf_msg.h"
 #include "qat_pf2vf.h"
 
+/* Hardware device information per generation */
+struct qat_gen_hw_data qat_gen_config[QAT_N_GENS];
+struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[QAT_N_GENS];
+
 /* pv2vf data Gen 4*/
 struct qat_pf2vf_dev qat_pf2vf_gen4 = {
.pf2vf_offset = ADF_4XXXIOV_PF2VM_OFFSET,
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 228c057d1e..b8b5c387a3 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -21,6 +21,29 @@
 #define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
 #define MAX_QP_THRESHOLD_SIZE  32
 
+/**
+ * Function prototypes for GENx specific device operations.
+ **/
+typedef int (*qat_dev_reset_ring_pairs_t)
+   (struct qat_pci_device *);
+typedef const struct rte_mem_resource* (*qat_dev_get_transport_bar_t)
+   (struct rte_pci_device *);
+typedef int (*qat_dev_get_misc_bar_t)
+   (struct rte_mem_resource **, struct rte_pci_device *);
+typedef int (*qat_dev_read_config_t)
+   (struct qat_pci_device *);
+typedef int (*qat_dev_get_extra_size_t)(void);
+
+struct qat_dev_hw_spec_funcs {
+   qat_dev_reset_ring_pairs_t  qat_dev_reset_ring_pairs;
+   qat_dev_get_transport_bar_t qat_dev_get_transport_bar;
+   qat_dev_get_misc_bar_t  qat_dev_get_misc_bar;
+   qat_dev_read_config_t   qat_dev_read_config;
+   qat_dev_get_extra_size_tqat_dev_get_extra_size;
+};
+
+extern struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[];
+
 struct qat_dev_cmd_param {
const char *name;
uint16_t val;
-- 
2.25.1

[dpdk-dev] [dpdk-dev v4 2/9] common/qat: add gen specific device implementation

2021-10-22 Thread Fan Zhang

This patch replaces the mixed QAT device configuration
implementation by separate files with shared or
individual implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c |  66 +
 drivers/common/qat/dev/qat_dev_gen2.c |  23 +++
 drivers/common/qat/dev/qat_dev_gen3.c |  23 +++
 drivers/common/qat/dev/qat_dev_gen4.c | 152 +++
 drivers/common/qat/dev/qat_dev_gens.h |  34 +
 drivers/common/qat/meson.build|   4 +
 drivers/common/qat/qat_device.c   | 205 +++---
 drivers/common/qat/qat_device.h   |   5 +-
 drivers/common/qat/qat_qp.c   |   3 +-
 9 files changed, 391 insertions(+), 124 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen1.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen2.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen3.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen4.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gens.h

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
new file mode 100644
index 00..d9e75fe9e2
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+#define ADF_ARB_REG_SLOT   0x1000
+
+int
+qat_reset_ring_pairs_gen1(struct qat_pci_device *qat_pci_dev __rte_unused)
+{
+   /*
+* Ring pairs reset not supported on base, continue
+*/
+   return 0;
+}
+
+const struct rte_mem_resource *
+qat_dev_get_transport_bar_gen1(struct rte_pci_device *pci_dev)
+{
+   return &pci_dev->mem_resource[0];
+}
+
+int
+qat_dev_get_misc_bar_gen1(struct rte_mem_resource **mem_resource __rte_unused,
+   struct rte_pci_device *pci_dev __rte_unused)
+{
+   return -1;
+}
+
+int
+qat_dev_read_config_gen1(struct qat_pci_device *qat_dev __rte_unused)
+{
+   /*
+* Base generations do not have configuration,
+* but set this pointer anyway that we can
+* distinguish higher generations faulty set to NULL
+*/
+   return 0;
+}
+
+int
+qat_dev_get_extra_size_gen1(void)
+{
+   return 0;
+}
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen1 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen1_init)
+{
+   qat_dev_hw_spec[QAT_GEN1] = &qat_dev_hw_spec_gen1;
+   qat_gen_config[QAT_GEN1].dev_gen = QAT_GEN1;
+   qat_gen_config[QAT_GEN1].comp_num_im_bufs_required =
+   QAT_NUM_INTERM_BUFS_GEN1;
+}
diff --git a/drivers/common/qat/dev/qat_dev_gen2.c 
b/drivers/common/qat/dev/qat_dev_gen2.c
new file mode 100644
index 00..d3470ed6b8
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen2.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen2 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen2_init)
+{
+   qat_dev_hw_spec[QAT_GEN2] = &qat_dev_hw_spec_gen2;
+   qat_gen_config[QAT_GEN2].dev_gen = QAT_GEN2;
+}
diff --git a/drivers/common/qat/dev/qat_dev_gen3.c 
b/drivers/common/qat/dev/qat_dev_gen3.c
new file mode 100644
index 00..e4a66869d2
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen3.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen3 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen3_init)
+{
+   qat_dev_hw_spec[QAT_GEN3] = &qat_dev_hw_spec_gen3;
+

[dpdk-dev] [dpdk-dev v4 3/9] common/qat: add gen specific queue pair function

2021-10-22 Thread Fan Zhang

This patch adds the queue pair data structure and function
prototypes for different QAT generations.

Signed-off-by: Fan Zhang 
---
 drivers/common/qat/qat_qp.c |   3 ++
 drivers/common/qat/qat_qp.h | 103 
 2 files changed, 71 insertions(+), 35 deletions(-)

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index b8c6000e86..27994036b8 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -34,6 +34,9 @@
ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
(ADF_ARB_REG_SLOT * index), value)
 
+struct qat_qp_hw_spec_funcs*
+   qat_qp_hw_spec[QAT_N_GENS];
+
 __extension__
 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index e1627197fa..726cd2ef61 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -7,8 +7,6 @@
 #include "qat_common.h"
 #include "adf_transport_access_macros.h"
 
-struct qat_pci_device;
-
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */
 
@@ -24,37 +22,7 @@ struct qat_pci_device;
 #define QAT_GEN4_BUNDLE_NUM 4
 #define QAT_GEN4_QPS_PER_BUNDLE_NUM 1
 
-/**
- * Structure with data needed for creation of queue pair.
- */
-struct qat_qp_hw_data {
-   enum qat_service_type service_type;
-   uint8_t hw_bundle_num;
-   uint8_t tx_ring_num;
-   uint8_t rx_ring_num;
-   uint16_t tx_msg_size;
-   uint16_t rx_msg_size;
-};
-
-/**
- * Structure with data needed for creation of queue pair on gen4.
- */
-struct qat_qp_gen4_data {
-   struct qat_qp_hw_data qat_qp_hw_data;
-   uint8_t reserved;
-   uint8_t valid;
-};
-
-/**
- * Structure with data needed for creation of queue pair.
- */
-struct qat_qp_config {
-   const struct qat_qp_hw_data *hw;
-   uint32_t nb_descriptors;
-   uint32_t cookie_size;
-   int socket_id;
-   const char *service_str;
-};
+struct qat_pci_device;
 
 /**
  * Structure associated with each queue.
@@ -96,8 +64,28 @@ struct qat_qp {
uint16_t min_enq_burst_threshold;
 } __rte_cache_aligned;
 
-extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
-extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
+/**
+ * Structure with data needed for creation of queue pair.
+ */
+struct qat_qp_hw_data {
+   enum qat_service_type service_type;
+   uint8_t hw_bundle_num;
+   uint8_t tx_ring_num;
+   uint8_t rx_ring_num;
+   uint16_t tx_msg_size;
+   uint16_t rx_msg_size;
+};
+
+/**
+ * Structure with data needed for creation of queue pair.
+ */
+struct qat_qp_config {
+   const struct qat_qp_hw_data *hw;
+   uint32_t nb_descriptors;
+   uint32_t cookie_size;
+   int socket_id;
+   const char *service_str;
+};
 
 uint16_t
 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
@@ -136,4 +124,49 @@ qat_select_valid_queue(struct qat_pci_device *qat_dev, int 
qp_id,
 int
 qat_read_qp_config(struct qat_pci_device *qat_dev);
 
+/**
+ * Function prototypes for GENx specific queue pair operations.
+ **/
+typedef int (*qat_qp_rings_per_service_t)
+   (struct qat_pci_device *, enum qat_service_type);
+
+typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
+
+typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
+   rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
+   rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
+
+typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue 
*q);
+
+typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
+   uint32_t new_head);
+
+typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
+   struct qat_qp *);
+
+typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
+   struct qat_pci_device *dev, enum qat_service_type service_type,
+   uint16_t qp_id);
+
+struct qat_qp_hw_spec_funcs {
+   qat_qp_rings_per_service_t  qat_qp_rings_per_service;
+   qat_qp_build_ring_base_tqat_qp_build_ring_base;
+   qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable;
+   qat_qp_adf_arb_disable_tqat_qp_adf_arb_disable;
+   qat_qp_adf_configure_queues_t   qat_qp_adf_configure_queues;
+   qat_qp_csr_write_tail_t qat_qp_csr_write_tail;
+   qat_qp_csr_write_head_t qat_qp_csr_write_head;
+   qat_qp_csr_setup_t  qat_qp_csr_setup;
+   qat_qp_get_hw_data_tqat_qp_get_hw_data;
+};
+
+extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
+
+extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];

[dpdk-dev] [dpdk-dev v4 4/9] common/qat: add gen specific queue implementation

2021-10-22 Thread Fan Zhang

This patch replaces the mixed QAT queue pair configuration
implementation by separate files with shared or individual
implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c | 190 +
 drivers/common/qat/dev/qat_dev_gen2.c |  14 +
 drivers/common/qat/dev/qat_dev_gen3.c |  60 ++
 drivers/common/qat/dev/qat_dev_gen4.c | 161 -
 drivers/common/qat/dev/qat_dev_gens.h |  37 +-
 .../qat/qat_adf/adf_transport_access_macros.h |   2 +
 drivers/common/qat/qat_device.h   |   3 -
 drivers/common/qat/qat_qp.c   | 677 +++---
 drivers/common/qat/qat_qp.h   |  24 +-
 drivers/crypto/qat/qat_sym_pmd.c  |  32 +-
 10 files changed, 723 insertions(+), 477 deletions(-)

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
index d9e75fe9e2..cc63b55bd1 100644
--- a/drivers/common/qat/dev/qat_dev_gen1.c
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -3,6 +3,7 @@
  */
 
 #include "qat_device.h"
+#include "qat_qp.h"
 #include "adf_transport_access_macros.h"
 #include "qat_dev_gens.h"
 
@@ -10,6 +11,194 @@
 
 #define ADF_ARB_REG_SLOT   0x1000
 
+#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
+   ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
+   (ADF_ARB_REG_SLOT * index), value)
+
+__extension__
+const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
+[ADF_MAX_QPS_ON_ANY_SERVICE] = {
+   /* queue pairs which provide an asymmetric crypto service */
+   [QAT_SERVICE_ASYMMETRIC] = {
+   {
+   .service_type = QAT_SERVICE_ASYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 0,
+   .rx_ring_num = 8,
+   .tx_msg_size = 64,
+   .rx_msg_size = 32,
+
+   }, {
+   .service_type = QAT_SERVICE_ASYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 1,
+   .rx_ring_num = 9,
+   .tx_msg_size = 64,
+   .rx_msg_size = 32,
+   }
+   },
+   /* queue pairs which provide a symmetric crypto service */
+   [QAT_SERVICE_SYMMETRIC] = {
+   {
+   .service_type = QAT_SERVICE_SYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 2,
+   .rx_ring_num = 10,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   },
+   {
+   .service_type = QAT_SERVICE_SYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 3,
+   .rx_ring_num = 11,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }
+   },
+   /* queue pairs which provide a compression service */
+   [QAT_SERVICE_COMPRESSION] = {
+   {
+   .service_type = QAT_SERVICE_COMPRESSION,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 6,
+   .rx_ring_num = 14,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }, {
+   .service_type = QAT_SERVICE_COMPRESSION,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 7,
+   .rx_ring_num = 15,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }
+   }
+};
+
+const struct qat_qp_hw_data *
+qat_qp_get_hw_data_gen1(struct qat_pci_device *dev __rte_unused,
+   enum qat_service_type service_type, uint16_t qp_id)
+{
+   return qat_gen1_qps[service_type] + qp_id;
+}
+
+int
+qat_qp_rings_per_service_gen1(struct qat_pci_device *qat_dev,
+   enum qat_service_type service)
+{
+   int i = 0, count = 0;
+
+   for (i = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++) {
+   const struct qat_qp_hw_data *hw_qps =
+   qat_qp_get_hw_data(qat_dev, service, i);
+   if (hw_qps->service_type == service)
+   count++;
+   }
+
+   return count;
+}
+
+void
+qat_qp_csr_build_ring_base_gen1(void *io_addr,
+   struct qat_queue *queue)
+{
+   uint64_t queue_base;
+
+   queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
+   queue->queue_size);
+   WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
+   queue->hw_queue_number, queue_base);
+}
+
+void
+qat_qp_adf_arb_enable_gen1(const stru

[dpdk-dev] [dpdk-dev v4 5/9] compress/qat: add gen specific data and function

2021-10-22 Thread Fan Zhang

This patch adds the compression data structure and function
prototypes for different QAT generations.

Signed-off-by: Adam Dybkowski 
Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c |   2 -
 .../common/qat/qat_adf/icp_qat_hw_gen4_comp.h | 195 
 .../qat/qat_adf/icp_qat_hw_gen4_comp_defs.h   | 299 ++
 drivers/common/qat/qat_common.h   |   4 +-
 drivers/common/qat/qat_device.h   |   7 -
 drivers/compress/qat/qat_comp.c   | 101 +++---
 drivers/compress/qat/qat_comp.h   |   8 +-
 drivers/compress/qat/qat_comp_pmd.c   | 159 --
 drivers/compress/qat/qat_comp_pmd.h   |  76 +
 9 files changed, 675 insertions(+), 176 deletions(-)
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
index cc63b55bd1..38757e6e40 100644
--- a/drivers/common/qat/dev/qat_dev_gen1.c
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -251,6 +251,4 @@ RTE_INIT(qat_dev_gen_gen1_init)
qat_qp_hw_spec[QAT_GEN1] = &qat_qp_hw_spec_gen1;
qat_dev_hw_spec[QAT_GEN1] = &qat_dev_hw_spec_gen1;
qat_gen_config[QAT_GEN1].dev_gen = QAT_GEN1;
-   qat_gen_config[QAT_GEN1].comp_num_im_bufs_required =
-   QAT_NUM_INTERM_BUFS_GEN1;
 }
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h 
b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
new file mode 100644
index 00..ec69dc7105
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#ifndef _ICP_QAT_HW_GEN4_COMP_H_
+#define _ICP_QAT_HW_GEN4_COMP_H_
+
+#include "icp_qat_fw.h"
+#include "icp_qat_hw_gen4_comp_defs.h"
+
+struct icp_qat_hw_comp_20_config_csr_lower {
+   icp_qat_hw_comp_20_extended_delay_match_mode_t edmm;
+   icp_qat_hw_comp_20_hw_comp_format_t algo;
+   icp_qat_hw_comp_20_search_depth_t sd;
+   icp_qat_hw_comp_20_hbs_control_t hbs;
+   icp_qat_hw_comp_20_abd_t abd;
+   icp_qat_hw_comp_20_lllbd_ctrl_t lllbd;
+   icp_qat_hw_comp_20_min_match_control_t mmctrl;
+   icp_qat_hw_comp_20_skip_hash_collision_t hash_col;
+   icp_qat_hw_comp_20_skip_hash_update_t hash_update;
+   icp_qat_hw_comp_20_byte_skip_t skip_ctrl;
+};
+
+static inline uint32_t ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(
+   struct icp_qat_hw_comp_20_config_csr_lower csr)
+{
+   uint32_t val32 = 0;
+
+   QAT_FIELD_SET(val32, csr.algo,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
+
+   QAT_FIELD_SET(val32, csr.sd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
+
+   QAT_FIELD_SET(val32, csr.edmm,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
+
+   QAT_FIELD_SET(val32, csr.hbs,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
+
+   QAT_FIELD_SET(val32, csr.lllbd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
+
+   QAT_FIELD_SET(val32, csr.mmctrl,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
+
+   QAT_FIELD_SET(val32, csr.hash_col,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
+
+   QAT_FIELD_SET(val32, csr.hash_update,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
+
+   QAT_FIELD_SET(val32, csr.skip_ctrl,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
+
+   QAT_FIELD_SET(val32, csr.abd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
+
+   QAT_FIELD_SET(val32, csr.lllbd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
+
+   return rte_bswap32(val32);
+}
+
+struct icp_qat_hw_comp_20_config_csr_upper {
+   icp_qat_hw_comp_20_scb_control_t scb_ctrl;
+   icp_qat_hw_comp_20_rmb_control_t rmb_ctrl;
+   icp_qat_hw_comp_20_som_control_t som_ctrl;
+   icp_qat_hw_comp_20_skip_hash

[dpdk-dev] [dpdk-dev v4 6/9] compress/qat: add gen specific implementation

2021-10-22 Thread Fan Zhang

This patch replaces the mixed QAT compression support
implementation by separate files with shared or individual
implementation for specific QAT generation.

Signed-off-by: Adam Dybkowski 
Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   4 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen1.c | 175 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen2.c |  30 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen3.c |  30 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 213 +++
 drivers/compress/qat/dev/qat_comp_pmd_gens.h |  30 +++
 6 files changed, 481 insertions(+), 1 deletion(-)
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen1.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen2.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen3.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen4.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gens.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 532e0fabb3..8a1c6d64e8 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -62,7 +62,9 @@ includes += include_directories(
 )
 
 if qat_compress
-foreach f: ['qat_comp_pmd.c', 'qat_comp.c']
+foreach f: ['qat_comp_pmd.c', 'qat_comp.c',
+'dev/qat_comp_pmd_gen1.c', 'dev/qat_comp_pmd_gen2.c',
+'dev/qat_comp_pmd_gen3.c', 'dev/qat_comp_pmd_gen4.c']
 sources += files(join_paths(qat_compress_relpath, f))
 endforeach
 endif
diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen1.c 
b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c
new file mode 100644
index 00..8a8fa4aec5
--- /dev/null
+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include "qat_comp_pmd.h"
+#include "qat_comp.h"
+#include "qat_comp_pmd_gens.h"
+
+#define QAT_NUM_INTERM_BUFS_GEN1 12
+
+const struct rte_compressdev_capabilities qat_gen1_comp_capabilities[] = {
+   {/* COMPRESSION - deflate */
+.algo = RTE_COMP_ALGO_DEFLATE,
+.comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+   RTE_COMP_FF_CRC32_CHECKSUM |
+   RTE_COMP_FF_ADLER32_CHECKSUM |
+   RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+   RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+   RTE_COMP_FF_HUFFMAN_FIXED |
+   RTE_COMP_FF_HUFFMAN_DYNAMIC |
+   RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
+   RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
+   RTE_COMP_FF_OOP_LB_IN_SGL_OUT |
+   RTE_COMP_FF_STATEFUL_DECOMPRESSION,
+.window_size = {.min = 15, .max = 15, .increment = 0} },
+   {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
+static int
+qat_comp_dev_config_gen1(struct rte_compressdev *dev,
+   struct rte_compressdev_config *config)
+{
+   struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+   if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+   QAT_LOG(WARNING,
+   "QAT device cannot be used for Dynamic Deflate.");
+   } else {
+   comp_dev->interm_buff_mz =
+   qat_comp_setup_inter_buffers(comp_dev,
+   RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+   if (comp_dev->interm_buff_mz == NULL)
+   return -ENOMEM;
+   }
+
+   return qat_comp_dev_config(dev, config);
+}
+
+struct rte_compressdev_ops qat_comp_ops_gen1 = {
+
+   /* Device related operations */
+   .dev_configure  = qat_comp_dev_config_gen1,
+   .dev_start  = qat_comp_dev_start,
+   .dev_stop   = qat_comp_dev_stop,
+   .dev_close  = qat_comp_dev_close,
+   .dev_infos_get  = qat_comp_dev_info_get,
+
+   .stats_get  = qat_comp_stats_get,
+   .stats_reset= qat_comp_stats_reset,
+   .queue_pair_setup   = qat_comp_qp_setup,
+   .queue_pair_release = qat_comp_qp_release,
+
+   /* Compression related operations */
+   .private_xform_create   = qat_comp_private_xform_create,
+   .private_xform_free = qat_comp_private_xform_free,
+   .stream_create  = qat_comp_stream_create,
+   .stream_free= qat_comp_stream_free
+};
+
+struct qat_comp_capabilities_info
+qat_comp_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)
+{
+   struct qat_comp_capabilities_info capa_info = {
+   .data = qat_ge

[dpdk-dev] [dpdk-dev v4 7/9] crypto/qat: unified device private data structure

2021-10-22 Thread Fan Zhang

This patch unifies the QAT symmetric and asymmetric device
private data structures and functions.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   2 +-
 drivers/common/qat/qat_common.c  |  15 ++
 drivers/common/qat/qat_common.h  |   3 +
 drivers/common/qat/qat_device.h  |   7 +-
 drivers/crypto/qat/qat_asym_pmd.c| 216 ---
 drivers/crypto/qat/qat_asym_pmd.h|  29 +---
 drivers/crypto/qat/qat_crypto.c  | 172 ++
 drivers/crypto/qat/qat_crypto.h  |  78 +
 drivers/crypto/qat/qat_sym_pmd.c | 250 +--
 drivers/crypto/qat/qat_sym_pmd.h |  21 +--
 drivers/crypto/qat/qat_sym_session.c |  15 +-
 11 files changed, 361 insertions(+), 447 deletions(-)
 create mode 100644 drivers/crypto/qat/qat_crypto.c
 create mode 100644 drivers/crypto/qat/qat_crypto.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 8a1c6d64e8..29fd0168ea 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -71,7 +71,7 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c']
+'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']
 sources += files(join_paths(qat_crypto_relpath, f))
 endforeach
 deps += ['security']
diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c
index 5343a1451e..59e7e02622 100644
--- a/drivers/common/qat/qat_common.c
+++ b/drivers/common/qat/qat_common.c
@@ -6,6 +6,21 @@
 #include "qat_device.h"
 #include "qat_logs.h"
 
+const char *
+qat_service_get_str(enum qat_service_type type)
+{
+   switch (type) {
+   case QAT_SERVICE_SYMMETRIC:
+   return "sym";
+   case QAT_SERVICE_ASYMMETRIC:
+   return "asym";
+   case QAT_SERVICE_COMPRESSION:
+   return "comp";
+   default:
+   return "invalid";
+   }
+}
+
 int
 qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,
void *list_in, uint32_t data_len,
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index a7632e31f8..9411a79301 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -91,4 +91,7 @@ void
 qat_stats_reset(struct qat_pci_device *dev,
enum qat_service_type service);
 
+const char *
+qat_service_get_str(enum qat_service_type type);
+
 #endif /* _QAT_COMMON_H_ */
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index e7c7e9af95..85fae7b7c7 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -76,8 +76,7 @@ struct qat_device_info {
 
 extern struct qat_device_info qat_pci_devs[];
 
-struct qat_sym_dev_private;
-struct qat_asym_dev_private;
+struct qat_cryptodev_private;
 struct qat_comp_dev_private;
 
 /*
@@ -106,14 +105,14 @@ struct qat_pci_device {
/**< links to qps set up for each service, index same as on API */
 
/* Data relating to symmetric crypto service */
-   struct qat_sym_dev_private *sym_dev;
+   struct qat_cryptodev_private *sym_dev;
/**< link back to cryptodev private data */
 
int qat_sym_driver_id;
/**< Symmetric driver id used by this device */
 
/* Data relating to asymmetric crypto service */
-   struct qat_asym_dev_private *asym_dev;
+   struct qat_cryptodev_private *asym_dev;
/**< link back to cryptodev private data */
 
int qat_asym_driver_id;
diff --git a/drivers/crypto/qat/qat_asym_pmd.c 
b/drivers/crypto/qat/qat_asym_pmd.c
index 0944d27a4d..042f39ddcc 100644
--- a/drivers/crypto/qat/qat_asym_pmd.c
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -6,6 +6,7 @@
 
 #include "qat_logs.h"
 
+#include "qat_crypto.h"
 #include "qat_asym.h"
 #include "qat_asym_pmd.h"
 #include "qat_sym_capabilities.h"
@@ -18,190 +19,45 @@ static const struct rte_cryptodev_capabilities 
qat_gen1_asym_capabilities[] = {
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-static int qat_asym_qp_release(struct rte_cryptodev *dev,
-  uint16_t queue_pair_id);
-
-static int qat_asym_dev_config(__rte_unused struct rte_cryptodev *dev,
-  __rte_unused struct rte_cryptodev_config *config)
-{
-   return 0;
-}
-
-static int qat_asym_dev_start(__rte_unused struct rte_cryptodev *dev)
-{
-   return 0;
-}
-
-static void qat_asym_dev_stop(__rte_unused struct rte_cryptodev *dev)
-{
-
-}
-
-static int qat_asym_dev_close(struct rte_cryptodev *dev)
-{
-   int i, ret;
-
-   for (i = 0

[dpdk-dev] [dpdk-dev v4 8/9] crypto/qat: add gen specific data and function

2021-10-22 Thread Fan Zhang

This patch adds the symmetric and asymmetric crypto data
structure and function prototypes for different QAT
generations.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/crypto/qat/README  |7 -
 drivers/crypto/qat/meson.build |   26 -
 drivers/crypto/qat/qat_asym_capabilities.h |   63 -
 drivers/crypto/qat/qat_asym_pmd.c  |   60 +-
 drivers/crypto/qat/qat_asym_pmd.h  |   25 +
 drivers/crypto/qat/qat_crypto.h|   16 +
 drivers/crypto/qat/qat_sym_capabilities.h  | 1248 
 drivers/crypto/qat/qat_sym_pmd.c   |  186 +--
 drivers/crypto/qat/qat_sym_pmd.h   |   57 +-
 9 files changed, 165 insertions(+), 1523 deletions(-)
 delete mode 100644 drivers/crypto/qat/README
 delete mode 100644 drivers/crypto/qat/meson.build
 delete mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
 delete mode 100644 drivers/crypto/qat/qat_sym_capabilities.h

diff --git a/drivers/crypto/qat/README b/drivers/crypto/qat/README
deleted file mode 100644
index 444ae605f0..00
--- a/drivers/crypto/qat/README
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2015-2018 Intel Corporation
-
-Makefile for crypto QAT PMD is in common/qat directory.
-The build for the QAT driver is done from there as only one library is built 
for the
-whole QAT pci device and that library includes all the services (crypto, 
compression)
-which are enabled on the device.
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
deleted file mode 100644
index b3b2d17258..00
--- a/drivers/crypto/qat/meson.build
+++ /dev/null
@@ -1,26 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017-2018 Intel Corporation
-
-# this does not build the QAT driver, instead that is done in the compression
-# driver which comes later. Here we just add our sources files to the list
-build = false
-reason = '' # sentinal value to suppress printout
-dep = dependency('libcrypto', required: false, method: 'pkg-config')
-qat_includes += include_directories('.')
-qat_deps += 'cryptodev'
-qat_deps += 'net'
-qat_deps += 'security'
-if dep.found()
-# Add our sources files to the list
-qat_sources += files(
-'qat_asym.c',
-'qat_asym_pmd.c',
-'qat_sym.c',
-'qat_sym_hw_dp.c',
-'qat_sym_pmd.c',
-'qat_sym_session.c',
-   )
-qat_ext_deps += dep
-qat_cflags += '-DBUILD_QAT_SYM'
-qat_cflags += '-DBUILD_QAT_ASYM'
-endif
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h 
b/drivers/crypto/qat/qat_asym_capabilities.h
deleted file mode 100644
index 523b4da6d3..00
--- a/drivers/crypto/qat/qat_asym_capabilities.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019 Intel Corporation
- */
-
-#ifndef _QAT_ASYM_CAPABILITIES_H_
-#define _QAT_ASYM_CAPABILITIES_H_
-
-#define QAT_BASE_GEN1_ASYM_CAPABILITIES
\
-   {   /* modexp */
\
-   .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
\
-   {.asym = {  
\
-   .xform_capa = { 
\
-   .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,  
\
-   .op_types = 0,  
\
-   {   
\
-   .modlen = { 
\
-   .min = 1,   
\
-   .max = 512, 
\
-   .increment = 1  
\
-   }, }
\
-   }   
\
-   },  
\
-   }   
\
-   },  
\
-   {   /* modinv */
\
-   .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
\
-   {.asym = {  
\
-   .xform_capa = {

[dpdk-dev] [dpdk-dev v4 9/9] crypto/qat: add gen specific implementation

2021-10-22 Thread Fan Zhang

This patch replaces the mixed QAT symmetric and asymmetric
support implementation by separate files with shared or
individual implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   7 +-
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   |  76 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 224 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 164 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 124 
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  36 +++
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 283 +++
 drivers/crypto/qat/qat_crypto.h  |   3 -
 8 files changed, 913 insertions(+), 4 deletions(-)
 create mode 100644 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
 create mode 100644 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 29fd0168ea..ce9959d103 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -71,7 +71,12 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']
+'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',
+   'dev/qat_sym_pmd_gen1.c',
+'dev/qat_asym_pmd_gen1.c',
+'dev/qat_crypto_pmd_gen2.c',
+'dev/qat_crypto_pmd_gen3.c',
+'dev/qat_crypto_pmd_gen4.c']
 sources += files(join_paths(qat_crypto_relpath, f))
 endforeach
 deps += ['security']
diff --git a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c 
b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
new file mode 100644
index 00..9ed1f21d9d
--- /dev/null
+++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017-2021 Intel Corporation
+ */
+
+#include 
+#include 
+#include "qat_asym.h"
+#include "qat_crypto.h"
+#include "qat_crypto_pmd_gens.h"
+#include "qat_pke_functionality_arrays.h"
+
+struct rte_cryptodev_ops qat_asym_crypto_ops_gen1 = {
+   /* Device related operations */
+   .dev_configure  = qat_cryptodev_config,
+   .dev_start  = qat_cryptodev_start,
+   .dev_stop   = qat_cryptodev_stop,
+   .dev_close  = qat_cryptodev_close,
+   .dev_infos_get  = qat_cryptodev_info_get,
+
+   .stats_get  = qat_cryptodev_stats_get,
+   .stats_reset= qat_cryptodev_stats_reset,
+   .queue_pair_setup   = qat_cryptodev_qp_setup,
+   .queue_pair_release = qat_cryptodev_qp_release,
+
+   /* Crypto related operations */
+   .asym_session_get_size  = qat_asym_session_get_private_size,
+   .asym_session_configure = qat_asym_session_configure,
+   .asym_session_clear = qat_asym_session_clear
+};
+
+static struct rte_cryptodev_capabilities qat_asym_crypto_caps_gen1[] = {
+   QAT_ASYM_CAP(MODEX,
+   0, 1, 512, 1),
+   QAT_ASYM_CAP(MODINV,
+   0, 1, 512, 1),
+   QAT_ASYM_CAP(RSA,
+   ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
+   (1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
+   (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
+   (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
+   64, 512, 64),
+   RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+
+struct qat_capabilities_info
+qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)
+{
+   struct qat_capabilities_info capa_info;
+   capa_info.data = qat_asym_crypto_caps_gen1;
+   capa_info.size = sizeof(qat_asym_crypto_caps_gen1);
+   return capa_info;
+}
+
+uint64_t
+qat_asym_crypto_feature_flags_get_gen1(
+   struct qat_pci_device *qat_dev __rte_unused)
+{
+   uint64_t feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+   RTE_CRYPTODEV_FF_HW_ACCELERATED |
+   RTE_CRYPTODEV_FF_ASYM_SESSIONLESS |
+   RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_EXP |
+   RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
+
+   return feature_flags;
+}
+
+RTE_INIT(qat_asym_crypto_gen1_init)
+{
+   qat_asym_gen_dev_ops[QAT_GEN1].cryptodev_ops =
+   &qat_asym_crypto_ops_gen1;
+   qat_asym_gen_dev_ops[QAT_GE

[dpdk-dev] [PATCH] examples/fips_validation: fix device start

2021-10-28 Thread Fan Zhang

Fixes: 261bbff75e34 ("examples: use separate crypto session mempools")
Cc: roy.fan.zh...@intel.com

Bugzilla Link: https://bugs.dpdk.org/show_bug.cgi?id=842

This patch fixes the missing device start for fips validation
sample app.

Signed-off-by: Fan Zhang 
---
 examples/fips_validation/main.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/examples/fips_validation/main.c b/examples/fips_validation/main.c
index b0de3d269a..dc40bffe7d 100644
--- a/examples/fips_validation/main.c
+++ b/examples/fips_validation/main.c
@@ -134,6 +134,10 @@ cryptodev_fips_validate_app_int(void)
if (ret < 0)
goto error_exit;
 
+   ret = rte_cryptodev_start(env.dev_id);
+   if (ret < 0)
+   goto error_exit;
+
return 0;
 
 error_exit:
-- 
2.25.1

[dpdk-dev] app/test: fix pdcp short mac test

2021-09-16 Thread Fan Zhang

Fixes: c24489e479fd ("test/crypto: support PDCP short MAC-I")
Cc: g.si...@nxp.com

This patch fixes the pdcp short mac-i test by removing them
from snow3g and kasumi test suite and move to pdcp test suite.
This is to prevent incorrect failure for crypto device not
support pdcp.

Signed-off-by: Fan Zhang 
---
 app/test/test_cryptodev.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 16d770a17f..d19482c20a 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -8886,6 +8886,7 @@ test_PDCP_PROTO_all(void)
status += test_PDCP_PROTO_SGL_oop_128B_32B();
status += test_PDCP_SDAP_PROTO_encap_all();
status += test_PDCP_SDAP_PROTO_decap_all();
+   status += test_PDCP_PROTO_short_mac();
 
if (status)
return TEST_FAILED;
@@ -14083,8 +14084,6 @@ static struct unit_test_suite 
cryptodev_snow3g_testsuite  = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_snow3g_encryption_test_case_5),
 
-   TEST_CASE_ST(ut_setup, ut_teardown,
-   test_PDCP_PROTO_short_mac),
TEST_CASE_ST(ut_setup, ut_teardown,
test_snow3g_encryption_test_case_1_oop),
TEST_CASE_ST(ut_setup, ut_teardown,
@@ -14324,9 +14323,6 @@ static struct unit_test_suite 
cryptodev_kasumi_testsuite  = {
test_kasumi_decryption_test_case_5),
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_decryption_test_case_1_oop),
-
-   TEST_CASE_ST(ut_setup, ut_teardown,
-   test_PDCP_PROTO_short_mac),
TEST_CASE_ST(ut_setup, ut_teardown,
test_kasumi_cipher_auth_test_case_1),
 
-- 
2.25.1

[dpdk-dev] [dpdk-dev v4] crypto/snow3g: add support for digest appended ops

2021-07-27 Thread Fan Zhang

From: Kai Ji 

This patch enable out-of-place auth-cipher operations where
digest should be encrypted among with the rest of raw data.
It also adds support for partially encrypted digest when using
auth-cipher operations.

Fixes: 7c87e2d7b359 ("crypto/snow3g: use IPsec library")
Cc: pablo.de.lara.gua...@intel.com

Signed-off-by: Damian Nowak 
Signed-off-by: Kai Ji 
---
v4:
fixed compile issue.


 doc/guides/cryptodevs/features/snow3g.ini |   1 +
 drivers/crypto/snow3g/rte_snow3g_pmd.c| 139 +++---
 2 files changed, 123 insertions(+), 17 deletions(-)

diff --git a/doc/guides/cryptodevs/features/snow3g.ini 
b/doc/guides/cryptodevs/features/snow3g.ini
index 14ac7e4b6d..4d4c5b579b 100644
--- a/doc/guides/cryptodevs/features/snow3g.ini
+++ b/doc/guides/cryptodevs/features/snow3g.ini
@@ -8,6 +8,7 @@ Symmetric crypto   = Y
 Sym operation chaining = Y
 Symmetric sessionless  = Y
 Non-Byte aligned data  = Y
+Digest encrypted   = Y
 OOP LB  In LB  Out = Y
 
 ;
diff --git a/drivers/crypto/snow3g/rte_snow3g_pmd.c 
b/drivers/crypto/snow3g/rte_snow3g_pmd.c
index 9aab357846..2c99ed02db 100644
--- a/drivers/crypto/snow3g/rte_snow3g_pmd.c
+++ b/drivers/crypto/snow3g/rte_snow3g_pmd.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2016-2018 Intel Corporation
+ * Copyright(c) 2016-2021 Intel Corporation
  */
 
 #include 
@@ -179,6 +179,24 @@ snow3g_get_session(struct snow3g_qp *qp, struct 
rte_crypto_op *op)
return sess;
 }
 
+/** Check if conditions are met for digest-appended operations */
+static uint8_t *
+snow3g_digest_appended_in_src(struct rte_crypto_op *op)
+{
+   unsigned int auth_size, cipher_size;
+
+   auth_size = (op->sym->auth.data.offset >> 3) +
+   (op->sym->auth.data.length >> 3);
+   cipher_size = (op->sym->cipher.data.offset >> 3) +
+   (op->sym->cipher.data.length >> 3);
+
+   if (auth_size < cipher_size)
+   return rte_pktmbuf_mtod_offset(op->sym->m_src,
+   uint8_t *, auth_size);
+
+   return NULL;
+}
+
 /** Encrypt/decrypt mbufs with same cipher key. */
 static uint8_t
 process_snow3g_cipher_op(struct snow3g_qp *qp, struct rte_crypto_op **ops,
@@ -187,22 +205,52 @@ process_snow3g_cipher_op(struct snow3g_qp *qp, struct 
rte_crypto_op **ops,
 {
unsigned i;
uint8_t processed_ops = 0;
-   const void *src[SNOW3G_MAX_BURST];
-   void *dst[SNOW3G_MAX_BURST];
-   const void *iv[SNOW3G_MAX_BURST];
-   uint32_t num_bytes[SNOW3G_MAX_BURST];
+   const void *src[SNOW3G_MAX_BURST] = {NULL};
+   void *dst[SNOW3G_MAX_BURST] = {NULL};
+   uint8_t *digest_appended[SNOW3G_MAX_BURST] = {NULL };
+   const void *iv[SNOW3G_MAX_BURST] = {NULL};
+   uint32_t num_bytes[SNOW3G_MAX_BURST] = {0};
+   uint32_t cipher_off, cipher_len;
+   int unencrypted_bytes = 0;
 
for (i = 0; i < num_ops; i++) {
-   src[i] = rte_pktmbuf_mtod(ops[i]->sym->m_src, uint8_t *) +
-   (ops[i]->sym->cipher.data.offset >> 3);
-   dst[i] = ops[i]->sym->m_dst ?
-   rte_pktmbuf_mtod(ops[i]->sym->m_dst, uint8_t *) +
-   (ops[i]->sym->cipher.data.offset >> 3) :
-   rte_pktmbuf_mtod(ops[i]->sym->m_src, uint8_t *) +
-   (ops[i]->sym->cipher.data.offset >> 3);
+   cipher_off = ops[i]->sym->cipher.data.offset >> 3;
+   cipher_len = ops[i]->sym->cipher.data.length >> 3;
+   src[i] = rte_pktmbuf_mtod_offset(
+   ops[i]->sym->m_src, uint8_t *, cipher_off);
+
+   /* If out-of-place operation */
+   if (ops[i]->sym->m_dst &&
+   ops[i]->sym->m_src != ops[i]->sym->m_dst) {
+   dst[i] = rte_pktmbuf_mtod_offset(
+   ops[i]->sym->m_dst, uint8_t *, cipher_off);
+
+   /* In case of out-of-place, auth-cipher operation
+* with partial encryption of the digest, copy
+* the remaining, unencrypted part.
+*/
+   if (session->op == SNOW3G_OP_AUTH_CIPHER)
+   unencrypted_bytes =
+   (ops[i]->sym->auth.data.offset >> 3) +
+   (ops[i]->sym->auth.data.length >> 3) +
+   (SNOW3G_DIGEST_LENGTH) -
+   cipher_off - cipher_len;
+   if (unencrypted_bytes > 0)
+   rte_memcpy(
+   rte_pktmbuf_mtod_offset(
+   ops[i]->sym->m_dst, uint8_t *,
+   cipher_off + cipher_len),
+   rte_pktmbuf_mtod_offset(
+

[dpdk-dev] crypto/qat: fix failed raw data path dequeue

2021-07-27 Thread Fan Zhang

This patch fixes the raw data path dequeue burst fail problem.
Previously the in case the queue is full and not all packets
asked to be dequeued are processed, the dequeue burst will
never happen.

Fixes: c21574edc52a ("cryptodev: add dequeue count parameter in raw API")
Cc: roy.fan.zh...@intel.com

Signed-off-by: Fan Zhang 
---
 drivers/crypto/qat/qat_sym_hw_dp.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_hw_dp.c 
b/drivers/crypto/qat/qat_sym_hw_dp.c
index 4305579b54..ac9ac05363 100644
--- a/drivers/crypto/qat/qat_sym_hw_dp.c
+++ b/drivers/crypto/qat/qat_sym_hw_dp.c
@@ -744,14 +744,6 @@ qat_sym_dp_dequeue_burst(void *qp_data, uint8_t *drv_ctx,
n = get_dequeue_count(resp_opaque);
if (unlikely(n == 0))
return 0;
-   else if (n > 1) {
-   head = (head + rx_queue->msg_size * (n - 1)) &
-   rx_queue->modulo_mask;
-   resp = (struct icp_qat_fw_comn_resp *)(
-   (uint8_t *)rx_queue->base_addr + head);
-   if (*(uint32_t *)resp == ADF_RING_EMPTY_SIG)
-   return 0;
-   }
} else {
if (unlikely(max_nb_to_dequeue == 0))
return 0;
-- 
2.25.1

[dpdk-dev] crypto/qat: fix digest in buffer

2021-01-20 Thread Fan Zhang

This patch fixes the missed digest in buffer support to
QAT symmetric raw API. Originally digest in buffer is
supported only for wireless algorithms

Fixes: 728c76b0e50f ("crypto/qat: support raw datapath API")
Cc: roy.fan.zh...@intel.com
Cc: sta...@dpdk.org

Signed-off-by: Fan Zhang 
---
 drivers/crypto/qat/qat_sym_hw_dp.c | 97 +++---
 1 file changed, 48 insertions(+), 49 deletions(-)

diff --git a/drivers/crypto/qat/qat_sym_hw_dp.c 
b/drivers/crypto/qat/qat_sym_hw_dp.c
index dfbbad59b..01afb883e 100644
--- a/drivers/crypto/qat/qat_sym_hw_dp.c
+++ b/drivers/crypto/qat/qat_sym_hw_dp.c
@@ -558,55 +558,6 @@ enqueue_one_chain_job(struct qat_sym_session *ctx,
case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
case ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:
auth_param->u1.aad_adr = auth_iv->iova;
-
-   if (unlikely(n_data_vecs > 1)) {
-   int auth_end_get = 0, i = n_data_vecs - 1;
-   struct rte_crypto_vec *cvec = &data[0];
-   uint32_t len;
-
-   len = data_len - ofs.ofs.auth.tail;
-
-   while (i >= 0 && len > 0) {
-   if (cvec->len >= len) {
-   auth_iova_end = cvec->iova +
-   (cvec->len - len);
-   len = 0;
-   auth_end_get = 1;
-   break;
-   }
-   len -= cvec->len;
-   i--;
-   cvec++;
-   }
-
-   if (unlikely(auth_end_get == 0))
-   return -1;
-   } else
-   auth_iova_end = data[0].iova + auth_param->auth_off +
-   auth_param->auth_len;
-
-   /* Then check if digest-encrypted conditions are met */
-   if ((auth_param->auth_off + auth_param->auth_len <
-   cipher_param->cipher_offset +
-   cipher_param->cipher_length) &&
-   (digest->iova == auth_iova_end)) {
-   /* Handle partial digest encryption */
-   if (cipher_param->cipher_offset +
-   cipher_param->cipher_length <
-   auth_param->auth_off +
-   auth_param->auth_len +
-   ctx->digest_length)
-   req->comn_mid.dst_length =
-   req->comn_mid.src_length =
-   auth_param->auth_off +
-   auth_param->auth_len +
-   ctx->digest_length;
-   struct icp_qat_fw_comn_req_hdr *header =
-   &req->comn_hdr;
-   ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
-   header->serv_specif_flags,
-   ICP_QAT_FW_LA_DIGEST_IN_BUFFER);
-   }
break;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
@@ -615,6 +566,54 @@ enqueue_one_chain_job(struct qat_sym_session *ctx,
break;
}
 
+   if (unlikely(n_data_vecs > 1)) {
+   int auth_end_get = 0, i = n_data_vecs - 1;
+   struct rte_crypto_vec *cvec = &data[0];
+   uint32_t len;
+
+   len = data_len - ofs.ofs.auth.tail;
+
+   while (i >= 0 && len > 0) {
+   if (cvec->len >= len) {
+   auth_iova_end = cvec->iova + len;
+   len = 0;
+   auth_end_get = 1;
+   break;
+   }
+   len -= cvec->len;
+   i--;
+   cvec++;
+   }
+
+   if (unlikely(auth_end_get == 0))
+   return -1;
+   } else
+   auth_iova_end = data[0].iova + auth_param->auth_off +
+   auth_param->auth_len;
+
+   /* Then check if digest-encrypted conditions are met */
+   if ((auth_param->auth_off + auth_param->auth_len <
+   cipher_param->cipher_offset +
+   cipher_param->cipher_length) &&
+   (digest->iova == auth_iova_end)) {
+   /* Handle partial digest encryption */
+   if (cipher_param->cipher_offset +
+

[PATCH] maintainers: update maintainer

2022-09-21 Thread Fan Zhang

Update maintainer and email address.

Signed-off-by: Fan Zhang 
Signed-off-by: Kai ji 
---
 MAINTAINERS | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 26d3a7077c..20eb277b35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -445,7 +445,7 @@ F: doc/guides/sample_app_ug/bbdev_app.rst
 
 Crypto API
 M: Akhil Goyal 
-M: Fan Zhang 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/cryptodev/
 F: app/test/test_cryptodev*
@@ -459,7 +459,7 @@ F: doc/guides/prog_guide/rte_security.rst
 F: app/test/test_security*
 
 Compression API - EXPERIMENTAL
-M: Fan Zhang 
+M: Fan Zhang 
 M: Ashish Gupta 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/compressdev/
@@ -1057,19 +1057,19 @@ F: doc/guides/cryptodevs/octeontx.rst
 F: doc/guides/cryptodevs/features/octeontx.ini
 
 Crypto Scheduler
-M: Fan Zhang 
+M: Kai Ji 
 F: drivers/crypto/scheduler/
 F: doc/guides/cryptodevs/scheduler.rst
 
 Intel QuickAssist
-M: Fan Zhang 
+M: Kai Ji 
 F: drivers/crypto/qat/
 F: drivers/common/qat/
 F: doc/guides/cryptodevs/qat.rst
 F: doc/guides/cryptodevs/features/qat.ini
 
 IPsec MB
-M: Fan Zhang 
+M: Kai Ji 
 M: Pablo de Lara 
 F: drivers/crypto/ipsec_mb/
 F: doc/guides/cryptodevs/aesni_gcm.rst
@@ -1115,7 +1115,7 @@ F: doc/guides/cryptodevs/mlx5.rst
 F: doc/guides/cryptodevs/features/mlx5.ini
 
 Null Crypto
-M: Fan Zhang 
+M: Kai Ji 
 F: drivers/crypto/null/
 F: doc/guides/cryptodevs/null.rst
 F: doc/guides/cryptodevs/features/null.ini
@@ -1142,7 +1142,7 @@ F: doc/guides/cryptodevs/dpaa2_sec.rst
 F: doc/guides/cryptodevs/features/dpaa2_sec.ini
 
 OpenSSL
-M: Fan Zhang 
+M: Kai Ji 
 F: drivers/crypto/openssl/
 F: doc/guides/cryptodevs/openssl.rst
 F: doc/guides/cryptodevs/features/openssl.ini
@@ -1165,7 +1165,7 @@ F: doc/guides/compressdevs/octeontx.rst
 F: doc/guides/compressdevs/features/octeontx.ini
 
 Intel QuickAssist
-M: Fan Zhang 
+M: Kai Ji 
 F: drivers/compress/qat/
 F: drivers/common/qat/
 
@@ -1749,7 +1749,6 @@ F: examples/ethtool/
 F: doc/guides/sample_app_ug/ethtool.rst
 
 FIPS validation example
-M: Fan Zhang 
 M: Brian Dooley 
 F: examples/fips_validation/
 F: doc/guides/sample_app_ug/fips_validation.rst
-- 
2.34.1

[dpdk-dev] [PATCH v2 00/10] drivers/qat: isolate implementations of qat generations

2021-10-01 Thread Fan Zhang

This patchset introduces new qat driver structure and updates
existing symmetric crypto qat PMD.

The purpose of the change is to isolate QAT generation specific
implementations from one to another.

It is expected the changes to the specific generation driver
code does minimum impact to other generations' implementations.
Also adding the support to new features or new qat generation
hardware will have zero impact to existing functionalities.

Fan Zhang (10):
  common/qat: add gen specific data and function
  common/qat: add gen specific device implementation
  common/qat: add gen specific queue pair function
  common/qat: add gen specific queue implementation
  compress/qat: add gen specific data and function
  compress/qat: add gen specific implementation
  crypto/qat: unified device private data structure
  crypto/qat: add gen specific data and function
  crypto/qat: add gen specific implementation
  doc: update release note

 doc/guides/rel_notes/release_21_11.rst|4 +
 drivers/common/qat/dev/qat_dev_gen1.c |  255 
 drivers/common/qat/dev/qat_dev_gen2.c |   37 +
 drivers/common/qat/dev/qat_dev_gen3.c |   83 ++
 drivers/common/qat/dev/qat_dev_gen4.c |  301 
 drivers/common/qat/dev/qat_dev_gens.h |   58 +
 drivers/common/qat/meson.build|   15 +-
 .../qat/qat_adf/adf_transport_access_macros.h |1 +
 .../common/qat/qat_adf/icp_qat_hw_gen4_comp.h |  195 +++
 .../qat/qat_adf/icp_qat_hw_gen4_comp_defs.h   |  300 
 drivers/common/qat/qat_common.c   |8 +
 drivers/common/qat/qat_common.h   |   16 +-
 drivers/common/qat/qat_device.c   |  185 +--
 drivers/common/qat/qat_device.h   |   42 +-
 drivers/common/qat/qat_qp.c   |  664 -
 drivers/common/qat/qat_qp.h   |   74 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen1.c  |  177 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen2.c  |   30 +
 drivers/compress/qat/dev/qat_comp_pmd_gen3.c  |   30 +
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c  |  213 +++
 drivers/compress/qat/dev/qat_comp_pmd_gens.h  |   30 +
 drivers/compress/qat/qat_comp.c   |  101 +-
 drivers/compress/qat/qat_comp.h   |8 +-
 drivers/compress/qat/qat_comp_pmd.c   |  159 +--
 drivers/compress/qat/qat_comp_pmd.h   |   76 +
 drivers/crypto/qat/README |7 -
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c|   76 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c  |  224 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c  |  164 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c  |  125 ++
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h  |   36 +
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c |  283 
 drivers/crypto/qat/meson.build|   26 -
 drivers/crypto/qat/qat_asym_capabilities.h|   63 -
 drivers/crypto/qat/qat_asym_pmd.c |  276 +---
 drivers/crypto/qat/qat_asym_pmd.h |   55 +-
 drivers/crypto/qat/qat_crypto.c   |  172 +++
 drivers/crypto/qat/qat_crypto.h   |   91 ++
 drivers/crypto/qat/qat_sym_capabilities.h | 1248 -
 drivers/crypto/qat/qat_sym_pmd.c  |  428 +-
 drivers/crypto/qat/qat_sym_pmd.h  |   71 +-
 drivers/crypto/qat/qat_sym_session.c  |   15 +-
 42 files changed, 3715 insertions(+), 2707 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen1.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen2.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen3.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen4.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gens.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen1.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen2.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen3.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen4.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gens.h
 delete mode 100644 drivers/crypto/qat/README
 create mode 100644 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
 create mode 100644 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
 delete mode 100644 drivers/crypto/qat/meson.build
 delete mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
 create mode 100644 drivers/crypto/qat/qat_crypto.c
 create mode 100644 drivers/crypto/qat/qat_crypto.h
 delete mode 100644 drivers/crypto/qat/qat_sym_capabilities.h

-- 
2.25.1

[dpdk-dev] [PATCH v2 01/10] common/qat: add gen specific data and function

2021-10-01 Thread Fan Zhang

This patch adds the data structure and function prototypes for
different QAT generations.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/qat_common.c |  8 
 drivers/common/qat/qat_common.h | 16 ++--
 drivers/common/qat/qat_device.c |  4 
 drivers/common/qat/qat_device.h | 23 +++
 4 files changed, 45 insertions(+), 6 deletions(-)

diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c
index 5343a1451e..e813d5c165 100644
--- a/drivers/common/qat/qat_common.c
+++ b/drivers/common/qat/qat_common.c
@@ -6,6 +6,14 @@
 #include "qat_device.h"
 #include "qat_logs.h"
 
+/* Keep it the same ordering as enum qat_service_type */
+const char *qat_service_type_str[] = {
+   "asym",
+   "sym",
+   "comp",
+   "invalid"
+};
+
 int
 qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,
void *list_in, uint32_t data_len,
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index 23715085f4..55f1ab8611 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -15,20 +15,26 @@
 /* Intel(R) QuickAssist Technology device generation is enumerated
  * from one according to the generation of the device
  */
+
 enum qat_device_gen {
-   QAT_GEN1 = 1,
+   QAT_GEN1,
QAT_GEN2,
QAT_GEN3,
-   QAT_GEN4
+   QAT_GEN4,
+   QAT_N_GENS
 };
 
 enum qat_service_type {
-   QAT_SERVICE_ASYMMETRIC = 0,
+   QAT_SERVICE_ASYMMETRIC,
QAT_SERVICE_SYMMETRIC,
QAT_SERVICE_COMPRESSION,
-   QAT_SERVICE_INVALID
+   QAT_MAX_SERVICES
 };
 
+extern const char *qat_service_type_str[];
+
+#define QAT_SERVICE_INVALID(QAT_MAX_SERVICES)
+
 enum qat_svc_list {
QAT_SVC_UNUSED = 0,
QAT_SVC_CRYPTO = 1,
@@ -37,8 +43,6 @@ enum qat_svc_list {
QAT_SVC_ASYM = 4,
 };
 
-#define QAT_MAX_SERVICES   (QAT_SERVICE_INVALID)
-
 /**< Common struct for scatter-gather list operations */
 struct qat_flat_buf {
uint32_t len;
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 1b967cbcf7..e6b43c541f 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -13,6 +13,10 @@
 #include "adf_pf2vf_msg.h"
 #include "qat_pf2vf.h"
 
+/* Hardware device information per generation */
+struct qat_gen_hw_data qat_gen_config[QAT_N_GENS];
+struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[QAT_N_GENS];
+
 /* pv2vf data Gen 4*/
 struct qat_pf2vf_dev qat_pf2vf_gen4 = {
.pf2vf_offset = ADF_4XXXIOV_PF2VM_OFFSET,
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 228c057d1e..b8b5c387a3 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -21,6 +21,29 @@
 #define COMP_ENQ_THRESHOLD_NAME "qat_comp_enq_threshold"
 #define MAX_QP_THRESHOLD_SIZE  32
 
+/**
+ * Function prototypes for GENx specific device operations.
+ **/
+typedef int (*qat_dev_reset_ring_pairs_t)
+   (struct qat_pci_device *);
+typedef const struct rte_mem_resource* (*qat_dev_get_transport_bar_t)
+   (struct rte_pci_device *);
+typedef int (*qat_dev_get_misc_bar_t)
+   (struct rte_mem_resource **, struct rte_pci_device *);
+typedef int (*qat_dev_read_config_t)
+   (struct qat_pci_device *);
+typedef int (*qat_dev_get_extra_size_t)(void);
+
+struct qat_dev_hw_spec_funcs {
+   qat_dev_reset_ring_pairs_t  qat_dev_reset_ring_pairs;
+   qat_dev_get_transport_bar_t qat_dev_get_transport_bar;
+   qat_dev_get_misc_bar_t  qat_dev_get_misc_bar;
+   qat_dev_read_config_t   qat_dev_read_config;
+   qat_dev_get_extra_size_tqat_dev_get_extra_size;
+};
+
+extern struct qat_dev_hw_spec_funcs *qat_dev_hw_spec[];
+
 struct qat_dev_cmd_param {
const char *name;
uint16_t val;
-- 
2.25.1

[dpdk-dev] [PATCH v2 02/10] common/qat: add gen specific device implementation

2021-10-01 Thread Fan Zhang

This patch replaces the mixed QAT device configuration
implementation by separate files with shared or
individual implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c |  66 +
 drivers/common/qat/dev/qat_dev_gen2.c |  23 
 drivers/common/qat/dev/qat_dev_gen3.c |  23 
 drivers/common/qat/dev/qat_dev_gen4.c | 152 +
 drivers/common/qat/dev/qat_dev_gens.h |  34 +
 drivers/common/qat/meson.build|   4 +
 drivers/common/qat/qat_device.c   | 185 ++
 drivers/common/qat/qat_device.h   |   5 +-
 drivers/common/qat/qat_qp.c   |   3 +-
 9 files changed, 374 insertions(+), 121 deletions(-)
 create mode 100644 drivers/common/qat/dev/qat_dev_gen1.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen2.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen3.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gen4.c
 create mode 100644 drivers/common/qat/dev/qat_dev_gens.h

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
new file mode 100644
index 00..d9e75fe9e2
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+#define ADF_ARB_REG_SLOT   0x1000
+
+int
+qat_reset_ring_pairs_gen1(struct qat_pci_device *qat_pci_dev __rte_unused)
+{
+   /*
+* Ring pairs reset not supported on base, continue
+*/
+   return 0;
+}
+
+const struct rte_mem_resource *
+qat_dev_get_transport_bar_gen1(struct rte_pci_device *pci_dev)
+{
+   return &pci_dev->mem_resource[0];
+}
+
+int
+qat_dev_get_misc_bar_gen1(struct rte_mem_resource **mem_resource __rte_unused,
+   struct rte_pci_device *pci_dev __rte_unused)
+{
+   return -1;
+}
+
+int
+qat_dev_read_config_gen1(struct qat_pci_device *qat_dev __rte_unused)
+{
+   /*
+* Base generations do not have configuration,
+* but set this pointer anyway that we can
+* distinguish higher generations faulty set to NULL
+*/
+   return 0;
+}
+
+int
+qat_dev_get_extra_size_gen1(void)
+{
+   return 0;
+}
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen1 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen1_init)
+{
+   qat_dev_hw_spec[QAT_GEN1] = &qat_dev_hw_spec_gen1;
+   qat_gen_config[QAT_GEN1].dev_gen = QAT_GEN1;
+   qat_gen_config[QAT_GEN1].comp_num_im_bufs_required =
+   QAT_NUM_INTERM_BUFS_GEN1;
+}
diff --git a/drivers/common/qat/dev/qat_dev_gen2.c 
b/drivers/common/qat/dev/qat_dev_gen2.c
new file mode 100644
index 00..d3470ed6b8
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen2.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen2 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen2_init)
+{
+   qat_dev_hw_spec[QAT_GEN2] = &qat_dev_hw_spec_gen2;
+   qat_gen_config[QAT_GEN2].dev_gen = QAT_GEN2;
+}
diff --git a/drivers/common/qat/dev/qat_dev_gen3.c 
b/drivers/common/qat/dev/qat_dev_gen3.c
new file mode 100644
index 00..e4a66869d2
--- /dev/null
+++ b/drivers/common/qat/dev/qat_dev_gen3.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include "qat_device.h"
+#include "adf_transport_access_macros.h"
+#include "qat_dev_gens.h"
+
+#include 
+
+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen3 = {
+   .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
+   .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
+   .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
+   .qat_dev_read_config = qat_dev_read_config_gen1,
+   .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
+};
+
+RTE_INIT(qat_dev_gen_gen3_init)
+{
+   qat_dev_hw_spec[QAT_GEN3] = &qat_dev_hw_spec_gen3;
+

[dpdk-dev] [PATCH v2 03/10] common/qat: add gen specific queue pair function

2021-10-01 Thread Fan Zhang

This patch adds the queue pair data structure and function
prototypes for different QAT generations.

Signed-off-by: Fan Zhang 
---
 drivers/common/qat/qat_qp.c |  3 +++
 drivers/common/qat/qat_qp.h | 45 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index b8c6000e86..27994036b8 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -34,6 +34,9 @@
ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
(ADF_ARB_REG_SLOT * index), value)
 
+struct qat_qp_hw_spec_funcs*
+   qat_qp_hw_spec[QAT_N_GENS];
+
 __extension__
 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index e1627197fa..2de66b888b 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -8,6 +8,51 @@
 #include "adf_transport_access_macros.h"
 
 struct qat_pci_device;
+struct qat_qp_hw_data;
+struct qat_queue;
+struct qat_qp;
+
+/**
+ * Function prototypes for GENx specific queue pair operations.
+ **/
+typedef int (*qat_qp_rings_per_service_t)
+   (struct qat_pci_device *, enum qat_service_type);
+
+typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
+
+typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
+   rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
+   rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
+
+typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue 
*q);
+
+typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
+   uint32_t new_head);
+
+typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
+   struct qat_qp *);
+
+typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
+   struct qat_pci_device *dev, enum qat_service_type service_type,
+   uint16_t qp_id);
+
+struct qat_qp_hw_spec_funcs {
+   qat_qp_rings_per_service_t  qat_qp_rings_per_service;
+   qat_qp_build_ring_base_tqat_qp_build_ring_base;
+   qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable;
+   qat_qp_adf_arb_disable_tqat_qp_adf_arb_disable;
+   qat_qp_adf_configure_queues_t   qat_qp_adf_configure_queues;
+   qat_qp_csr_write_tail_t qat_qp_csr_write_tail;
+   qat_qp_csr_write_head_t qat_qp_csr_write_head;
+   qat_qp_csr_setup_t  qat_qp_csr_setup;
+   qat_qp_get_hw_data_tqat_qp_get_hw_data;
+};
+
+extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
 
 #define QAT_CSR_HEAD_WRITE_THRESH 32U
 /* number of requests to accumulate before writing head CSR */
-- 
2.25.1

[dpdk-dev] [PATCH v2 04/10] common/qat: add gen specific queue implementation

2021-10-01 Thread Fan Zhang

This patch replaces the mixed QAT queue pair configuration
implementation by separate files with shared or individual
implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c | 193 -
 drivers/common/qat/dev/qat_dev_gen2.c |  14 +
 drivers/common/qat/dev/qat_dev_gen3.c |  60 ++
 drivers/common/qat/dev/qat_dev_gen4.c | 157 -
 drivers/common/qat/dev/qat_dev_gens.h |  30 +-
 .../qat/qat_adf/adf_transport_access_macros.h |   1 +
 drivers/common/qat/qat_qp.c   | 664 +++---
 drivers/common/qat/qat_qp.h   |  29 +-
 drivers/crypto/qat/qat_sym_pmd.c  |  32 +-
 9 files changed, 709 insertions(+), 471 deletions(-)

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
index d9e75fe9e2..f1f43c17b1 100644
--- a/drivers/common/qat/dev/qat_dev_gen1.c
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -3,6 +3,7 @@
  */
 
 #include "qat_device.h"
+#include "qat_qp.h"
 #include "adf_transport_access_macros.h"
 #include "qat_dev_gens.h"
 
@@ -10,6 +11,195 @@
 
 #define ADF_ARB_REG_SLOT   0x1000
 
+#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
+   ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
+   (ADF_ARB_REG_SLOT * index), value)
+
+__extension__
+const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
+[ADF_MAX_QPS_ON_ANY_SERVICE] = {
+   /* queue pairs which provide an asymmetric crypto service */
+   [QAT_SERVICE_ASYMMETRIC] = {
+   {
+   .service_type = QAT_SERVICE_ASYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 0,
+   .rx_ring_num = 8,
+   .tx_msg_size = 64,
+   .rx_msg_size = 32,
+
+   }, {
+   .service_type = QAT_SERVICE_ASYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 1,
+   .rx_ring_num = 9,
+   .tx_msg_size = 64,
+   .rx_msg_size = 32,
+   }
+   },
+   /* queue pairs which provide a symmetric crypto service */
+   [QAT_SERVICE_SYMMETRIC] = {
+   {
+   .service_type = QAT_SERVICE_SYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 2,
+   .rx_ring_num = 10,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   },
+   {
+   .service_type = QAT_SERVICE_SYMMETRIC,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 3,
+   .rx_ring_num = 11,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }
+   },
+   /* queue pairs which provide a compression service */
+   [QAT_SERVICE_COMPRESSION] = {
+   {
+   .service_type = QAT_SERVICE_COMPRESSION,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 6,
+   .rx_ring_num = 14,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }, {
+   .service_type = QAT_SERVICE_COMPRESSION,
+   .hw_bundle_num = 0,
+   .tx_ring_num = 7,
+   .rx_ring_num = 15,
+   .tx_msg_size = 128,
+   .rx_msg_size = 32,
+   }
+   }
+};
+
+const struct qat_qp_hw_data *
+qat_qp_get_hw_data_gen1(struct qat_pci_device *dev __rte_unused,
+   enum qat_service_type service_type, uint16_t qp_id)
+{
+   return qat_gen1_qps[service_type] + qp_id;
+}
+
+int
+qat_qp_rings_per_service_gen1(struct qat_pci_device *qat_dev,
+   enum qat_service_type service)
+{
+   int i = 0, count = 0;
+
+   for (i = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++) {
+   const struct qat_qp_hw_data *hw_qps =
+   qat_qp_get_hw_data(qat_dev, service, i);
+   if (hw_qps->service_type == service)
+   count++;
+   }
+
+   return count;
+}
+
+void
+qat_qp_csr_build_ring_base_gen1(void *io_addr,
+   struct qat_queue *queue)
+{
+   uint64_t queue_base;
+
+   queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
+   queue->queue_size);
+   WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
+   queue->hw_queue_number, queue_base);
+}
+
+void
+qat_qp_adf_arb_enable_gen1(const struct qat_queue *txq,
+

[dpdk-dev] [PATCH v2 05/10] compress/qat: add gen specific data and function

2021-10-01 Thread Fan Zhang

This patch adds the compression data structure and function
prototypes for different QAT generations.

Signed-off-by: Adam Dybkowski 
Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/dev/qat_dev_gen1.c |   2 -
 .../common/qat/qat_adf/icp_qat_hw_gen4_comp.h | 195 
 .../qat/qat_adf/icp_qat_hw_gen4_comp_defs.h   | 300 ++
 drivers/common/qat/qat_device.h   |   7 -
 drivers/compress/qat/qat_comp.c   | 101 +++---
 drivers/compress/qat/qat_comp.h   |   8 +-
 drivers/compress/qat/qat_comp_pmd.c   | 159 --
 drivers/compress/qat/qat_comp_pmd.h   |  76 +
 8 files changed, 674 insertions(+), 174 deletions(-)
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
 create mode 100644 drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h

diff --git a/drivers/common/qat/dev/qat_dev_gen1.c 
b/drivers/common/qat/dev/qat_dev_gen1.c
index f1f43c17b1..ed4c4a2c03 100644
--- a/drivers/common/qat/dev/qat_dev_gen1.c
+++ b/drivers/common/qat/dev/qat_dev_gen1.c
@@ -252,6 +252,4 @@ RTE_INIT(qat_dev_gen_gen1_init)
qat_qp_hw_spec[QAT_GEN1] = &qat_qp_hw_spec_gen1;
qat_dev_hw_spec[QAT_GEN1] = &qat_dev_hw_spec_gen1;
qat_gen_config[QAT_GEN1].dev_gen = QAT_GEN1;
-   qat_gen_config[QAT_GEN1].comp_num_im_bufs_required =
-   QAT_NUM_INTERM_BUFS_GEN1;
 }
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h 
b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
new file mode 100644
index 00..ec69dc7105
--- /dev/null
+++ b/drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#ifndef _ICP_QAT_HW_GEN4_COMP_H_
+#define _ICP_QAT_HW_GEN4_COMP_H_
+
+#include "icp_qat_fw.h"
+#include "icp_qat_hw_gen4_comp_defs.h"
+
+struct icp_qat_hw_comp_20_config_csr_lower {
+   icp_qat_hw_comp_20_extended_delay_match_mode_t edmm;
+   icp_qat_hw_comp_20_hw_comp_format_t algo;
+   icp_qat_hw_comp_20_search_depth_t sd;
+   icp_qat_hw_comp_20_hbs_control_t hbs;
+   icp_qat_hw_comp_20_abd_t abd;
+   icp_qat_hw_comp_20_lllbd_ctrl_t lllbd;
+   icp_qat_hw_comp_20_min_match_control_t mmctrl;
+   icp_qat_hw_comp_20_skip_hash_collision_t hash_col;
+   icp_qat_hw_comp_20_skip_hash_update_t hash_update;
+   icp_qat_hw_comp_20_byte_skip_t skip_ctrl;
+};
+
+static inline uint32_t ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(
+   struct icp_qat_hw_comp_20_config_csr_lower csr)
+{
+   uint32_t val32 = 0;
+
+   QAT_FIELD_SET(val32, csr.algo,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
+
+   QAT_FIELD_SET(val32, csr.sd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
+
+   QAT_FIELD_SET(val32, csr.edmm,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
+
+   QAT_FIELD_SET(val32, csr.hbs,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
+
+   QAT_FIELD_SET(val32, csr.lllbd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
+
+   QAT_FIELD_SET(val32, csr.mmctrl,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
+
+   QAT_FIELD_SET(val32, csr.hash_col,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
+
+   QAT_FIELD_SET(val32, csr.hash_update,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
+
+   QAT_FIELD_SET(val32, csr.skip_ctrl,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
+
+   QAT_FIELD_SET(val32, csr.abd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
+
+   QAT_FIELD_SET(val32, csr.lllbd,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
+   ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
+
+   return rte_bswap32(val32);
+}
+
+struct icp_qat_hw_comp_20_config_csr_upper {
+   icp_qat_hw_comp_20_scb_control_t scb_ctrl;
+   icp_qat_hw_comp_20_rmb_control_t rmb_ctrl;
+   icp_qat_hw_comp_20_som_control_t som_ctrl;
+   icp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl;
+   icp_qat_hw_comp_20_scb_unlo

[dpdk-dev] [PATCH v2 06/10] compress/qat: add gen specific implementation

2021-10-01 Thread Fan Zhang

This patch replaces the mixed QAT compression support
implementation by separate files with shared or individual
implementation for specific QAT generation.

Signed-off-by: Adam Dybkowski 
Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   4 +-
 drivers/compress/qat/dev/qat_comp_pmd_gen1.c | 177 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen2.c |  30 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen3.c |  30 +++
 drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 213 +++
 drivers/compress/qat/dev/qat_comp_pmd_gens.h |  30 +++
 6 files changed, 483 insertions(+), 1 deletion(-)
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen1.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen2.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen3.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gen4.c
 create mode 100644 drivers/compress/qat/dev/qat_comp_pmd_gens.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 532e0fabb3..8a1c6d64e8 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -62,7 +62,9 @@ includes += include_directories(
 )
 
 if qat_compress
-foreach f: ['qat_comp_pmd.c', 'qat_comp.c']
+foreach f: ['qat_comp_pmd.c', 'qat_comp.c',
+'dev/qat_comp_pmd_gen1.c', 'dev/qat_comp_pmd_gen2.c',
+'dev/qat_comp_pmd_gen3.c', 'dev/qat_comp_pmd_gen4.c']
 sources += files(join_paths(qat_compress_relpath, f))
 endforeach
 endif
diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen1.c 
b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c
new file mode 100644
index 00..0e1afe544a
--- /dev/null
+++ b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include "qat_comp_pmd.h"
+#include "qat_comp.h"
+#include "qat_comp_pmd_gens.h"
+
+#define QAT_NUM_INTERM_BUFS_GEN1 12
+
+const struct rte_compressdev_capabilities qat_gen1_comp_capabilities[] = {
+   {/* COMPRESSION - deflate */
+.algo = RTE_COMP_ALGO_DEFLATE,
+.comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
+   RTE_COMP_FF_CRC32_CHECKSUM |
+   RTE_COMP_FF_ADLER32_CHECKSUM |
+   RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
+   RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
+   RTE_COMP_FF_HUFFMAN_FIXED |
+   RTE_COMP_FF_HUFFMAN_DYNAMIC |
+   RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
+   RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
+   RTE_COMP_FF_OOP_LB_IN_SGL_OUT |
+   RTE_COMP_FF_STATEFUL_DECOMPRESSION,
+.window_size = {.min = 15, .max = 15, .increment = 0} },
+   {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
+
+static int
+qat_comp_dev_config_gen1(struct rte_compressdev *dev,
+   struct rte_compressdev_config *config)
+{
+   struct qat_comp_dev_private *comp_dev = dev->data->dev_private;
+
+   if (RTE_PMD_QAT_COMP_IM_BUFFER_SIZE == 0) {
+   QAT_LOG(WARNING,
+   "RTE_PMD_QAT_COMP_IM_BUFFER_SIZE = 0 in config file, so"
+   " QAT device can't be used for Dynamic Deflate. "
+   "Did you really intend to do this?");
+   } else {
+   comp_dev->interm_buff_mz =
+   qat_comp_setup_inter_buffers(comp_dev,
+   RTE_PMD_QAT_COMP_IM_BUFFER_SIZE);
+   if (comp_dev->interm_buff_mz == NULL)
+   return -ENOMEM;
+   }
+
+   return qat_comp_dev_config(dev, config);
+}
+
+struct rte_compressdev_ops qat_comp_ops_gen1 = {
+
+   /* Device related operations */
+   .dev_configure  = qat_comp_dev_config_gen1,
+   .dev_start  = qat_comp_dev_start,
+   .dev_stop   = qat_comp_dev_stop,
+   .dev_close  = qat_comp_dev_close,
+   .dev_infos_get  = qat_comp_dev_info_get,
+
+   .stats_get  = qat_comp_stats_get,
+   .stats_reset= qat_comp_stats_reset,
+   .queue_pair_setup   = qat_comp_qp_setup,
+   .queue_pair_release = qat_comp_qp_release,
+
+   /* Compression related operations */
+   .private_xform_create   = qat_comp_private_xform_create,
+   .private_xform_free = qat_comp_private_xform_free,
+   .stream_create  = qat_comp_stream_create,
+   .stream_free= qat_comp_stream_free
+};
+
+struct qat_comp_capabilit

[dpdk-dev] [PATCH v2 07/10] crypto/qat: unified device private data structure

2021-10-01 Thread Fan Zhang

This patch unifies the QAT symmetric and asymmetric device
private data structures and functions.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   2 +-
 drivers/common/qat/qat_device.h  |   7 +-
 drivers/crypto/qat/qat_asym_pmd.c| 214 ---
 drivers/crypto/qat/qat_asym_pmd.h|  29 +---
 drivers/crypto/qat/qat_crypto.c  | 172 ++
 drivers/crypto/qat/qat_crypto.h  |  78 +
 drivers/crypto/qat/qat_sym_pmd.c | 250 +--
 drivers/crypto/qat/qat_sym_pmd.h |  21 +--
 drivers/crypto/qat/qat_sym_session.c |  15 +-
 9 files changed, 342 insertions(+), 446 deletions(-)
 create mode 100644 drivers/crypto/qat/qat_crypto.c
 create mode 100644 drivers/crypto/qat/qat_crypto.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 8a1c6d64e8..29fd0168ea 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -71,7 +71,7 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c']
+'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']
 sources += files(join_paths(qat_crypto_relpath, f))
 endforeach
 deps += ['security']
diff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h
index 421c8299e0..5d5c64e168 100644
--- a/drivers/common/qat/qat_device.h
+++ b/drivers/common/qat/qat_device.h
@@ -76,8 +76,7 @@ struct qat_device_info {
 
 extern struct qat_device_info qat_pci_devs[];
 
-struct qat_sym_dev_private;
-struct qat_asym_dev_private;
+struct qat_cryptodev_private;
 struct qat_comp_dev_private;
 
 /*
@@ -106,14 +105,14 @@ struct qat_pci_device {
/**< links to qps set up for each service, index same as on API */
 
/* Data relating to symmetric crypto service */
-   struct qat_sym_dev_private *sym_dev;
+   struct qat_cryptodev_private *sym_dev;
/**< link back to cryptodev private data */
 
int qat_sym_driver_id;
/**< Symmetric driver id used by this device */
 
/* Data relating to asymmetric crypto service */
-   struct qat_asym_dev_private *asym_dev;
+   struct qat_cryptodev_private *asym_dev;
/**< link back to cryptodev private data */
 
int qat_asym_driver_id;
diff --git a/drivers/crypto/qat/qat_asym_pmd.c 
b/drivers/crypto/qat/qat_asym_pmd.c
index e91bb0d317..63e61fa322 100644
--- a/drivers/crypto/qat/qat_asym_pmd.c
+++ b/drivers/crypto/qat/qat_asym_pmd.c
@@ -6,6 +6,7 @@
 
 #include "qat_logs.h"
 
+#include "qat_crypto.h"
 #include "qat_asym.h"
 #include "qat_asym_pmd.h"
 #include "qat_sym_capabilities.h"
@@ -18,190 +19,45 @@ static const struct rte_cryptodev_capabilities 
qat_gen1_asym_capabilities[] = {
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
-static int qat_asym_qp_release(struct rte_cryptodev *dev,
-  uint16_t queue_pair_id);
-
-static int qat_asym_dev_config(__rte_unused struct rte_cryptodev *dev,
-  __rte_unused struct rte_cryptodev_config *config)
-{
-   return 0;
-}
-
-static int qat_asym_dev_start(__rte_unused struct rte_cryptodev *dev)
-{
-   return 0;
-}
-
-static void qat_asym_dev_stop(__rte_unused struct rte_cryptodev *dev)
-{
-
-}
-
-static int qat_asym_dev_close(struct rte_cryptodev *dev)
-{
-   int i, ret;
-
-   for (i = 0; i < dev->data->nb_queue_pairs; i++) {
-   ret = qat_asym_qp_release(dev, i);
-   if (ret < 0)
-   return ret;
-   }
-
-   return 0;
-}
-
-static void qat_asym_dev_info_get(struct rte_cryptodev *dev,
- struct rte_cryptodev_info *info)
-{
-   struct qat_asym_dev_private *internals = dev->data->dev_private;
-   struct qat_pci_device *qat_dev = internals->qat_dev;
-
-   if (info != NULL) {
-   info->max_nb_queue_pairs = qat_qps_per_service(qat_dev,
-   QAT_SERVICE_ASYMMETRIC);
-   info->feature_flags = dev->feature_flags;
-   info->capabilities = internals->qat_dev_capabilities;
-   info->driver_id = qat_asym_driver_id;
-   /* No limit of number of sessions */
-   info->sym.max_nb_sessions = 0;
-   }
-}
-
-static void qat_asym_stats_get(struct rte_cryptodev *dev,
-  struct rte_cryptodev_stats *stats)
-{
-   struct qat_common_stats qat_stats = {0};
-   struct qat_asym_dev_private *qat_priv;
-
-   if (stats == NULL || dev == NULL) {
-   QAT_LOG(ERR, "invalid ptr:

[dpdk-dev] [PATCH v2 08/10] crypto/qat: add gen specific data and function

2021-10-01 Thread Fan Zhang

This patch adds the symmetric and asymmetric crypto data
structure and function prototypes for different QAT
generations.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/crypto/qat/README  |7 -
 drivers/crypto/qat/meson.build |   26 -
 drivers/crypto/qat/qat_asym_capabilities.h |   63 -
 drivers/crypto/qat/qat_asym_pmd.c  |   62 +-
 drivers/crypto/qat/qat_asym_pmd.h  |   25 +
 drivers/crypto/qat/qat_crypto.h|   16 +
 drivers/crypto/qat/qat_sym_capabilities.h  | 1248 
 drivers/crypto/qat/qat_sym_pmd.c   |  186 +--
 drivers/crypto/qat/qat_sym_pmd.h   |   52 +-
 9 files changed, 161 insertions(+), 1524 deletions(-)
 delete mode 100644 drivers/crypto/qat/README
 delete mode 100644 drivers/crypto/qat/meson.build
 delete mode 100644 drivers/crypto/qat/qat_asym_capabilities.h
 delete mode 100644 drivers/crypto/qat/qat_sym_capabilities.h

diff --git a/drivers/crypto/qat/README b/drivers/crypto/qat/README
deleted file mode 100644
index 444ae605f0..00
--- a/drivers/crypto/qat/README
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2015-2018 Intel Corporation
-
-Makefile for crypto QAT PMD is in common/qat directory.
-The build for the QAT driver is done from there as only one library is built 
for the
-whole QAT pci device and that library includes all the services (crypto, 
compression)
-which are enabled on the device.
diff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build
deleted file mode 100644
index b3b2d17258..00
--- a/drivers/crypto/qat/meson.build
+++ /dev/null
@@ -1,26 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017-2018 Intel Corporation
-
-# this does not build the QAT driver, instead that is done in the compression
-# driver which comes later. Here we just add our sources files to the list
-build = false
-reason = '' # sentinal value to suppress printout
-dep = dependency('libcrypto', required: false, method: 'pkg-config')
-qat_includes += include_directories('.')
-qat_deps += 'cryptodev'
-qat_deps += 'net'
-qat_deps += 'security'
-if dep.found()
-# Add our sources files to the list
-qat_sources += files(
-'qat_asym.c',
-'qat_asym_pmd.c',
-'qat_sym.c',
-'qat_sym_hw_dp.c',
-'qat_sym_pmd.c',
-'qat_sym_session.c',
-   )
-qat_ext_deps += dep
-qat_cflags += '-DBUILD_QAT_SYM'
-qat_cflags += '-DBUILD_QAT_ASYM'
-endif
diff --git a/drivers/crypto/qat/qat_asym_capabilities.h 
b/drivers/crypto/qat/qat_asym_capabilities.h
deleted file mode 100644
index 523b4da6d3..00
--- a/drivers/crypto/qat/qat_asym_capabilities.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019 Intel Corporation
- */
-
-#ifndef _QAT_ASYM_CAPABILITIES_H_
-#define _QAT_ASYM_CAPABILITIES_H_
-
-#define QAT_BASE_GEN1_ASYM_CAPABILITIES
\
-   {   /* modexp */
\
-   .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
\
-   {.asym = {  
\
-   .xform_capa = { 
\
-   .xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,  
\
-   .op_types = 0,  
\
-   {   
\
-   .modlen = { 
\
-   .min = 1,   
\
-   .max = 512, 
\
-   .increment = 1  
\
-   }, }
\
-   }   
\
-   },  
\
-   }   
\
-   },  
\
-   {   /* modinv */
\
-   .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
\
-   {.asym = {  
\
-   .xform_capa = {

[dpdk-dev] [PATCH v2 09/10] crypto/qat: add gen specific implementation

2021-10-01 Thread Fan Zhang

This patch replaces the mixed QAT symmetric and asymmetric
support implementation by separate files with shared or
individual implementation for specific QAT generation.

Signed-off-by: Arek Kusztal 
Signed-off-by: Fan Zhang 
Signed-off-by: Kai Ji 
---
 drivers/common/qat/meson.build   |   7 +-
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   |  76 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 224 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 164 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 125 
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  36 +++
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 283 +++
 drivers/crypto/qat/qat_asym_pmd.h|   1 +
 drivers/crypto/qat/qat_crypto.h  |   3 -
 9 files changed, 915 insertions(+), 4 deletions(-)
 create mode 100644 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
 create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
 create mode 100644 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 29fd0168ea..ce9959d103 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -71,7 +71,12 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c']
+'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',
+   'dev/qat_sym_pmd_gen1.c',
+'dev/qat_asym_pmd_gen1.c',
+'dev/qat_crypto_pmd_gen2.c',
+'dev/qat_crypto_pmd_gen3.c',
+'dev/qat_crypto_pmd_gen4.c']
 sources += files(join_paths(qat_crypto_relpath, f))
 endforeach
 deps += ['security']
diff --git a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c 
b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
new file mode 100644
index 00..61250fe433
--- /dev/null
+++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017-2021 Intel Corporation
+ */
+
+#include 
+#include 
+#include "qat_asym.h"
+#include "qat_crypto.h"
+#include "qat_crypto_pmd_gens.h"
+#include "qat_pke_functionality_arrays.h"
+
+struct rte_cryptodev_ops qat_asym_crypto_ops_gen1 = {
+   /* Device related operations */
+   .dev_configure  = qat_cryptodev_config,
+   .dev_start  = qat_cryptodev_start,
+   .dev_stop   = qat_cryptodev_stop,
+   .dev_close  = qat_cryptodev_close,
+   .dev_infos_get  = qat_cryptodev_info_get,
+
+   .stats_get  = qat_cryptodev_stats_get,
+   .stats_reset= qat_cryptodev_stats_reset,
+   .queue_pair_setup   = qat_cryptodev_qp_setup,
+   .queue_pair_release = qat_cryptodev_qp_release,
+
+   /* Crypto related operations */
+   .asym_session_get_size  = qat_asym_session_get_private_size,
+   .asym_session_configure = qat_asym_session_configure,
+   .asym_session_clear = qat_asym_session_clear
+};
+
+static struct rte_cryptodev_capabilities qat_asym_crypto_caps_gen1[] = {
+   QAT_ASYM_CAP(MODEX, \
+   0, 1, 512, 1), \
+   QAT_ASYM_CAP(MODINV, \
+   0, 1, 512, 1), \
+   QAT_ASYM_CAP(RSA, \
+   ((1 << RTE_CRYPTO_ASYM_OP_SIGN) | \
+   (1 << RTE_CRYPTO_ASYM_OP_VERIFY) | \
+   (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) | \
+   (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)), \
+   64, 512, 64),
+   RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+
+struct qat_capabilities_info
+qat_asym_crypto_cap_get_gen1(struct qat_pci_device *qat_dev __rte_unused)
+{
+   struct qat_capabilities_info capa_info;
+   capa_info.data = qat_asym_crypto_caps_gen1;
+   capa_info.size = sizeof(qat_asym_crypto_caps_gen1);
+   return capa_info;
+}
+
+uint64_t
+qat_asym_crypto_feature_flags_get_gen1(
+   struct qat_pci_device *qat_dev __rte_unused)
+{
+   uint64_t feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
+   RTE_CRYPTODEV_FF_HW_ACCELERATED |
+   RTE_CRYPTODEV_FF_ASYM_SESSIONLESS |
+   RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_EXP |
+   RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
+
+   return feature_flags;
+}
+
+RTE_INIT(qat_asym_crypto_gen1_init)
+{
+   qat_asym_gen_dev_ops[QAT_GEN1].c

[dpdk-dev] [PATCH v2 10/10] doc: update release note

2021-10-01 Thread Fan Zhang

This patch updates the release note to describe qat refactor
changes made.

Signed-off-by: Fan Zhang 
---
 doc/guides/rel_notes/release_21_11.rst | 4 
 1 file changed, 4 insertions(+)

diff --git a/doc/guides/rel_notes/release_21_11.rst 
b/doc/guides/rel_notes/release_21_11.rst
index 3ade7fe5ac..02a61be76b 100644
--- a/doc/guides/rel_notes/release_21_11.rst
+++ b/doc/guides/rel_notes/release_21_11.rst
@@ -157,6 +157,10 @@ API Changes
   the crypto/security operation. This field will be used to communicate
   events such as soft expiry with IPsec in lookaside mode.
 
+* common/qat: QAT PMD is refactored to divide generation specific control
+  path code into dedicated files. This change also applies qat compression,
+  qat symmetric crypto, and qat asymmetric crypto.
+
 
 ABI Changes
 ---
-- 
2.25.1

[PATCH] maintainers: update for crypto and compressdev

2022-11-08 Thread Fan Zhang

Update email address.

Signed-off-by: Fan Zhang 
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1c9922123e..536e82fd4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -441,7 +441,7 @@ F: doc/guides/sample_app_ug/bbdev_app.rst
 
 Crypto API
 M: Akhil Goyal 
-M: Fan Zhang 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/cryptodev/
 F: app/test/test_cryptodev*
@@ -455,7 +455,7 @@ F: doc/guides/prog_guide/rte_security.rst
 F: app/test/test_security*
 
 Compression API - EXPERIMENTAL
-M: Fan Zhang 
+M: Fan Zhang 
 M: Ashish Gupta 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/compressdev/
-- 
2.25.1

[PATCH] cryptodev: fix sym session mempool creation description

2023-01-06 Thread Fan Zhang

After the session mempool creation API is changed, some
description is no longer valid. This patch fixes the
descriptions in both API comment and the programmer's guide.

Fixes: bdce2564dbf7 ("cryptodev: rework session framework")
Cc: gak...@marvell.com

Signed-off-by: Fan Zhang 
---
 doc/guides/prog_guide/cryptodev_lib.rst   |  41 +-
 .../prog_guide/img/cryptodev_sym_sess.svg | 417 --
 lib/cryptodev/rte_cryptodev.h |  17 +-
 3 files changed, 26 insertions(+), 449 deletions(-)
 delete mode 100644 doc/guides/prog_guide/img/cryptodev_sym_sess.svg

diff --git a/doc/guides/prog_guide/cryptodev_lib.rst 
b/doc/guides/prog_guide/cryptodev_lib.rst
index 01aad842a9..6963229898 100644
--- a/doc/guides/prog_guide/cryptodev_lib.rst
+++ b/doc/guides/prog_guide/cryptodev_lib.rst
@@ -499,37 +499,28 @@ a flow. Crypto sessions cache this immutable data in a 
optimal way for the
 underlying PMD and this allows further acceleration of the offload of
 Crypto workloads.
 
-.. figure:: img/cryptodev_sym_sess.*
-
 The Crypto device framework provides APIs to create session mempool and 
allocate
 and initialize sessions for crypto devices, where sessions are mempool objects.
 The application has to use ``rte_cryptodev_sym_session_pool_create()`` to
-create the session header mempool that creates a mempool with proper element
-size automatically and stores necessary information for safely accessing the
-session in the mempool's private data field.
-
-To create a mempool for storing session private data, the application has two
-options. The first is to create another mempool with elt size equal to or
-bigger than the maximum session private data size of all crypto devices that
-will share the same session header. The creation of the mempool shall use the
-traditional ``rte_mempool_create()`` with the correct ``elt_size``. The other
-option is to change the ``elt_size`` parameter in
-``rte_cryptodev_sym_session_pool_create()`` to the correct value. The first
-option is more complex to implement but may result in better memory usage as
-a session header normally takes smaller memory footprint as the session private
-data.
+create the session mempool header and the private data with the size specified
+by the user through the ``elt_size`` parameter in the function. The session
+private data is for the driver to initialize and access during crypto 
operations,
+hence the ``elt_size`` should be big enough for all drivers that will share 
this
+mempool. To obtain the proper session private data size of a crypto device, the
+user can call ``rte_cryptodev_sym_get_private_session_size()`` function. In 
case
+of heterogeneous crypto devices will share the same session mempool, the 
maximum
+session private data size of them should be passed.
 
 Once the session mempools have been created, 
``rte_cryptodev_sym_session_create()``
-is used to allocate an uninitialized session from the given mempool.
-The session then must be initialized using ``rte_cryptodev_sym_session_init()``
-for each of the required crypto devices. A symmetric transform chain
-is used to specify the operation and its parameters. See the section below for
-details on transforms.
+is used to allocate and initialize the session from the given mempool. The
+created session can ONLY be used by the crypto devices sharing the same driver 
ID
+as the device ID passed into the function as the parameter. In addition, a 
symmetric
+transform chain is used to specify the operation and its parameters.
+See the section below for details on transforms.
 
-When a session is no longer used, user must call 
``rte_cryptodev_sym_session_clear()``
-for each of the crypto devices that are using the session, to free all driver
-private session data. Once this is done, session should be freed using
-``rte_cryptodev_sym_session_free`` which returns them to their mempool.
+When a session is no longer used, user must call 
``rte_cryptodev_sym_session_free()``
+to uninitialize the session data and return the session back to the mempool it
+belongs.
 
 
 Transforms and Transform Chaining
diff --git a/doc/guides/prog_guide/img/cryptodev_sym_sess.svg 
b/doc/guides/prog_guide/img/cryptodev_sym_sess.svg
deleted file mode 100644
index 9b522458c8..00
--- a/doc/guides/prog_guide/img/cryptodev_sym_sess.svg
+++ /dev/null
@@ -1,417 +0,0 @@
-
-
-
-http://purl.org/dc/elements/1.1/";
-   xmlns:cc="http://creativecommons.org/ns#";
-   xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#";
-   xmlns:svg="http://www.w3.org/2000/svg";
-   xmlns="http://www.w3.org/2000/svg";
-   xmlns:xlink="http://www.w3.org/1999/xlink";
-   xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd";
-   xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape";
-   width="4.8933434in"
-   height="3.8972795in"
-   viewBox="0 0 352.31955 280.60496&

[dpdk-dev] cryptodev: change raw data path dequeue API

2021-03-16 Thread Fan Zhang

This patch changes the experimental raw data path dequeue burst API.
Originally the API enforces the user to provide callback function
to get maximum dequeue count. This change gives the user one more
option to pass directly the expected dequeue count.

Signed-off-by: Fan Zhang 
---
 app/test/test_cryptodev.c  | 8 +---
 doc/guides/rel_notes/release_21_05.rst | 2 ++
 drivers/crypto/qat/qat_sym_hw_dp.c | 4 +++-
 lib/librte_cryptodev/rte_cryptodev.c   | 5 +++--
 lib/librte_cryptodev/rte_cryptodev.h   | 8 
 5 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index f91debc16..a91054742 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -162,12 +162,6 @@ ceil_byte_length(uint32_t num_bits)
return (num_bits >> 3);
 }
 
-static uint32_t
-get_raw_dp_dequeue_count(void *user_data __rte_unused)
-{
-   return 1;
-}
-
 static void
 post_process_raw_dp_op(void *user_data,uint32_t index __rte_unused,
uint8_t is_op_success)
@@ -345,7 +339,7 @@ process_sym_raw_dp_op(uint8_t dev_id, uint16_t qp_id,
n = n_success = 0;
while (count++ < MAX_RAW_DEQUEUE_COUNT && n == 0) {
n = rte_cryptodev_raw_dequeue_burst(ctx,
-   get_raw_dp_dequeue_count, post_process_raw_dp_op,
+   NULL, 1, post_process_raw_dp_op,
(void **)&ret_op, 0, &n_success,
&dequeue_status);
if (dequeue_status < 0) {
diff --git a/doc/guides/rel_notes/release_21_05.rst 
b/doc/guides/rel_notes/release_21_05.rst
index 21dc6d234..b9ca0cc30 100644
--- a/doc/guides/rel_notes/release_21_05.rst
+++ b/doc/guides/rel_notes/release_21_05.rst
@@ -130,6 +130,8 @@ ABI Changes
 
 * No ABI change that would break compatibility with 20.11.
 
+* cryptodev: the function ``rte_cryptodev_raw_dequeue_burst`` is added a
+  parameter ``max_nb_to_dequeue`` to give user a more flexible dequeue control.
 
 Known Issues
 
diff --git a/drivers/crypto/qat/qat_sym_hw_dp.c 
b/drivers/crypto/qat/qat_sym_hw_dp.c
index 01afb883e..e075f3ec2 100644
--- a/drivers/crypto/qat/qat_sym_hw_dp.c
+++ b/drivers/crypto/qat/qat_sym_hw_dp.c
@@ -707,6 +707,7 @@ qat_sym_dp_enqueue_chain_jobs(void *qp_data, uint8_t 
*drv_ctx,
 static __rte_always_inline uint32_t
 qat_sym_dp_dequeue_burst(void *qp_data, uint8_t *drv_ctx,
rte_cryptodev_raw_get_dequeue_count_t get_dequeue_count,
+   uint32_t max_nb_to_dequeue,
rte_cryptodev_raw_post_dequeue_t post_dequeue,
void **out_user_data, uint8_t is_user_data_array,
uint32_t *n_success_jobs, int *return_status)
@@ -736,7 +737,8 @@ qat_sym_dp_dequeue_burst(void *qp_data, uint8_t *drv_ctx,
 
resp_opaque = (void *)(uintptr_t)resp->opaque_data;
/* get the dequeue count */
-   n = get_dequeue_count(resp_opaque);
+   n = get_dequeue_count != NULL ? get_dequeue_count(resp_opaque) :
+   max_nb_to_dequeue;
if (unlikely(n == 0))
return 0;
 
diff --git a/lib/librte_cryptodev/rte_cryptodev.c 
b/lib/librte_cryptodev/rte_cryptodev.c
index 40f55a3cd..0c16b04f8 100644
--- a/lib/librte_cryptodev/rte_cryptodev.c
+++ b/lib/librte_cryptodev/rte_cryptodev.c
@@ -2232,13 +2232,14 @@ rte_cryptodev_raw_enqueue_done(struct 
rte_crypto_raw_dp_ctx *ctx,
 uint32_t
 rte_cryptodev_raw_dequeue_burst(struct rte_crypto_raw_dp_ctx *ctx,
rte_cryptodev_raw_get_dequeue_count_t get_dequeue_count,
+   uint32_t max_nb_to_dequeue,
rte_cryptodev_raw_post_dequeue_t post_dequeue,
void **out_user_data, uint8_t is_user_data_array,
uint32_t *n_success_jobs, int *status)
 {
return (*ctx->dequeue_burst)(ctx->qp_data, ctx->drv_ctx_data,
-   get_dequeue_count, post_dequeue, out_user_data,
-   is_user_data_array, n_success_jobs, status);
+   get_dequeue_count, max_nb_to_dequeue, post_dequeue,
+   out_user_data, is_user_data_array, n_success_jobs, status);
 }
 
 int
diff --git a/lib/librte_cryptodev/rte_cryptodev.h 
b/lib/librte_cryptodev/rte_cryptodev.h
index ae34f33f6..b2a125511 100644
--- a/lib/librte_cryptodev/rte_cryptodev.h
+++ b/lib/librte_cryptodev/rte_cryptodev.h
@@ -1546,6 +1546,9 @@ typedef void (*rte_cryptodev_raw_post_dequeue_t)(void 
*user_data,
  * @param  drv_ctx Driver specific context data.
  * @param  get_dequeue_count   User provided callback function to
  * obtain dequeue operation count.
+ * @param  max_nb_to_dequeue   When get_dequeue_count is NULL this
+ * value is used to pass the maximum
+ * number of operations to be dequeued.
  * @param  post_dequeueUser provided callback function to
  *

[PATCH 2/3] crypto/scheduler: use unified session

2022-08-29 Thread Fan Zhang

This patch updates the scheduler PMD to use unified session
data structure. Previously thanks to the private session
array in cryptodev sym session there are no necessary
change needed for scheduler PMD other than the way ops
are enqueued/dequeued. The patch inherits the same design
in the original session data structure to the scheduler PMD
so the cryptodev sym session can be as a linear buffer for
both session header and driver private data.

With the change there are inevitable extra cost on both memory
(64 bytes per session per driver type) and cycle count (set
the correct session for each cop based on the worker before
enqueue, and retrieve the original session after dequeue).

Signed-off-by: Fan Zhang 
---
 app/test/test_cryptodev.c |   4 +-
 drivers/crypto/scheduler/scheduler_failover.c |  19 ++-
 .../crypto/scheduler/scheduler_multicore.c|  17 +++
 .../scheduler/scheduler_pkt_size_distr.c  |  84 +---
 drivers/crypto/scheduler/scheduler_pmd_ops.c  | 101 ++-
 .../crypto/scheduler/scheduler_pmd_private.h  | 120 +-
 .../crypto/scheduler/scheduler_roundrobin.c   |  11 +-
 7 files changed, 314 insertions(+), 42 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index c975c38001..e181b0aa3e 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -14986,8 +14986,8 @@ test_scheduler_attach_worker_op(void)
ts_params->session_mpool =
rte_cryptodev_sym_session_pool_create(
"test_sess_mp",
-   MAX_NB_SESSIONS, 0, 0, 0,
-   SOCKET_ID_ANY);
+   MAX_NB_SESSIONS, session_size,
+   0, 0, SOCKET_ID_ANY);
TEST_ASSERT_NOT_NULL(ts_params->session_mpool,
"session mempool allocation failed");
}
diff --git a/drivers/crypto/scheduler/scheduler_failover.c 
b/drivers/crypto/scheduler/scheduler_failover.c
index 2a0e29fa72..7fadcf66d0 100644
--- a/drivers/crypto/scheduler/scheduler_failover.c
+++ b/drivers/crypto/scheduler/scheduler_failover.c
@@ -16,18 +16,19 @@
 struct fo_scheduler_qp_ctx {
struct scheduler_worker primary_worker;
struct scheduler_worker secondary_worker;
+   uint8_t primary_worker_index;
+   uint8_t secondary_worker_index;
 
uint8_t deq_idx;
 };
 
 static __rte_always_inline uint16_t
 failover_worker_enqueue(struct scheduler_worker *worker,
-   struct rte_crypto_op **ops, uint16_t nb_ops)
+   struct rte_crypto_op **ops, uint16_t nb_ops, uint8_t index)
 {
-   uint16_t i, processed_ops;
+   uint16_t processed_ops;
 
-   for (i = 0; i < nb_ops && i < 4; i++)
-   rte_prefetch0(ops[i]->sym->session);
+   scheduler_set_worker_session(ops, nb_ops, index);
 
processed_ops = rte_cryptodev_enqueue_burst(worker->dev_id,
worker->qp_id, ops, nb_ops);
@@ -47,13 +48,14 @@ schedule_enqueue(void *qp, struct rte_crypto_op **ops, 
uint16_t nb_ops)
return 0;
 
enqueued_ops = failover_worker_enqueue(&qp_ctx->primary_worker,
-   ops, nb_ops);
+   ops, nb_ops, PRIMARY_WORKER_IDX);
 
if (enqueued_ops < nb_ops)
enqueued_ops += failover_worker_enqueue(
&qp_ctx->secondary_worker,
&ops[enqueued_ops],
-   nb_ops - enqueued_ops);
+   nb_ops - enqueued_ops,
+   SECONDARY_WORKER_IDX);
 
return enqueued_ops;
 }
@@ -94,7 +96,7 @@ schedule_dequeue(void *qp, struct rte_crypto_op **ops, 
uint16_t nb_ops)
qp_ctx->deq_idx = (~qp_ctx->deq_idx) & WORKER_SWITCH_MASK;
 
if (nb_deq_ops == nb_ops)
-   return nb_deq_ops;
+   goto retrieve_session;
 
worker = workers[qp_ctx->deq_idx];
 
@@ -104,6 +106,9 @@ schedule_dequeue(void *qp, struct rte_crypto_op **ops, 
uint16_t nb_ops)
worker->nb_inflight_cops -= nb_deq_ops2;
}
 
+retrieve_session:
+   scheduler_retrieve_session(ops, nb_deq_ops + nb_deq_ops2);
+
return nb_deq_ops + nb_deq_ops2;
 }
 
diff --git a/drivers/crypto/scheduler/scheduler_multicore.c 
b/drivers/crypto/scheduler/scheduler_multicore.c
index 900ab4049d..3dea850661 100644
--- a/drivers/crypto/scheduler/scheduler_multicore.c
+++ b/drivers/crypto/scheduler/scheduler_multicore.c
@@ -183,11 +183,19 @@ mc_scheduler_worker(struct rte_cryptodev *dev)
 
while (!mc_ctx->stop_signal) {
if (pending_enq_ops) {
+

[PATCH 0/3] cryptodev: sym session framework rework

2022-08-29 Thread Fan Zhang

This patchset reworks the symmetric crypto session data structure to
use a single virtual/physical contiguous buffer for symmetric crypto
session and driver private data. In addition the session data
structure is now private. The session is represented as an opaque
pointer in the application.

With the change the session is no longer supported to be accessed
by multiple device drivers. For the same reason
rte_cryptodev_sym_session_init/clear APIs are deprecated as
rte_cryptodev_sym_session_create/free will initialize and
clear the driver specific data field.

Fan Zhang (3):
  cryptodev: rework session framework
  crypto/scheduler: use unified session
  cryptodev: hide sym session structure

 app/test-crypto-perf/cperf_ops.c  |  21 +-
 app/test-crypto-perf/cperf_test_latency.c |   6 +-
 .../cperf_test_pmd_cyclecount.c   |   5 +-
 app/test-crypto-perf/cperf_test_throughput.c  |   6 +-
 app/test-crypto-perf/cperf_test_verify.c  |   6 +-
 app/test-crypto-perf/main.c   |  29 +-
 app/test-eventdev/test_perf_common.c  |  35 +-
 app/test-eventdev/test_perf_common.h  |   1 -
 app/test/test_cryptodev.c | 302 +-
 app/test/test_cryptodev_blockcipher.c |  16 +-
 app/test/test_event_crypto_adapter.c  |  35 +-
 app/test/test_ipsec.c |  42 +--
 app/test/test_ipsec_perf.c|   4 +-
 doc/guides/prog_guide/cryptodev_lib.rst   |  16 +-
 doc/guides/rel_notes/deprecation.rst  |   9 +
 doc/guides/rel_notes/release_22_11.rst|   7 +
 drivers/crypto/armv8/rte_armv8_pmd.c  |  21 +-
 drivers/crypto/armv8/rte_armv8_pmd_ops.c  |  32 +-
 drivers/crypto/bcmfs/bcmfs_sym_session.c  |  38 +--
 drivers/crypto/bcmfs/bcmfs_sym_session.h  |   3 +-
 drivers/crypto/caam_jr/caam_jr.c  |  28 +-
 drivers/crypto/ccp/ccp_crypto.c   |  58 +---
 drivers/crypto/ccp/ccp_pmd_ops.c  |  32 +-
 drivers/crypto/ccp/ccp_pmd_private.h  |   2 -
 drivers/crypto/ccp/rte_ccp_pmd.c  |  29 +-
 drivers/crypto/cnxk/cn10k_cryptodev_ops.c |  36 +--
 drivers/crypto/cnxk/cn9k_cryptodev_ops.c  |  31 +-
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c  |  54 +---
 drivers/crypto/cnxk/cnxk_cryptodev_ops.h  |  14 +-
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c   |  31 +-
 drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c   |   3 +-
 drivers/crypto/dpaa_sec/dpaa_sec.c|  37 +--
 drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c |   4 +-
 drivers/crypto/ipsec_mb/ipsec_mb_ops.c|  34 +-
 drivers/crypto/ipsec_mb/ipsec_mb_private.h|  41 ++-
 drivers/crypto/ipsec_mb/pmd_aesni_gcm.c   |  48 +--
 drivers/crypto/ipsec_mb/pmd_aesni_mb.c|  26 +-
 drivers/crypto/ipsec_mb/pmd_chacha_poly.c |   4 -
 drivers/crypto/ipsec_mb/pmd_kasumi.c  |  10 +-
 drivers/crypto/ipsec_mb/pmd_snow3g.c  |   9 +-
 drivers/crypto/ipsec_mb/pmd_zuc.c |   4 -
 drivers/crypto/mlx5/mlx5_crypto.c |  26 +-
 drivers/crypto/mvsam/rte_mrvl_pmd.c   |   8 +-
 drivers/crypto/mvsam/rte_mrvl_pmd_ops.c   |  21 +-
 drivers/crypto/nitrox/nitrox_sym.c|  39 +--
 drivers/crypto/null/null_crypto_pmd.c |  19 +-
 drivers/crypto/null/null_crypto_pmd_ops.c |  33 +-
 drivers/crypto/null/null_crypto_pmd_private.h |   2 -
 .../crypto/octeontx/otx_cryptodev_hw_access.h |   1 -
 drivers/crypto/octeontx/otx_cryptodev_ops.c   |  67 +---
 drivers/crypto/openssl/openssl_pmd_private.h  |   2 -
 drivers/crypto/openssl/rte_openssl_pmd.c  |  24 +-
 drivers/crypto/openssl/rte_openssl_pmd_ops.c  |  29 +-
 drivers/crypto/qat/qat_sym.c  |  10 +-
 drivers/crypto/qat/qat_sym.h  |   4 +-
 drivers/crypto/qat/qat_sym_session.c  |  40 +--
 drivers/crypto/qat/qat_sym_session.h  |   6 +-
 drivers/crypto/scheduler/scheduler_failover.c |  19 +-
 .../crypto/scheduler/scheduler_multicore.c|  17 +
 .../scheduler/scheduler_pkt_size_distr.c  |  84 +++--
 drivers/crypto/scheduler/scheduler_pmd_ops.c  |  87 -
 .../crypto/scheduler/scheduler_pmd_private.h  | 120 ++-
 .../crypto/scheduler/scheduler_roundrobin.c   |  11 +-
 drivers/crypto/virtio/virtio_cryptodev.c  |  40 +--
 drivers/crypto/virtio/virtio_rxtx.c   |   3 +-
 examples/fips_validation/fips_dev_self_test.c |  30 +-
 examples/fips_validation/main.c   |  35 +-
 examples/ipsec-secgw/ipsec-secgw.c|  10 +-
 examples/ipsec-secgw/ipsec.c  |   7 +-
 examples/l2fwd-crypto/main.c  |  54 +---
 examples/vhost_crypto/main.c  |  16 +-
 lib/cryptodev/cryptodev_pmd.h |  59 ++--
 lib/cryptodev/cryptodev_trace_points.c|   6 -
 lib/cryptodev/rte_cryptodev.c | 280 ++--
 lib/cryptodev/rte_cryptodev.h | 153 +++--
 lib/cryptodev/rte_cryptodev_trace.h

[PATCH 3/3] cryptodev: hide sym session structure

2022-08-29 Thread Fan Zhang

Structure rte_cryptodev_sym_session is moved to internal
headers which are not visible to applications.
The only field which should be used by app is opaque_data.
This field can now be accessed via set/get APIs added in this
patch.
Subsequent changes in app and lib are made to compile the code.

Signed-off-by: Fan Zhang 
Signed-off-by: Akhil Goyal 
---
 app/test/test_ipsec_perf.c  |  4 +-
 doc/guides/prog_guide/cryptodev_lib.rst | 16 ++
 doc/guides/rel_notes/deprecation.rst|  9 
 doc/guides/rel_notes/release_22_11.rst  |  7 +++
 drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c |  2 +-
 drivers/crypto/dpaa_sec/dpaa_sec_raw_dp.c   |  2 +-
 drivers/crypto/qat/qat_sym.c|  2 +-
 lib/cryptodev/cryptodev_pmd.h   | 31 
 lib/cryptodev/rte_cryptodev.c   | 16 +++---
 lib/cryptodev/rte_cryptodev.h   | 56 ++---
 lib/cryptodev/rte_cryptodev_trace.h |  8 +--
 lib/ipsec/rte_ipsec_group.h |  5 +-
 lib/ipsec/ses.c |  3 +-
 13 files changed, 100 insertions(+), 61 deletions(-)

diff --git a/app/test/test_ipsec_perf.c b/app/test/test_ipsec_perf.c
index b5d0c2e036..b221b7fc32 100644
--- a/app/test/test_ipsec_perf.c
+++ b/app/test/test_ipsec_perf.c
@@ -227,7 +227,7 @@ static int
 create_sa(enum rte_security_session_action_type action_type,
  struct ipsec_sa *sa)
 {
-   static struct rte_cryptodev_sym_session dummy_ses;
+   void *dummy_ses = NULL;
size_t sz;
int rc;
 
@@ -247,7 +247,7 @@ create_sa(enum rte_security_session_action_type action_type,
"failed to allocate memory for rte_ipsec_sa\n");
 
sa->ss[0].type = action_type;
-   sa->ss[0].crypto.ses = &dummy_ses;
+   sa->ss[0].crypto.ses = dummy_ses;
 
rc = rte_ipsec_sa_init(sa->ss[0].sa, &sa->sa_prm, sz);
rc = (rc > 0 && (uint32_t)rc <= sz) ? 0 : -EINVAL;
diff --git a/doc/guides/prog_guide/cryptodev_lib.rst 
b/doc/guides/prog_guide/cryptodev_lib.rst
index 9e54683aa1..01aad842a9 100644
--- a/doc/guides/prog_guide/cryptodev_lib.rst
+++ b/doc/guides/prog_guide/cryptodev_lib.rst
@@ -125,13 +125,11 @@ Each queue pairs resources may be allocated on a 
specified socket.
 uint32_t nb_descriptors; /**< Number of descriptors per queue pair */
 struct rte_mempool *mp_session;
 /**< The mempool for creating session in sessionless mode */
-struct rte_mempool *mp_session_private;
-/**< The mempool for creating sess private data in sessionless mode */
 };
 
 
-The fields ``mp_session`` and ``mp_session_private`` are used for creating
-temporary session to process the crypto operations in the session-less mode.
+The field ``mp_session`` is used for creating temporary session to process
+the crypto operations in the session-less mode.
 They can be the same other different mempools. Please note not all Cryptodev
 PMDs supports session-less mode.
 
@@ -595,7 +593,7 @@ chain.
 struct rte_mbuf *m_dst;
 
 union {
-struct rte_cryptodev_sym_session *session;
+void *session;
 /**< Handle for the initialised session context */
 struct rte_crypto_sym_xform *xform;
 /**< Session-less API Crypto operation parameters */
@@ -943,15 +941,11 @@ using one of the crypto PMDs available in DPDK.
 
 /* Create crypto session and initialize it for the crypto device. */
 struct rte_cryptodev_sym_session *session;
-session = rte_cryptodev_sym_session_create(session_pool);
+session = rte_cryptodev_sym_session_create(cdev_id, &cipher_xform,
+session_pool);
 if (session == NULL)
 rte_exit(EXIT_FAILURE, "Session could not be created\n");
 
-if (rte_cryptodev_sym_session_init(cdev_id, session,
-&cipher_xform, session_priv_pool) < 0)
-rte_exit(EXIT_FAILURE, "Session could not be initialized "
-"for the crypto device\n");
-
 /* Get a burst of crypto operations. */
 struct rte_crypto_op *crypto_ops[BURST_SIZE];
 if (rte_crypto_op_bulk_alloc(crypto_op_pool,
diff --git a/doc/guides/rel_notes/deprecation.rst 
b/doc/guides/rel_notes/deprecation.rst
index e7583cae4c..ba46b6930f 100644
--- a/doc/guides/rel_notes/deprecation.rst
+++ b/doc/guides/rel_notes/deprecation.rst
@@ -237,3 +237,12 @@ Deprecation Notices
   applications should be updated to use the ``dmadev`` library instead,
   with the underlying HW-functionality being provided by the ``ioat`` or
   ``idxd`` dma drivers
+
+* cryptodev: Hide structure ``rte_cryptodev_sym_session`` to remove unnecessary
+  indirection between session and the private data of session. An opaque 
pointer
+  can be exposed directly to application which can be attached to the
+  ``rte_crypto_op``.
+
+* cryptodev: The function

[PATCH v2] crypto/ipsec_mb: add NULL/NULL support to aesni-mb

2022-02-21 Thread Fan Zhang

Add NULL cipher and auth support to AESNI-MB PMD type.

Signed-off-by: Fan Zhang 
Signed-off-by: Declan Doherty 
Signed-off-by: Radu Nicolau 
---
v2:
- Added actual PMD support.

 drivers/crypto/ipsec_mb/pmd_aesni_mb.c  | 18 ++
 drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 37 +
 2 files changed, 55 insertions(+)

diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c 
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index a308d42ffa..0111c6f540 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -88,6 +88,12 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR *mb_mgr,
sess->auth.operation = xform->auth.op;
 
/* Set Authentication Parameters */
+   if (xform->auth.algo == RTE_CRYPTO_AUTH_NULL) {
+   sess->auth.algo = IMB_AUTH_NULL;
+   sess->auth.gen_digest_len = 0;
+   return 0;
+   }
+
if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_XCBC_MAC) {
sess->auth.algo = IMB_AUTH_AES_XCBC;
 
@@ -434,6 +440,12 @@ aesni_mb_set_session_cipher_parameters(const IMB_MGR 
*mb_mgr,
sess->cipher.mode = IMB_CIPHER_KASUMI_UEA1_BITLEN;
is_kasumi = 1;
break;
+   case RTE_CRYPTO_CIPHER_NULL:
+   sess->cipher.mode = IMB_CIPHER_NULL;
+   sess->cipher.key_length_in_bytes = 0;
+   sess->iv.offset = xform->cipher.iv.offset;
+   sess->iv.length = xform->cipher.iv.length;
+   return 0;
default:
IPSEC_MB_LOG(ERR, "Unsupported cipher mode parameter");
return -ENOTSUP;
@@ -1324,6 +1336,12 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,
session->iv.offset);
}
 
+   if (job->cipher_mode == IMB_CIPHER_NULL && oop) {
+   memcpy(job->dst + job->cipher_start_src_offset_in_bytes,
+   job->src + job->cipher_start_src_offset_in_bytes,
+   job->msg_len_to_cipher_in_bytes);
+   }
+
if (job->cipher_mode == IMB_CIPHER_ZUC_EEA3)
job->msg_len_to_cipher_in_bytes >>= 3;
else if (job->hash_alg == IMB_AUTH_KASUMI_UIA1)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h 
b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
index d37cc787a0..f46037ff76 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
@@ -275,6 +275,43 @@ static const struct rte_cryptodev_capabilities 
aesni_mb_capabilities[] = {
}, }
}, }
},
+   {   /* NULL (AUTH) */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   {.sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   {.auth = {
+   .algo = RTE_CRYPTO_AUTH_NULL,
+   .block_size = 1,
+   .key_size = {
+   .min = 0,
+   .max = 0,
+   .increment = 0
+   },
+   .digest_size = {
+   .min = 0,
+   .max = 0,
+   .increment = 0
+   },
+   .iv_size = { 0 }
+   }, },
+   }, },
+   },
+   {   /* NULL (CIPHER) */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   {.sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+   {.cipher = {
+   .algo = RTE_CRYPTO_CIPHER_NULL,
+   .block_size = 1,
+   .key_size = {
+   .min = 0,
+   .max = 0,
+   .increment = 0
+   },
+   .iv_size = { 0 }
+   }, },
+   }, }
+   },
{   /* AES CBC */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
{.sym = {
-- 
2.25.1

[PATCH v11 0/9] drivers/qat: QAT symmetric crypto datapatch rework

2022-02-22 Thread Fan Zhang

This patch reworks QAT symmetric crypto datapatch implementation where each
generation request building separated and the crypto operation under the
raw datapath api implementation are unified.

In addtion this patchset also enables QAT OOP support in raw datapath api
implementation.

v11:
- fixed a compile issue

v10:
- rebase to the lastest for-main
- fix of build rerror when RTE_LOG_DEBUG enabled

v9:
- commit messages reword
- fix of unused function error

v8:
- rebase to 22.03-rc1

v7:
- fix of pointer cast compile error in x86

v6:
- fix of pointer cast error in x86
- rebase to the lastest for-main

v5:
- rebase to the latest for-main
- patchset reconstruct

v4:
- patchset break down and reconstruct

v3:
- sperate a single patch 6 to two different patches

v2:
- review comments addressed

Kai Ji (9):
  common/qat: define build request and dequeue ops
  crypto/qat: support symmetric build op request
  crypto/qat: rework session functions
  crypto/qat: rework asymmetric op build operation
  crypto/qat: unify symmetric functions
  crypto/qat: unify asymmetric functions
  crypto/qat: rework burst data path
  crypto/qat: unify raw data path functions
  crypto/qat: support out of place SG list

 drivers/common/qat/meson.build   |   6 +-
 drivers/common/qat/qat_device.c  |   4 +-
 drivers/common/qat/qat_qp.c  |  42 +-
 drivers/common/qat/qat_qp.h  |  54 +-
 drivers/compress/qat/qat_comp_pmd.c  |  14 +-
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   |   9 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |  93 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 490 -
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 257 -
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 913 -
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 942 +-
 drivers/crypto/qat/qat_asym.c| 303 +-
 drivers/crypto/qat/qat_asym.h|  79 +-
 drivers/crypto/qat/qat_asym_pmd.c| 231 -
 drivers/crypto/qat/qat_asym_pmd.h|  54 -
 drivers/crypto/qat/qat_crypto.h  |  16 +-
 drivers/crypto/qat/qat_sym.c | 979 ++
 drivers/crypto/qat/qat_sym.h | 148 ++-
 drivers/crypto/qat/qat_sym_hw_dp.c   | 995 ---
 drivers/crypto/qat/qat_sym_pmd.c | 251 -
 drivers/crypto/qat/qat_sym_pmd.h |  95 --
 drivers/crypto/qat/qat_sym_session.c | 115 +--
 drivers/crypto/qat/qat_sym_session.h |  15 +-
 23 files changed, 3582 insertions(+), 2523 deletions(-)
 delete mode 100644 drivers/crypto/qat/qat_asym_pmd.c
 delete mode 100644 drivers/crypto/qat/qat_asym_pmd.h
 delete mode 100644 drivers/crypto/qat/qat_sym_hw_dp.c
 delete mode 100644 drivers/crypto/qat/qat_sym_pmd.c
 delete mode 100644 drivers/crypto/qat/qat_sym_pmd.h

-- 
2.25.1

[PATCH v11 1/9] common/qat: define build request and dequeue ops

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch introduce build request and dequeue op function
pointers to the qat queue pair implementation. The function
poniters are assigned during qat session generation based on input
crypto operation request.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/common/qat/qat_qp.c  | 10 --
 drivers/common/qat/qat_qp.h  | 54 ++--
 drivers/compress/qat/qat_comp_pmd.c  |  6 ++--
 drivers/crypto/qat/qat_asym_pmd.c|  4 +--
 drivers/crypto/qat/qat_sym_pmd.c |  4 +--
 drivers/crypto/qat/qat_sym_session.h | 13 ++-
 6 files changed, 77 insertions(+), 14 deletions(-)

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 57ac8fefca..56234ca1a4 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015-2018 Intel Corporation
+ * Copyright(c) 2015-2022 Intel Corporation
  */
 
 #include 
@@ -547,7 +547,9 @@ adf_modulo(uint32_t data, uint32_t modulo_mask)
 }
 
 uint16_t
-qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
+qat_enqueue_op_burst(void *qp,
+   __rte_unused qat_op_build_request_t op_build_request,
+   void **ops, uint16_t nb_ops)
 {
register struct qat_queue *queue;
struct qat_qp *tmp_qp = (struct qat_qp *)qp;
@@ -814,7 +816,9 @@ qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t 
nb_ops)
 }
 
 uint16_t
-qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
+qat_dequeue_op_burst(void *qp, void **ops,
+   __rte_unused qat_op_dequeue_t qat_dequeue_process_response,
+   uint16_t nb_ops)
 {
struct qat_queue *rx_queue;
struct qat_qp *tmp_qp = (struct qat_qp *)qp;
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index deafb407b3..66f00943a5 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018 Intel Corporation
+ * Copyright(c) 2018-2022 Intel Corporation
  */
 #ifndef _QAT_QP_H_
 #define _QAT_QP_H_
@@ -36,6 +36,51 @@ struct qat_queue {
/* number of responses processed since last CSR head write */
 };
 
+/**
+ * Type define qat_op_build_request_t function pointer, passed in as argument
+ * in enqueue op burst, where a build request assigned base on the type of
+ * crypto op.
+ *
+ * @param in_op
+ *An input op pointer
+ * @param out_msg
+ *out_meg pointer
+ * @param op_cookie
+ *op cookie pointer
+ * @param opaque
+ *an opaque data may be used to store context may be useful between
+ *2 enqueue operations.
+ * @param dev_gen
+ *qat device gen id
+ * @return
+ *   - 0 if the crypto request is build successfully,
+ *   - EINVAL if error
+ **/
+typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg,
+   void *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen);
+
+/**
+ * Type define qat_op_dequeue_t function pointer, passed in as argument
+ * in dequeue op burst, where a dequeue op assigned base on the type of
+ * crypto op.
+ *
+ * @param op
+ *An input op pointer
+ * @param resp
+ *qat response msg pointer
+ * @param op_cookie
+ *op cookie pointer
+ * @param dequeue_err_count
+ *dequeue error counter
+ * @return
+ *- 0 if dequeue OP is successful
+ *- EINVAL if error
+ **/
+typedef int (*qat_op_dequeue_t)(void **op, uint8_t *resp, void *op_cookie,
+   uint64_t *dequeue_err_count __rte_unused);
+
+#define QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE  2
+
 struct qat_qp {
void*mmap_bar_addr;
struct qat_queuetx_q;
@@ -44,6 +89,7 @@ struct qat_qp {
struct rte_mempool *op_cookie_pool;
void **op_cookies;
uint32_t nb_descriptors;
+   uint64_t opaque[QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE];
enum qat_device_gen qat_dev_gen;
enum qat_service_type service_type;
struct qat_pci_device *qat_dev;
@@ -78,13 +124,15 @@ struct qat_qp_config {
 };
 
 uint16_t
-qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
+qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,
+   void **ops, uint16_t nb_ops);
 
 uint16_t
 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);
 
 uint16_t
-qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);
+qat_dequeue_op_burst(void *qp, void **ops,
+   qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops);
 
 int
 qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr);
diff --git a/drivers/compress/qat/qat_comp_pmd.c 
b/drivers/compress/qat/qat_comp_pmd.c
index da6404c017..efe5d08a99 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2015-2019 Intel Corporation
+ * Copyright(c) 2015-2022 Intel

[PATCH v11 2/9] crypto/qat: support symmetric build op request

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch adds common inline functions for QAT symmetric
crypto driver to process crypto op, and the implementation of
build op request function for QAT generation 1.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 832 ++-
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 187 -
 drivers/crypto/qat/qat_sym.c |  90 +-
 3 files changed, 1019 insertions(+), 90 deletions(-)

diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h 
b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
index 67a4d2cb2c..1130e0e76f 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017-2021 Intel Corporation
+ * Copyright(c) 2017-2022 Intel Corporation
  */
 
 #ifndef _QAT_CRYPTO_PMD_GENS_H_
@@ -8,14 +8,844 @@
 #include 
 #include "qat_crypto.h"
 #include "qat_sym_session.h"
+#include "qat_sym.h"
+
+#define QAT_SYM_DP_GET_MAX_ENQ(q, c, n) \
+   RTE_MIN((q->max_inflights - q->enqueued + q->dequeued - c), n)
+
+#define QAT_SYM_DP_IS_RESP_SUCCESS(resp) \
+   (ICP_QAT_FW_COMN_STATUS_FLAG_OK == \
+   ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(resp->comn_hdr.comn_status))
+
+static __rte_always_inline int
+op_bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
+   uint8_t *iv, int ivlen, int srclen,
+   void *bpi_ctx)
+{
+   EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
+   int encrypted_ivlen;
+   uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
+   uint8_t *encr = encrypted_iv;
+
+   /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
+   if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
+   <= 0)
+   goto cipher_decrypt_err;
+
+   for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
+   *dst = *src ^ *encr;
+
+   return 0;
+
+cipher_decrypt_err:
+   QAT_DP_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
+   return -EINVAL;
+}
+
+static __rte_always_inline uint32_t
+qat_bpicipher_preprocess(struct qat_sym_session *ctx,
+   struct rte_crypto_op *op)
+{
+   int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
+   struct rte_crypto_sym_op *sym_op = op->sym;
+   uint8_t last_block_len = block_len > 0 ?
+   sym_op->cipher.data.length % block_len : 0;
+
+   if (last_block_len && ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
+   /* Decrypt last block */
+   uint8_t *last_block, *dst, *iv;
+   uint32_t last_block_offset = sym_op->cipher.data.offset +
+   sym_op->cipher.data.length - last_block_len;
+   last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
+   uint8_t *, last_block_offset);
+
+   if (unlikely((sym_op->m_dst != NULL)
+   && (sym_op->m_dst != sym_op->m_src)))
+   /* out-of-place operation (OOP) */
+   dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
+   uint8_t *, last_block_offset);
+   else
+   dst = last_block;
+
+   if (last_block_len < sym_op->cipher.data.length)
+   /* use previous block ciphertext as IV */
+   iv = last_block - block_len;
+   else
+   /* runt block, i.e. less than one full block */
+   iv = rte_crypto_op_ctod_offset(op, uint8_t *,
+   ctx->cipher_iv.offset);
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+   QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: src before pre-process:",
+   last_block, last_block_len);
+   if (sym_op->m_dst != NULL)
+   QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: dst before 
pre-process:",
+   dst, last_block_len);
+#endif
+   op_bpi_cipher_decrypt(last_block, dst, iv, block_len,
+   last_block_len, ctx->bpi_ctx);
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+   QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: src after pre-process:",
+   last_block, last_block_len);
+   if (sym_op->m_dst != NULL)
+   QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: dst after pre-process:",
+   dst, last_block_len);
+#endif
+   }
+
+   return sym_op->cipher.data.length - last_block_len;
+}
+
+static __rte_always_inline int
+qat_auth_is_len_in_bits

[PATCH v11 3/9] crypto/qat: rework session functions

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch introduces a set of set_session methods to QAT
generations. In addition, the reuse of QAT session between
generations is prohibit as the support of min_qat_dev_gen_id'
is removed.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/crypto/qat/dev/qat_asym_pmd_gen1.c   |   9 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |  91 ++-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 256 ++-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 125 -
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |   3 +
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c|  64 +
 drivers/crypto/qat/qat_crypto.h  |   8 +-
 drivers/crypto/qat/qat_sym.c |  12 +-
 drivers/crypto/qat/qat_sym_session.c | 113 ++--
 drivers/crypto/qat/qat_sym_session.h |   2 +-
 10 files changed, 574 insertions(+), 109 deletions(-)

diff --git a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c 
b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
index 9ed1f21d9d..01a897a21f 100644
--- a/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
+++ b/drivers/crypto/qat/dev/qat_asym_pmd_gen1.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017-2021 Intel Corporation
+ * Copyright(c) 2017-2022 Intel Corporation
  */
 
 #include 
@@ -65,6 +65,13 @@ qat_asym_crypto_feature_flags_get_gen1(
return feature_flags;
 }
 
+int
+qat_asym_crypto_set_session_gen1(void *cdev __rte_unused,
+   void *session __rte_unused)
+{
+   return 0;
+}
+
 RTE_INIT(qat_asym_crypto_gen1_init)
 {
qat_asym_gen_dev_ops[QAT_GEN1].cryptodev_ops =
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c 
b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
index b4ec440e05..64e6ae66ec 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017-2021 Intel Corporation
+ * Copyright(c) 2017-2022 Intel Corporation
  */
 
 #include 
@@ -166,6 +166,91 @@ qat_sym_crypto_qp_setup_gen2(struct rte_cryptodev *dev, 
uint16_t qp_id,
return 0;
 }
 
+void
+qat_sym_session_set_ext_hash_flags_gen2(struct qat_sym_session *session,
+   uint8_t hash_flag)
+{
+   struct icp_qat_fw_comn_req_hdr *header = &session->fw_req.comn_hdr;
+   struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *cd_ctrl =
+   (struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *)
+   session->fw_req.cd_ctrl.content_desc_ctrl_lw;
+
+   /* Set the Use Extended Protocol Flags bit in LW 1 */
+   QAT_FIELD_SET(header->comn_req_flags,
+   QAT_COMN_EXT_FLAGS_USED,
+   QAT_COMN_EXT_FLAGS_BITPOS,
+   QAT_COMN_EXT_FLAGS_MASK);
+
+   /* Set Hash Flags in LW 28 */
+   cd_ctrl->hash_flags |= hash_flag;
+
+   /* Set proto flags in LW 1 */
+   switch (session->qat_cipher_alg) {
+   case ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2:
+   ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
+   ICP_QAT_FW_LA_SNOW_3G_PROTO);
+   ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(
+   header->serv_specif_flags, 0);
+   break;
+   case ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3:
+   ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
+   ICP_QAT_FW_LA_NO_PROTO);
+   ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(
+   header->serv_specif_flags,
+   ICP_QAT_FW_LA_ZUC_3G_PROTO);
+   break;
+   default:
+   ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
+   ICP_QAT_FW_LA_NO_PROTO);
+   ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(
+   header->serv_specif_flags, 0);
+   break;
+   }
+}
+
+static int
+qat_sym_crypto_set_session_gen2(void *cdev, void *session)
+{
+   struct rte_cryptodev *dev = cdev;
+   struct qat_sym_session *ctx = session;
+   const struct qat_cryptodev_private *qat_private =
+   dev->data->dev_private;
+   int ret;
+
+   ret = qat_sym_crypto_set_session_gen1(cdev, session);
+   if (ret == -ENOTSUP) {
+   /* GEN1 returning -ENOTSUP as it cannot handle some mixed algo,
+* but some are not supported by GEN2, so checking here
+*/
+   if ((qat_private->internal_capabilities &
+   QAT_SYM_CAP_MIXED_CRYPTO) == 0)
+   return -ENOTSUP;
+
+   if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&
+   ctx->qat_cipher_alg !=
+   ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
+   qat_sym_s

[PATCH v11 4/9] crypto/qat: rework asymmetric op build operation

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch reworks the asymmetric crypto data path
implementation in QAT driver. The changes include asymmetric
crypto data path separation for QAT hardware generations, and
code optimisation of the device capabilities declaration.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/common/qat/qat_qp.c   |   5 +-
 drivers/crypto/qat/qat_asym.c | 129 +++---
 drivers/crypto/qat/qat_asym.h |  63 +++--
 3 files changed, 131 insertions(+), 66 deletions(-)

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 56234ca1a4..7f2fdc53ce 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -619,7 +619,7 @@ qat_enqueue_op_burst(void *qp,
 #ifdef BUILD_QAT_ASYM
ret = qat_asym_build_request(*ops, base_addr + tail,
tmp_qp->op_cookies[tail >> queue->trailz],
-   tmp_qp->qat_dev_gen);
+   NULL, tmp_qp->qat_dev_gen);
 #endif
}
if (ret != 0) {
@@ -847,7 +847,8 @@ qat_dequeue_op_burst(void *qp, void **ops,
 #ifdef BUILD_QAT_ASYM
else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)
qat_asym_process_response(ops, resp_msg,
-   tmp_qp->op_cookies[head >> rx_queue->trailz]);
+   tmp_qp->op_cookies[head >> rx_queue->trailz],
+   NULL);
 #endif
 
head = adf_modulo(head + rx_queue->msg_size,
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index 27ce0337a7..d6ca1afae8 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -1,68 +1,36 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019 Intel Corporation
+ * Copyright(c) 2019 - 2022 Intel Corporation
  */
 
 #include 
 
-#include "qat_asym.h"
+#include 
+
 #include "icp_qat_fw_pke.h"
 #include "icp_qat_fw.h"
 #include "qat_pke_functionality_arrays.h"
 
-#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))
-
-static int qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
-   size_t arr_sz, size_t *size, uint32_t *func_id)
-{
-   size_t i;
-
-   for (i = 0; i < arr_sz; i++) {
-   if (*size <= arr[i][0]) {
-   *size = arr[i][0];
-   *func_id = arr[i][1];
-   return 0;
-   }
-   }
-   return -1;
-}
-
-static inline void qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req)
-{
-   memset(qat_req, 0, sizeof(*qat_req));
-   qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
-
-   qat_req->pke_hdr.hdr_flags =
-   ICP_QAT_FW_COMN_HDR_FLAGS_BUILD
-   (ICP_QAT_FW_COMN_REQ_FLAG_SET);
-}
-
-static inline void qat_asym_build_req_tmpl(void *sess_private_data)
-{
-   struct icp_qat_fw_pke_request *qat_req;
-   struct qat_asym_session *session = sess_private_data;
+#include "qat_device.h"
 
-   qat_req = &session->req_tmpl;
-   qat_fill_req_tmpl(qat_req);
-}
+#include "qat_logs.h"
+#include "qat_asym.h"
 
-static size_t max_of(int n, ...)
-{
-   va_list args;
-   size_t len = 0, num;
-   int i;
+uint8_t qat_asym_driver_id;
 
-   va_start(args, n);
-   len = va_arg(args, size_t);
+struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[QAT_N_GENS];
 
-   for (i = 0; i < n - 1; i++) {
-   num = va_arg(args, size_t);
-   if (num > len)
-   len = num;
-   }
-   va_end(args);
+/* An rte_driver is needed in the registration of both the device and the 
driver
+ * with cryptodev.
+ * The actual qat pci's rte_driver can't be used as its name represents
+ * the whole pci device with all services. Think of this as a holder for a name
+ * for the crypto part of the pci device.
+ */
+static const char qat_asym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_ASYM_PMD);
+static const struct rte_driver cryptodev_qat_asym_driver = {
+   .name = qat_asym_drv_name,
+   .alias = qat_asym_drv_name
+};
 
-   return len;
-}
 
 static void qat_clear_arrays(struct qat_asym_op_cookie *cookie,
int in_count, int out_count, int alg_size)
@@ -106,7 +74,46 @@ static void qat_clear_arrays_by_alg(struct 
qat_asym_op_cookie *cookie,
}
 }
 
-static int qat_asym_check_nonzero(rte_crypto_param n)
+#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))
+
+static int
+qat_asym_get_sz_and_func_id(const uint32_t arr[][2],
+   size_t arr_sz, size_t *size, uint32_t *func_id)
+{
+   size_t i;
+
+   for (i = 0; i < arr_sz; i++) {
+   if (*size <= arr[i][0]) {
+   *size

[PATCH v11 5/9] crypto/qat: unify symmetric functions

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch removes qat_sym_pmd.c and integrates all the functions into
qat_sym.c. The unified/integrated qat sym crypto pmd functions should
make them easier to maintain.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/common/qat/meson.build   |   4 +-
 drivers/common/qat/qat_device.c  |   4 +-
 drivers/common/qat/qat_qp.c  |   3 +-
 drivers/crypto/qat/qat_crypto.h  |   5 +-
 drivers/crypto/qat/qat_sym.c |  21 +++
 drivers/crypto/qat/qat_sym.h | 147 ++--
 drivers/crypto/qat/qat_sym_hw_dp.c   |  11 +-
 drivers/crypto/qat/qat_sym_pmd.c | 251 ---
 drivers/crypto/qat/qat_sym_pmd.h |  95 --
 drivers/crypto/qat/qat_sym_session.c |   2 +-
 10 files changed, 168 insertions(+), 375 deletions(-)
 delete mode 100644 drivers/crypto/qat/qat_sym_pmd.c
 delete mode 100644 drivers/crypto/qat/qat_sym_pmd.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index af92271a75..1bf6896a7e 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017-2018 Intel Corporation
+# Copyright(c) 2017-2022 Intel Corporation
 
 if is_windows
 build = false
@@ -73,7 +73,7 @@ if qat_compress
 endif
 
 if qat_crypto
-foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c',
+foreach f: ['qat_sym.c', 'qat_sym_session.c',
 'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',
 'dev/qat_sym_pmd_gen1.c',
 'dev/qat_asym_pmd_gen1.c',
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index 1f870d689a..6824d97050 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2020 Intel Corporation
+ * Copyright(c) 2018-2022 Intel Corporation
  */
 
 #include 
@@ -8,7 +8,7 @@
 
 #include "qat_device.h"
 #include "adf_transport_access_macros.h"
-#include "qat_sym_pmd.h"
+#include "qat_sym.h"
 #include "qat_comp_pmd.h"
 #include "adf_pf2vf_msg.h"
 #include "qat_pf2vf.h"
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 7f2fdc53ce..b36ffa6f6d 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -838,7 +838,8 @@ qat_dequeue_op_burst(void *qp, void **ops,
 
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_process_response(ops, resp_msg,
-   tmp_qp->op_cookies[head >> rx_queue->trailz]);
+   tmp_qp->op_cookies[head >> rx_queue->trailz],
+   NULL);
else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
nb_fw_responses = qat_comp_process_response(
ops, resp_msg,
diff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h
index 5ca76fcaa6..c01266f81c 100644
--- a/drivers/crypto/qat/qat_crypto.h
+++ b/drivers/crypto/qat/qat_crypto.h
@@ -12,7 +12,10 @@
 extern uint8_t qat_sym_driver_id;
 extern uint8_t qat_asym_driver_id;
 
-/** helper macro to set cryptodev capability range **/
+/**
+ * helper macro to set cryptodev capability range
+ * 
+ **/
 #define CAP_RNG(n, l, r, i) .n = {.min = l, .max = r, .increment = i}
 
 #define CAP_RNG_ZERO(n) .n = {.min = 0, .max = 0, .increment = 0}
diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index 83bf55c933..aad4b243b7 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -17,6 +17,27 @@ uint8_t qat_sym_driver_id;
 
 struct qat_crypto_gen_dev_ops qat_sym_gen_dev_ops[QAT_N_GENS];
 
+void
+qat_sym_init_op_cookie(void *op_cookie)
+{
+   struct qat_sym_op_cookie *cookie = op_cookie;
+
+   cookie->qat_sgl_src_phys_addr =
+   rte_mempool_virt2iova(cookie) +
+   offsetof(struct qat_sym_op_cookie,
+   qat_sgl_src);
+
+   cookie->qat_sgl_dst_phys_addr =
+   rte_mempool_virt2iova(cookie) +
+   offsetof(struct qat_sym_op_cookie,
+   qat_sgl_dst);
+
+   cookie->opt.spc_gmac.cd_phys_addr =
+   rte_mempool_virt2iova(cookie) +
+   offsetof(struct qat_sym_op_cookie,
+   opt.spc_gmac.cd_cipher);
+}
+
 static inline void
 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
struct icp_qat_fw_la_cipher_req_params *cipher_param,
diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h
index e3ec7f0de4..f4ff2ce4cd 100644
--- a/drivers/crypto/qat/q

[PATCH v11 6/9] crypto/qat: unify asymmetric functions

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch removes qat_asym_pmd.c and integrates all the
functions into qat_asym.c. The unified/integrated asym crypto
pmd functions should make them easier to maintain.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/common/qat/meson.build|   2 +-
 drivers/crypto/qat/qat_asym.c | 180 +++
 drivers/crypto/qat/qat_asym_pmd.c | 231 --
 drivers/crypto/qat/qat_asym_pmd.h |  54 ---
 4 files changed, 181 insertions(+), 286 deletions(-)
 delete mode 100644 drivers/crypto/qat/qat_asym_pmd.c
 delete mode 100644 drivers/crypto/qat/qat_asym_pmd.h

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 1bf6896a7e..f687f5c9d8 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -74,7 +74,7 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c',
+'qat_sym_hw_dp.c', 'qat_asym.c', 'qat_crypto.c',
 'dev/qat_sym_pmd_gen1.c',
 'dev/qat_asym_pmd_gen1.c',
 'dev/qat_crypto_pmd_gen2.c',
diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c
index d6ca1afae8..353c36534a 100644
--- a/drivers/crypto/qat/qat_asym.c
+++ b/drivers/crypto/qat/qat_asym.c
@@ -19,6 +19,32 @@ uint8_t qat_asym_driver_id;
 
 struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[QAT_N_GENS];
 
+void
+qat_asym_init_op_cookie(void *op_cookie)
+{
+   int j;
+   struct qat_asym_op_cookie *cookie = op_cookie;
+
+   cookie->input_addr = rte_mempool_virt2iova(cookie) +
+   offsetof(struct qat_asym_op_cookie,
+   input_params_ptrs);
+
+   cookie->output_addr = rte_mempool_virt2iova(cookie) +
+   offsetof(struct qat_asym_op_cookie,
+   output_params_ptrs);
+
+   for (j = 0; j < 8; j++) {
+   cookie->input_params_ptrs[j] =
+   rte_mempool_virt2iova(cookie) +
+   offsetof(struct qat_asym_op_cookie,
+   input_array[j]);
+   cookie->output_params_ptrs[j] =
+   rte_mempool_virt2iova(cookie) +
+   offsetof(struct qat_asym_op_cookie,
+   output_array[j]);
+   }
+}
+
 /* An rte_driver is needed in the registration of both the device and the 
driver
  * with cryptodev.
  * The actual qat pci's rte_driver can't be used as its name represents
@@ -788,6 +814,160 @@ qat_asym_session_clear(struct rte_cryptodev *dev,
memset(s, 0, qat_asym_session_get_private_size(dev));
 }
 
+static uint16_t
+qat_asym_crypto_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
+   uint16_t nb_ops)
+{
+   return qat_enqueue_op_burst(qp, qat_asym_build_request, (void **)ops,
+   nb_ops);
+}
+
+static uint16_t
+qat_asym_crypto_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
+   uint16_t nb_ops)
+{
+   return qat_dequeue_op_burst(qp, (void **)ops, qat_asym_process_response,
+   nb_ops);
+}
+
+int
+qat_asym_dev_create(struct qat_pci_device *qat_pci_dev,
+   struct qat_dev_cmd_param *qat_dev_cmd_param)
+{
+   struct qat_cryptodev_private *internals;
+   struct rte_cryptodev *cryptodev;
+   struct qat_device_info *qat_dev_instance =
+   &qat_pci_devs[qat_pci_dev->qat_dev_id];
+   struct rte_cryptodev_pmd_init_params init_params = {
+   .name = "",
+   .socket_id = qat_dev_instance->pci_dev->device.numa_node,
+   .private_data_size = sizeof(struct qat_cryptodev_private)
+   };
+   struct qat_capabilities_info capa_info;
+   const struct rte_cryptodev_capabilities *capabilities;
+   const struct qat_crypto_gen_dev_ops *gen_dev_ops =
+   &qat_asym_gen_dev_ops[qat_pci_dev->qat_dev_gen];
+   char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+   char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN];
+   uint64_t capa_size;
+   int i = 0;
+
+   snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s",
+   qat_pci_dev->name, "asym");
+   QAT_LOG(DEBUG, "Creating QAT ASYM device %s\n", name);
+
+   if (gen_dev_ops->cryptodev_ops == NULL) {
+   QAT_LOG(ERR, "Device %s does not support asymmetric crypto",
+   name);
+   return -(EFAULT);
+   }
+
+   if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
+   qat_pci_dev->qat_asym_driver_id =

[PATCH v11 7/9] crypto/qat: rework burst data path

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch enable the op_build_request function in
qat_enqueue_op_burst, and the qat_dequeue_process_response
function in qat_dequeue_op_burst.
The op_build_request invoked in crypto build request op is based
on crypto operations setup'd during session init.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/common/qat/qat_qp.c   |  42 +-
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c |   4 -
 drivers/crypto/qat/qat_asym.c |   2 +-
 drivers/crypto/qat/qat_asym.h |  22 -
 drivers/crypto/qat/qat_sym.c  | 830 +++---
 drivers/crypto/qat/qat_sym.h  |   5 -
 6 files changed, 271 insertions(+), 634 deletions(-)

diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index b36ffa6f6d..08ac91eac4 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -547,8 +547,7 @@ adf_modulo(uint32_t data, uint32_t modulo_mask)
 }
 
 uint16_t
-qat_enqueue_op_burst(void *qp,
-   __rte_unused qat_op_build_request_t op_build_request,
+qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,
void **ops, uint16_t nb_ops)
 {
register struct qat_queue *queue;
@@ -599,29 +598,18 @@ qat_enqueue_op_burst(void *qp,
}
}
 
-#ifdef BUILD_QAT_SYM
+#ifdef RTE_LIB_SECURITY
if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
qat_sym_preprocess_requests(ops, nb_ops_possible);
 #endif
 
+   memset(tmp_qp->opaque, 0xff, sizeof(tmp_qp->opaque));
+
while (nb_ops_sent != nb_ops_possible) {
-   if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC) {
-#ifdef BUILD_QAT_SYM
-   ret = qat_sym_build_request(*ops, base_addr + tail,
-   tmp_qp->op_cookies[tail >> queue->trailz],
-   tmp_qp->qat_dev_gen);
-#endif
-   } else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION) {
-   ret = qat_comp_build_request(*ops, base_addr + tail,
+   ret = op_build_request(*ops, base_addr + tail,
tmp_qp->op_cookies[tail >> queue->trailz],
-   tmp_qp->qat_dev_gen);
-   } else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
-#ifdef BUILD_QAT_ASYM
-   ret = qat_asym_build_request(*ops, base_addr + tail,
-   tmp_qp->op_cookies[tail >> queue->trailz],
-   NULL, tmp_qp->qat_dev_gen);
-#endif
-   }
+   tmp_qp->opaque, tmp_qp->qat_dev_gen);
+
if (ret != 0) {
tmp_qp->stats.enqueue_err_count++;
/* This message cannot be enqueued */
@@ -817,8 +805,7 @@ qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t 
nb_ops)
 
 uint16_t
 qat_dequeue_op_burst(void *qp, void **ops,
-   __rte_unused qat_op_dequeue_t qat_dequeue_process_response,
-   uint16_t nb_ops)
+   qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops)
 {
struct qat_queue *rx_queue;
struct qat_qp *tmp_qp = (struct qat_qp *)qp;
@@ -836,21 +823,10 @@ qat_dequeue_op_burst(void *qp, void **ops,
 
nb_fw_responses = 1;
 
-   if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
-   qat_sym_process_response(ops, resp_msg,
-   tmp_qp->op_cookies[head >> rx_queue->trailz],
-   NULL);
-   else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
-   nb_fw_responses = qat_comp_process_response(
+   nb_fw_responses = qat_dequeue_process_response(
ops, resp_msg,
tmp_qp->op_cookies[head >> rx_queue->trailz],
&tmp_qp->stats.dequeue_err_count);
-#ifdef BUILD_QAT_ASYM
-   else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)
-   qat_asym_process_response(ops, resp_msg,
-   tmp_qp->op_cookies[head >> rx_queue->trailz],
-   NULL);
-#endif
 
head = adf_modulo(head + rx_queue->msg_size,
  rx_queue->modulo_mask);
diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c 
b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
index ff176dddf1..c088fd50d2 100644
--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
@@ -146,10 +146,6 @@ struct rte_cryptodev_ops qat_sym_crypto_ops_gen1 = {
.sym_session_get_size   = qat_sym_session_get_private_size,
.sym_session_configure  = qat_sym_session_configure,

[PATCH v11 8/9] crypto/qat: unify raw data path functions

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch unifies QAT's raw dp api implementations
to the same enqueue/dequeue methods used in crypto operations.
The specific functions for different QAT generation are updated
respectively. The qat_sym_hw_dp.c is removed as no longer required.

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/common/qat/meson.build   |   2 +-
 drivers/compress/qat/qat_comp_pmd.c  |  12 +-
 drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c |   2 +
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 214 
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 122 +++
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  78 ++
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 656 
 drivers/crypto/qat/qat_crypto.h  |   3 +
 drivers/crypto/qat/qat_sym.c |  56 +-
 drivers/crypto/qat/qat_sym_hw_dp.c   | 986 ---
 10 files changed, 1137 insertions(+), 994 deletions(-)
 delete mode 100644 drivers/crypto/qat/qat_sym_hw_dp.c

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index f687f5c9d8..b7027f3164 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -74,7 +74,7 @@ endif
 
 if qat_crypto
 foreach f: ['qat_sym.c', 'qat_sym_session.c',
-'qat_sym_hw_dp.c', 'qat_asym.c', 'qat_crypto.c',
+'qat_asym.c', 'qat_crypto.c',
 'dev/qat_sym_pmd_gen1.c',
 'dev/qat_asym_pmd_gen1.c',
 'dev/qat_crypto_pmd_gen2.c',
diff --git a/drivers/compress/qat/qat_comp_pmd.c 
b/drivers/compress/qat/qat_comp_pmd.c
index efe5d08a99..dc8db84a68 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -616,11 +616,18 @@ static struct rte_compressdev_ops compress_qat_dummy_ops 
= {
.private_xform_free = qat_comp_private_xform_free
 };
 
+static uint16_t
+qat_comp_dequeue_burst(void *qp, struct rte_comp_op **ops,  uint16_t nb_ops)
+{
+   return qat_dequeue_op_burst(qp, (void **)ops, qat_comp_process_response,
+   nb_ops);
+}
+
 static uint16_t
 qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops,
   uint16_t nb_ops)
 {
-   uint16_t ret = qat_dequeue_op_burst(qp, (void **)ops, NULL, nb_ops);
+   uint16_t ret = qat_comp_dequeue_burst(qp, ops, nb_ops);
struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 
if (ret) {
@@ -638,8 +645,7 @@ qat_comp_pmd_dequeue_first_op_burst(void *qp, struct 
rte_comp_op **ops,
 
} else {
tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst =
-   (compressdev_dequeue_pkt_burst_t)
-   qat_comp_pmd_enq_deq_dummy_op_burst;
+   qat_comp_dequeue_burst;
}
}
return ret;
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c 
b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
index 64e6ae66ec..0c64c1e43f 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c
@@ -291,6 +291,8 @@ RTE_INIT(qat_sym_crypto_gen2_init)
qat_sym_crypto_cap_get_gen2;
qat_sym_gen_dev_ops[QAT_GEN2].set_session =
qat_sym_crypto_set_session_gen2;
+   qat_sym_gen_dev_ops[QAT_GEN2].set_raw_dp_ctx =
+   qat_sym_configure_raw_dp_ctx_gen1;
qat_sym_gen_dev_ops[QAT_GEN2].get_feature_flags =
qat_sym_crypto_feature_flags_get_gen1;
 
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c 
b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index db864d973a..ffa093a7a3 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -394,6 +394,218 @@ qat_sym_crypto_set_session_gen3(void *cdev __rte_unused, 
void *session)
return ret;
 }
 
+static int
+qat_sym_dp_enqueue_single_aead_gen3(void *qp_data, uint8_t *drv_ctx,
+   struct rte_crypto_vec *data, uint16_t n_data_vecs,
+   union rte_crypto_sym_ofs ofs,
+   struct rte_crypto_va_iova_ptr *iv,
+   struct rte_crypto_va_iova_ptr *digest,
+   struct rte_crypto_va_iova_ptr *aad,
+   void *user_data)
+{
+   struct qat_qp *qp = qp_data;
+   struct qat_sym_dp_ctx *dp_ctx = (void *)drv_ctx;
+   struct qat_queue *tx_queue = &qp->tx_q;
+   struct qat_sym_op_cookie *cookie;
+   struct qat_sym_session *ctx = dp_ctx->session;
+   struct icp_qat_fw_la_bulk_req *req;
+
+   int32_t data_len;
+   uint32_t tail = dp_ctx->tail;
+
+   req = (struct icp_qat_fw_la_bulk_req *)(
+   (uint8_t *)tx_queue->base_addr + tail);
+   cookie = qp->op_cookies[tail >> tx_queue->trailz];
+   tail

[PATCH v11 9/9] crypto/qat: support out of place SG list

2022-02-22 Thread Fan Zhang

From: Kai Ji 

This patch adds the SGL out of place support to QAT PMD

Signed-off-by: Kai Ji 
Acked-by: Fan Zhang 
---
 drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 28 --
 drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 14 -
 drivers/crypto/qat/dev/qat_sym_pmd_gen1.c| 55 +---
 3 files changed, 83 insertions(+), 14 deletions(-)

diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c 
b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index ffa093a7a3..5084a5fcd1 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -468,8 +468,18 @@ qat_sym_dp_enqueue_aead_jobs_gen3(void *qp_data, uint8_t 
*drv_ctx,
(uint8_t *)tx_queue->base_addr + tail);
rte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));
 
-   data_len = qat_sym_build_req_set_data(req, user_data[i], cookie,
-   vec->src_sgl[i].vec, vec->src_sgl[i].num, NULL, 0);
+   if (vec->dest_sgl) {
+   data_len = qat_sym_build_req_set_data(req,
+   user_data[i], cookie,
+   vec->src_sgl[i].vec, vec->src_sgl[i].num,
+   vec->dest_sgl[i].vec, vec->dest_sgl[i].num);
+   } else {
+   data_len = qat_sym_build_req_set_data(req,
+   user_data[i], cookie,
+   vec->src_sgl[i].vec,
+   vec->src_sgl[i].num, NULL, 0);
+   }
+
if (unlikely(data_len < 0))
break;
 
@@ -565,8 +575,18 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t 
*drv_ctx,
(uint8_t *)tx_queue->base_addr + tail);
rte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));
 
-   data_len = qat_sym_build_req_set_data(req, user_data[i], cookie,
-   vec->src_sgl[i].vec, vec->src_sgl[i].num, NULL, 0);
+   if (vec->dest_sgl) {
+   data_len = qat_sym_build_req_set_data(req,
+   user_data[i], cookie,
+   vec->src_sgl[i].vec, vec->src_sgl[i].num,
+   vec->dest_sgl[i].vec, vec->dest_sgl[i].num);
+   } else {
+   data_len = qat_sym_build_req_set_data(req,
+   user_data[i], cookie,
+   vec->src_sgl[i].vec,
+   vec->src_sgl[i].num, NULL, 0);
+   }
+
if (unlikely(data_len < 0))
break;
enqueue_one_auth_job_gen3(ctx, cookie, req, &vec->digest[i],
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c 
b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
index f803bc1459..bd7f3785df 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c
@@ -297,8 +297,18 @@ qat_sym_dp_enqueue_aead_jobs_gen4(void *qp_data, uint8_t 
*drv_ctx,
(uint8_t *)tx_queue->base_addr + tail);
rte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));
 
-   data_len = qat_sym_build_req_set_data(req, user_data[i], cookie,
-   vec->src_sgl[i].vec, vec->src_sgl[i].num, NULL, 0);
+   if (vec->dest_sgl) {
+   data_len = qat_sym_build_req_set_data(req,
+   user_data[i], cookie,
+   vec->src_sgl[i].vec, vec->src_sgl[i].num,
+   vec->dest_sgl[i].vec, vec->dest_sgl[i].num);
+   } else {
+   data_len = qat_sym_build_req_set_data(req,
+   user_data[i], cookie,
+   vec->src_sgl[i].vec,
+   vec->src_sgl[i].num, NULL, 0);
+   }
+
if (unlikely(data_len < 0))
break;
 
diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c 
b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
index 58f07eb0b3..3bcb53cf9f 100644
--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
@@ -526,9 +526,18 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t 
*drv_ctx,
(uint8_t *)tx_queue->base_addr + tail);
rte_mov128((uint8_t *)req, (const uint8_t *)&(ctx->fw_req));
 
-   data_len = qat_sym_build_req_set_data(req, user_data[i],
-   cookie, vec->src_sgl[i].vec,
+   if (vec->dest_sgl) {
+   data_len = qat_sym_build_req_set_data(req,
+   user_data[i], cookie

[dpdk-dev] maintainers: update for qat and ipsec-mb pmds

2021-05-20 Thread Fan Zhang

Add myself to Crypto API, QAT, SW PMDs based on ipsec-mb, and
NULL PMD maintainer.

Signed-off-by: Fan Zhang 
---
 MAINTAINERS | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a16971..11653b3dcd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -421,7 +421,7 @@ F: examples/bbdev_app/
 F: doc/guides/sample_app_ug/bbdev_app.rst
 
 Crypto API
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/cryptodev/
 F: app/test/test_cryptodev*
@@ -429,7 +429,7 @@ F: examples/l2fwd-crypto/
 
 Security API
 M: Akhil Goyal 
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/security/
 F: doc/guides/prog_guide/rte_security.rst
@@ -1031,23 +1031,22 @@ F: drivers/crypto/scheduler/
 F: doc/guides/cryptodevs/scheduler.rst
 
 Intel AES-NI GCM
-M: Declan Doherty 
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/aesni_gcm/
 F: doc/guides/cryptodevs/aesni_gcm.rst
 F: doc/guides/cryptodevs/features/aesni_gcm.ini
 
 Intel AES-NI Multi-Buffer
-M: Declan Doherty 
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/aesni_mb/
 F: doc/guides/cryptodevs/aesni_mb.rst
 F: doc/guides/cryptodevs/features/aesni_mb.ini
 
 Intel QuickAssist
-M: John Griffin 
 M: Fiona Trahe 
-M: Deepak Kumar Jain 
+M: Fan Zhang 
 F: drivers/crypto/qat/
 F: drivers/common/qat/
 F: doc/guides/cryptodevs/qat.rst
@@ -1055,6 +1054,7 @@ F: doc/guides/cryptodevs/features/qat.ini
 
 KASUMI
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/kasumi/
 F: doc/guides/cryptodevs/kasumi.rst
 F: doc/guides/cryptodevs/features/kasumi.ini
@@ -1081,7 +1081,7 @@ F: doc/guides/cryptodevs/octeontx2.rst
 F: doc/guides/cryptodevs/features/octeontx2.ini
 
 Null Crypto
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/null/
 F: doc/guides/cryptodevs/null.rst
 F: doc/guides/cryptodevs/features/null.ini
@@ -1108,13 +1108,14 @@ F: doc/guides/cryptodevs/dpaa2_sec.rst
 F: doc/guides/cryptodevs/features/dpaa2_sec.ini
 
 OpenSSL
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/openssl/
 F: doc/guides/cryptodevs/openssl.rst
 F: doc/guides/cryptodevs/features/openssl.ini
 
 SNOW 3G
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/snow3g/
 F: doc/guides/cryptodevs/snow3g.rst
 F: doc/guides/cryptodevs/features/snow3g.ini
@@ -1127,6 +1128,7 @@ F: doc/guides/cryptodevs/features/virtio.ini
 
 ZUC
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/zuc/
 F: doc/guides/cryptodevs/zuc.rst
 F: doc/guides/cryptodevs/features/zuc.ini
-- 
2.25.1

[dpdk-dev] [dpdk-dev v2] maintainers: update for qat and ipsec-mb pmds

2021-05-20 Thread Fan Zhang

Add myself to Crypto API, QAT, SW PMDs based on ipsec-mb, and
NULL PMD maintainer.

Signed-off-by: Fan Zhang 
Acked-by: Declan Doherty 
Acked-by: Fiona Trahe 
Acked-by: John Griffin 
---
V2:
- Remove Declan from crypto perf maintainer

 MAINTAINERS | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a16971..131a7aba73 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -421,7 +421,7 @@ F: examples/bbdev_app/
 F: doc/guides/sample_app_ug/bbdev_app.rst
 
 Crypto API
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/cryptodev/
 F: app/test/test_cryptodev*
@@ -429,7 +429,7 @@ F: examples/l2fwd-crypto/
 
 Security API
 M: Akhil Goyal 
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/security/
 F: doc/guides/prog_guide/rte_security.rst
@@ -1031,23 +1031,22 @@ F: drivers/crypto/scheduler/
 F: doc/guides/cryptodevs/scheduler.rst
 
 Intel AES-NI GCM
-M: Declan Doherty 
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/aesni_gcm/
 F: doc/guides/cryptodevs/aesni_gcm.rst
 F: doc/guides/cryptodevs/features/aesni_gcm.ini
 
 Intel AES-NI Multi-Buffer
-M: Declan Doherty 
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/aesni_mb/
 F: doc/guides/cryptodevs/aesni_mb.rst
 F: doc/guides/cryptodevs/features/aesni_mb.ini
 
 Intel QuickAssist
-M: John Griffin 
 M: Fiona Trahe 
-M: Deepak Kumar Jain 
+M: Fan Zhang 
 F: drivers/crypto/qat/
 F: drivers/common/qat/
 F: doc/guides/cryptodevs/qat.rst
@@ -1055,6 +1054,7 @@ F: doc/guides/cryptodevs/features/qat.ini
 
 KASUMI
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/kasumi/
 F: doc/guides/cryptodevs/kasumi.rst
 F: doc/guides/cryptodevs/features/kasumi.ini
@@ -1081,7 +1081,7 @@ F: doc/guides/cryptodevs/octeontx2.rst
 F: doc/guides/cryptodevs/features/octeontx2.ini
 
 Null Crypto
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/null/
 F: doc/guides/cryptodevs/null.rst
 F: doc/guides/cryptodevs/features/null.ini
@@ -1108,13 +1108,14 @@ F: doc/guides/cryptodevs/dpaa2_sec.rst
 F: doc/guides/cryptodevs/features/dpaa2_sec.ini
 
 OpenSSL
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/openssl/
 F: doc/guides/cryptodevs/openssl.rst
 F: doc/guides/cryptodevs/features/openssl.ini
 
 SNOW 3G
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/snow3g/
 F: doc/guides/cryptodevs/snow3g.rst
 F: doc/guides/cryptodevs/features/snow3g.ini
@@ -1127,6 +1128,7 @@ F: doc/guides/cryptodevs/features/virtio.ini
 
 ZUC
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/zuc/
 F: doc/guides/cryptodevs/zuc.rst
 F: doc/guides/cryptodevs/features/zuc.ini
@@ -1616,7 +1618,6 @@ F: app/test-compress-perf/
 F: doc/guides/tools/comp_perf.rst
 
 Crypto performance test application
-M: Declan Doherty 
 M: Ciara Power 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: app/test-crypto-perf/
-- 
2.25.1

[dpdk-dev] [dpdk-dev v3] maintainers: update for crypto api/crypto perf/sw crypto pmds using ipsec-mb

2021-05-21 Thread Fan Zhang

Add myself as Crypto API, QAT, SW PMDs based on ipsec-mb,
NULL PMD, and crypto perf test maintainer. Also remove
Declan, Deepak, and John from the maintainers of these
areas.

Signed-off-by: Fan Zhang 
Acked-by: Declan Doherty 
Acked-by: Fiona Trahe 
Acked-by: John Griffin 
---
 MAINTAINERS | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a16971..131a7aba73 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -421,7 +421,7 @@ F: examples/bbdev_app/
 F: doc/guides/sample_app_ug/bbdev_app.rst
 
 Crypto API
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/cryptodev/
 F: app/test/test_cryptodev*
@@ -429,7 +429,7 @@ F: examples/l2fwd-crypto/
 
 Security API
 M: Akhil Goyal 
-M: Declan Doherty 
+M: Fan Zhang 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: lib/security/
 F: doc/guides/prog_guide/rte_security.rst
@@ -1031,23 +1031,22 @@ F: drivers/crypto/scheduler/
 F: doc/guides/cryptodevs/scheduler.rst
 
 Intel AES-NI GCM
-M: Declan Doherty 
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/aesni_gcm/
 F: doc/guides/cryptodevs/aesni_gcm.rst
 F: doc/guides/cryptodevs/features/aesni_gcm.ini
 
 Intel AES-NI Multi-Buffer
-M: Declan Doherty 
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/aesni_mb/
 F: doc/guides/cryptodevs/aesni_mb.rst
 F: doc/guides/cryptodevs/features/aesni_mb.ini
 
 Intel QuickAssist
-M: John Griffin 
 M: Fiona Trahe 
-M: Deepak Kumar Jain 
+M: Fan Zhang 
 F: drivers/crypto/qat/
 F: drivers/common/qat/
 F: doc/guides/cryptodevs/qat.rst
@@ -1055,6 +1054,7 @@ F: doc/guides/cryptodevs/features/qat.ini
 
 KASUMI
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/kasumi/
 F: doc/guides/cryptodevs/kasumi.rst
 F: doc/guides/cryptodevs/features/kasumi.ini
@@ -1081,7 +1081,7 @@ F: doc/guides/cryptodevs/octeontx2.rst
 F: doc/guides/cryptodevs/features/octeontx2.ini
 
 Null Crypto
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/null/
 F: doc/guides/cryptodevs/null.rst
 F: doc/guides/cryptodevs/features/null.ini
@@ -1108,13 +1108,14 @@ F: doc/guides/cryptodevs/dpaa2_sec.rst
 F: doc/guides/cryptodevs/features/dpaa2_sec.ini
 
 OpenSSL
-M: Declan Doherty 
+M: Fan Zhang 
 F: drivers/crypto/openssl/
 F: doc/guides/cryptodevs/openssl.rst
 F: doc/guides/cryptodevs/features/openssl.ini
 
 SNOW 3G
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/snow3g/
 F: doc/guides/cryptodevs/snow3g.rst
 F: doc/guides/cryptodevs/features/snow3g.ini
@@ -1127,6 +1128,7 @@ F: doc/guides/cryptodevs/features/virtio.ini
 
 ZUC
 M: Pablo de Lara 
+M: Fan Zhang 
 F: drivers/crypto/zuc/
 F: doc/guides/cryptodevs/zuc.rst
 F: doc/guides/cryptodevs/features/zuc.ini
@@ -1616,7 +1618,6 @@ F: app/test-compress-perf/
 F: doc/guides/tools/comp_perf.rst
 
 Crypto performance test application
-M: Declan Doherty 
 M: Ciara Power 
 T: git://dpdk.org/next/dpdk-next-crypto
 F: app/test-crypto-perf/
-- 
2.25.1

[PATCH] crypto/qat: use intel-ipsec-mb for partial hash

2022-04-07 Thread Fan Zhang

Since openssl 3.0 now deprecates the low level API QAT required to
perform partial hash operation when creating the session. This
patch is to transfer such dependency from openssl to intel-ipsec-mb.

Signed-off-by: Fan Zhang 
---
 drivers/common/qat/meson.build   |  10 +++
 drivers/crypto/qat/qat_sym_session.c | 101 +--
 2 files changed, 28 insertions(+), 83 deletions(-)

diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index b7027f3164..d35fc69d96 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -35,6 +35,16 @@ if qat_crypto and not libcrypto.found()
 'missing dependency, libcrypto')
 endif
 
+
+IMB_required_ver = '1.0.0'
+libipsecmb = cc.find_library('IPSec_MB', required: false)
+if not lib.found()
+build = false
+reason = 'missing dependency, "libIPSec_MB"'
+else
+ext_deps += libipsecmb
+endif
+
 # The driver should not build if both compression and crypto are disabled
 #FIXME common code depends on compression files so check only compress!
 if not qat_compress # and not qat_crypto
diff --git a/drivers/crypto/qat/qat_sym_session.c 
b/drivers/crypto/qat/qat_sym_session.c
index 9d6a19c0be..05a11db750 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -6,6 +6,7 @@
 #include/* Needed to calculate pre-compute values */
 #include/* Needed to calculate pre-compute values */
 #include/* Needed for bpi runt block processing */
+#include 
 
 #include 
 #include 
@@ -1057,139 +1058,73 @@ static int qat_hash_get_block_size(enum 
icp_qat_hw_auth_algo qat_hash_alg)
return -EFAULT;
 }
 
-static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)
-{
-   SHA_CTX ctx;
-
-   if (!SHA1_Init(&ctx))
-   return -EFAULT;
-   SHA1_Transform(&ctx, data_in);
-   rte_memcpy(data_out, &ctx, SHA_DIGEST_LENGTH);
-   return 0;
-}
-
-static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
-{
-   SHA256_CTX ctx;
-
-   if (!SHA224_Init(&ctx))
-   return -EFAULT;
-   SHA256_Transform(&ctx, data_in);
-   rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
-   return 0;
-}
-
-static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
-{
-   SHA256_CTX ctx;
-
-   if (!SHA256_Init(&ctx))
-   return -EFAULT;
-   SHA256_Transform(&ctx, data_in);
-   rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
-   return 0;
-}
-
-static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
-{
-   SHA512_CTX ctx;
-
-   if (!SHA384_Init(&ctx))
-   return -EFAULT;
-   SHA512_Transform(&ctx, data_in);
-   rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
-   return 0;
-}
-
-static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
-{
-   SHA512_CTX ctx;
-
-   if (!SHA512_Init(&ctx))
-   return -EFAULT;
-   SHA512_Transform(&ctx, data_in);
-   rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
-   return 0;
-}
-
-static int partial_hash_md5(uint8_t *data_in, uint8_t *data_out)
-{
-   MD5_CTX ctx;
-
-   if (!MD5_Init(&ctx))
-   return -EFAULT;
-   MD5_Transform(&ctx, data_in);
-   rte_memcpy(data_out, &ctx, MD5_DIGEST_LENGTH);
-
-   return 0;
-}
-
 static int
 partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
uint8_t *data_in, uint8_t *data_out)
 {
+   IMB_MGR *m;
+   uint32_t *hash_state_out_be32;
+   uint64_t *hash_state_out_be64;
int digest_size;
uint8_t digest[qat_hash_get_digest_size(
ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
-   uint32_t *hash_state_out_be32;
-   uint64_t *hash_state_out_be64;
int i;
 
+   hash_state_out_be32 = (uint32_t *)data_out;
+   hash_state_out_be64 = (uint64_t *)data_out;
+
/* Initialize to avoid gcc warning */
memset(digest, 0, sizeof(digest));
 
digest_size = qat_hash_get_digest_size(hash_alg);
if (digest_size <= 0)
return -EFAULT;
+   m = alloc_mb_mgr(0);
+   if (m == NULL)
+   return -ENOMEM;
 
-   hash_state_out_be32 = (uint32_t *)data_out;
-   hash_state_out_be64 = (uint64_t *)data_out;
+   init_mb_mgr_auto(m, NULL);
 
switch (hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
-   if (partial_hash_sha1(data_in, digest))
-   return -EFAULT;
+   IMB_SHA1_ONE_BLOCK(m, data_in, digest);
for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
*hash_state_out_be32 =
rte_bswap32(*(((uint32_t *)digest)+i));
break;
case ICP_QAT_HW_AUTH_ALGO_SHA224:
-

[dpdk-dev] [PATCH] Scheduler: add driver for scheduler crypto pmd

2016-12-02 Thread Fan Zhang

This patch provides the initial implementation of the scheduler poll mode
driver using DPDK cryptodev framework.

Scheduler PMD is used to schedule and enqueue the crypto ops to the
hardware and/or software crypto devices attached to it (slaves). The
dequeue operation from the slave(s), and the possible dequeued crypto op
reordering, are then carried out by the scheduler.

The scheduler PMD can be used to fill the throughput gap between the
physical core and the existing cryptodevs to increase the overall
performance. For example, if a physical core has higher crypto op
processing rate than a cryptodev, the scheduler PMD can be introduced to
attach more than one cryptodevs.

This initial implementation is limited to supporting the following
scheduling modes:

- CRYPTO_SCHED_SW_ROUND_ROBIN_MODE (round robin amongst attached software
slave cryptodevs, to set this mode, the scheduler should have been
attached 1 or more software cryptodevs.

- CRYPTO_SCHED_HW_ROUND_ROBIN_MODE (round robin amongst attached hardware
slave cryptodevs (QAT), to set this mode, the scheduler should have
been attached 1 or more QATs.

Build instructions:
To build DPDK with CRYTPO_SCHEDULER_PMD the user is required to set
CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y in config/common_base

Notice:
Scheduler PMD shares same EAL commandline options as other cryptodevs.
In addition, one extra option "enable_reorder" exists. When it is set to
"yes", the dequeued crypto op reorder will take place. This feature can
be disabled by filling "no" in the "enable_reorder" option. For example,
the following EAL commandline fragment creates a scheduler PMD with
crypto op reordering feature enabled:

... --vdev "crypto_scheduler_pmd,enable_reorder=yes" ...

Signed-off-by: Fan Zhang 
---
 config/common_base |   6 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/scheduler/Makefile  |  64 +++
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 387 +
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h |  90 
 .../scheduler/rte_pmd_crypto_scheduler_version.map |   8 +
 drivers/crypto/scheduler/scheduler_pmd.c   | 475 +
 drivers/crypto/scheduler/scheduler_pmd_ops.c   | 335 +++
 drivers/crypto/scheduler/scheduler_pmd_private.h   | 137 ++
 lib/librte_cryptodev/rte_cryptodev.h   |   2 +
 mk/rte.app.mk  |   3 +-
 11 files changed, 1507 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/scheduler/Makefile
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.c
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.h
 create mode 100644 
drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd.c
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_ops.c
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_private.h

diff --git a/config/common_base b/config/common_base
index 4bff83a..79d120d 100644
--- a/config/common_base
+++ b/config/common_base
@@ -400,6 +400,12 @@ CONFIG_RTE_LIBRTE_PMD_KASUMI=n
 CONFIG_RTE_LIBRTE_PMD_KASUMI_DEBUG=n
 
 #
+# Compile PMD for Crypto Scheduler device
+#
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=n
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n
+
+#
 # Compile PMD for ZUC device
 #
 CONFIG_RTE_LIBRTE_PMD_ZUC=n
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 745c614..cdd3c94 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -38,6 +38,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += kasumi
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += zuc
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += null
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/crypto/scheduler/Makefile 
b/drivers/crypto/scheduler/Makefile
new file mode 100644
index 000..d8e1ff5
--- /dev/null
+++ b/drivers/crypto/scheduler/Makefile
@@ -0,0 +1,64 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+# * Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in
+#   the documentation and/or other materials provided with the
+#   distribution.
+# * Neither the name of Intel Corporation nor the names of its
+#   contributors may be used to endorse or promote products derived
+#

[dpdk-dev] test: fix GMAC SGL test

2020-10-29 Thread Fan Zhang

This ptach fixes the GMAC SGL test that fails to bypass
unsupported PMDs.

Fixes: dcdd01691f39 ("test/crypto: add GMAC SGL")
Cc: pablo.de.lara.gua...@intel.com

Signed-off-by: Fan Zhang 
---
 app/test/test_cryptodev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 0fed124d3..130719d67 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -11069,8 +11069,8 @@ test_AES_GMAC_authentication_SGL(const struct 
gmac_test_data *tdata,
rte_cryptodev_info_get(ts_params->valid_devs[0], &dev_info);
feature_flags = dev_info.feature_flags;
 
-   if ((!(feature_flags & RTE_CRYPTODEV_FF_IN_PLACE_SGL)) &&
-   (!(feature_flags & RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT)) 
&&
+   if ((!(feature_flags & RTE_CRYPTODEV_FF_IN_PLACE_SGL)) ||
+   (!(feature_flags & RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT)) 
||
(!(feature_flags & 
RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT)))
return -ENOTSUP;
 
-- 
2.26.2

[dpdk-dev] [dpdk-dev v2] test: fix GMAC SGL test

2020-10-29 Thread Fan Zhang

This patch fixes the GMAC SGL test that fails to bypass
unsupported PMDs.

Fixes: dcdd01691f39 ("test/crypto: add GMAC SGL")
Cc: pablo.de.lara.gua...@intel.com

Signed-off-by: Fan Zhang 
---
v2:
- fix typo
 app/test/test_cryptodev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 0fed124d3..130719d67 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -11069,8 +11069,8 @@ test_AES_GMAC_authentication_SGL(const struct 
gmac_test_data *tdata,
rte_cryptodev_info_get(ts_params->valid_devs[0], &dev_info);
feature_flags = dev_info.feature_flags;
 
-   if ((!(feature_flags & RTE_CRYPTODEV_FF_IN_PLACE_SGL)) &&
-   (!(feature_flags & RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT)) 
&&
+   if ((!(feature_flags & RTE_CRYPTODEV_FF_IN_PLACE_SGL)) ||
+   (!(feature_flags & RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT)) 
||
(!(feature_flags & 
RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT)))
return -ENOTSUP;
 
-- 
2.26.2

[dpdk-dev] [PATCH] crypto/aesni_mb: fix cpu crypto cipher auth

2020-10-29 Thread Fan Zhang

This patch fixes the AESNI-MB PMD CPU crypto process function. Orignally
the function tried to access crypto vector's aad buffer even it is not
needed.

Fixes: 8d928d47a29a ("cryptodev: change crypto symmetric vector structure")
Cc: roy.fan.zh...@intel.com

Signed-off-by: Fan Zhang 
---
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 69 +++---
 1 file changed, 49 insertions(+), 20 deletions(-)

diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c 
b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index fbbb38af0..53834f9f3 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -1990,33 +1990,62 @@ aesni_mb_cpu_crypto_process_bulk(struct rte_cryptodev 
*dev,
RTE_PER_LCORE(sync_mb_mgr) = mb_mgr;
}
 
-   for (i = 0, j = 0, k = 0; i != vec->num; i++) {
+   if (is_aead_algo(s->auth.algo, s->cipher.mode)) {
+   for (i = 0, j = 0, k = 0; i != vec->num; i++) {
+   ret = check_crypto_sgl(sofs, vec->sgl + i);
+   if (ret != 0) {
+   vec->status[i] = ret;
+   continue;
+   }
 
+   buf = vec->sgl[i].vec[0].base;
+   len = vec->sgl[i].vec[0].len;
 
-   ret = check_crypto_sgl(sofs, vec->sgl + i);
-   if (ret != 0) {
-   vec->status[i] = ret;
-   continue;
+   job = IMB_GET_NEXT_JOB(mb_mgr);
+   if (job == NULL) {
+   k += flush_mb_sync_mgr(mb_mgr);
+   job = IMB_GET_NEXT_JOB(mb_mgr);
+   RTE_ASSERT(job != NULL);
+   }
+
+   /* Submit job for processing */
+   set_cpu_mb_job_params(job, s, sofs, buf, len,
+   vec->iv[i].va, vec->aad[i].va, tmp_dgst[i],
+   &vec->status[i]);
+   job = submit_sync_job(mb_mgr);
+   j++;
+
+   /* handle completed jobs */
+   k += handle_completed_sync_jobs(job, mb_mgr);
}
+   } else {
+   for (i = 0, j = 0, k = 0; i != vec->num; i++) {
+   ret = check_crypto_sgl(sofs, vec->sgl + i);
+   if (ret != 0) {
+   vec->status[i] = ret;
+   continue;
+   }
 
-   buf = vec->sgl[i].vec[0].base;
-   len = vec->sgl[i].vec[0].len;
+   buf = vec->sgl[i].vec[0].base;
+   len = vec->sgl[i].vec[0].len;
 
-   job = IMB_GET_NEXT_JOB(mb_mgr);
-   if (job == NULL) {
-   k += flush_mb_sync_mgr(mb_mgr);
job = IMB_GET_NEXT_JOB(mb_mgr);
-   RTE_ASSERT(job != NULL);
+   if (job == NULL) {
+   k += flush_mb_sync_mgr(mb_mgr);
+   job = IMB_GET_NEXT_JOB(mb_mgr);
+   RTE_ASSERT(job != NULL);
+   }
+
+   /* Submit job for processing */
+   set_cpu_mb_job_params(job, s, sofs, buf, len,
+   vec->iv[i].va, NULL, tmp_dgst[i],
+   &vec->status[i]);
+   job = submit_sync_job(mb_mgr);
+   j++;
+
+   /* handle completed jobs */
+   k += handle_completed_sync_jobs(job, mb_mgr);
}
-
-   /* Submit job for processing */
-   set_cpu_mb_job_params(job, s, sofs, buf, len, vec->iv[i].va,
-   vec->aad[i].va, tmp_dgst[i], &vec->status[i]);
-   job = submit_sync_job(mb_mgr);
-   j++;
-
-   /* handle completed jobs */
-   k += handle_completed_sync_jobs(job, mb_mgr);
}
 
/* flush remaining jobs */
-- 
2.26.2

[dpdk-dev] [dpdk-dev v2] crypto/aesni_mb: fix cpu crypto cipher auth

2020-10-29 Thread Fan Zhang

This patch fixes the AESNI-MB PMD CPU crypto process function. Originally
the function tried to access crypto vector's aad buffer even it is not
needed.

Fixes: 8d928d47a29a ("cryptodev: change crypto symmetric vector structure")
Cc: roy.fan.zh...@intel.com

Signed-off-by: Fan Zhang 
---
V2:
- fix typo.

 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 69 +++---
 1 file changed, 49 insertions(+), 20 deletions(-)

diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c 
b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
index fbbb38af0..53834f9f3 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c
@@ -1990,33 +1990,62 @@ aesni_mb_cpu_crypto_process_bulk(struct rte_cryptodev 
*dev,
RTE_PER_LCORE(sync_mb_mgr) = mb_mgr;
}
 
-   for (i = 0, j = 0, k = 0; i != vec->num; i++) {
+   if (is_aead_algo(s->auth.algo, s->cipher.mode)) {
+   for (i = 0, j = 0, k = 0; i != vec->num; i++) {
+   ret = check_crypto_sgl(sofs, vec->sgl + i);
+   if (ret != 0) {
+   vec->status[i] = ret;
+   continue;
+   }
 
+   buf = vec->sgl[i].vec[0].base;
+   len = vec->sgl[i].vec[0].len;
 
-   ret = check_crypto_sgl(sofs, vec->sgl + i);
-   if (ret != 0) {
-   vec->status[i] = ret;
-   continue;
+   job = IMB_GET_NEXT_JOB(mb_mgr);
+   if (job == NULL) {
+   k += flush_mb_sync_mgr(mb_mgr);
+   job = IMB_GET_NEXT_JOB(mb_mgr);
+   RTE_ASSERT(job != NULL);
+   }
+
+   /* Submit job for processing */
+   set_cpu_mb_job_params(job, s, sofs, buf, len,
+   vec->iv[i].va, vec->aad[i].va, tmp_dgst[i],
+   &vec->status[i]);
+   job = submit_sync_job(mb_mgr);
+   j++;
+
+   /* handle completed jobs */
+   k += handle_completed_sync_jobs(job, mb_mgr);
}
+   } else {
+   for (i = 0, j = 0, k = 0; i != vec->num; i++) {
+   ret = check_crypto_sgl(sofs, vec->sgl + i);
+   if (ret != 0) {
+   vec->status[i] = ret;
+   continue;
+   }
 
-   buf = vec->sgl[i].vec[0].base;
-   len = vec->sgl[i].vec[0].len;
+   buf = vec->sgl[i].vec[0].base;
+   len = vec->sgl[i].vec[0].len;
 
-   job = IMB_GET_NEXT_JOB(mb_mgr);
-   if (job == NULL) {
-   k += flush_mb_sync_mgr(mb_mgr);
job = IMB_GET_NEXT_JOB(mb_mgr);
-   RTE_ASSERT(job != NULL);
+   if (job == NULL) {
+   k += flush_mb_sync_mgr(mb_mgr);
+   job = IMB_GET_NEXT_JOB(mb_mgr);
+   RTE_ASSERT(job != NULL);
+   }
+
+   /* Submit job for processing */
+   set_cpu_mb_job_params(job, s, sofs, buf, len,
+   vec->iv[i].va, NULL, tmp_dgst[i],
+   &vec->status[i]);
+   job = submit_sync_job(mb_mgr);
+   j++;
+
+   /* handle completed jobs */
+   k += handle_completed_sync_jobs(job, mb_mgr);
}
-
-   /* Submit job for processing */
-   set_cpu_mb_job_params(job, s, sofs, buf, len, vec->iv[i].va,
-   vec->aad[i].va, tmp_dgst[i], &vec->status[i]);
-   job = submit_sync_job(mb_mgr);
-   j++;
-
-   /* handle completed jobs */
-   k += handle_completed_sync_jobs(job, mb_mgr);
}
 
/* flush remaining jobs */
-- 
2.26.2

[dpdk-dev] [PATCH] cryptodev: fix for loop in rte_cryptodev_pmd_get_named_dev

2017-01-11 Thread Fan Zhang

Fixes: d11b0f30 ("cryptodev: introduce API and framework for crypto devices")

This patch fixes the dev value update problem in
rte_cryptodev_pmd_get_named_dev, orginally, dev won't be updated
after the initiail step in the loop.

Signed-off-by: Fan Zhang 
---
 lib/librte_cryptodev/rte_cryptodev_pmd.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/lib/librte_cryptodev/rte_cryptodev_pmd.h 
b/lib/librte_cryptodev/rte_cryptodev_pmd.h
index abfe2dc..c6a5794 100644
--- a/lib/librte_cryptodev/rte_cryptodev_pmd.h
+++ b/lib/librte_cryptodev/rte_cryptodev_pmd.h
@@ -183,8 +183,9 @@ rte_cryptodev_pmd_get_named_dev(const char *name)
if (name == NULL)
return NULL;
 
-   for (i = 0, dev = &rte_cryptodev_globals->devs[i];
-   i < rte_cryptodev_globals->max_devs; i++) {
+   for (i = 0; i < rte_cryptodev_globals->max_devs; i++) {
+   dev = &rte_cryptodev_globals->devs[i];
+
if ((dev->attached == RTE_CRYPTODEV_ATTACHED) &&
(strcmp(dev->data->name, name) == 0))
return dev;
-- 
2.7.4

[dpdk-dev] [PATCH 1/2] cryptodev: add user defined name initializing parameter to software PMD

2017-01-11 Thread Fan Zhang

This patch adds a user defined name initializing parameter to cryptodev
library.

Originally, for software cryptodev PMD, the vdev name parameter is
treated as the driver identifier, and will create an unique name for each
device automatically, which is not necessarily as same as the vdev
parameter.

This patch allows the user to either create a unique name for his software
cryptodev, or by default, let the system creates a unique one. This should
help the user managing the created cryptodevs easily.

Examples:
CLI command fragment 1: --vdev "crypto_aesni_gcm_pmd"
The above command will result in creating a AESNI-GCM PMD with name of
"crypto_aesni_gcm_X", where postfix X is the number assigned by the system,
starting from 0. This fragment can be placed in the same CLI command
multiple times, resulting the postfixs incremented by one for each new
device.

CLI command fragment 2: --vdev "crypto_aesni_gcm_pmd,name=gcm1"
The above command will result in creating a AESNI-GCM PMD with name of
"gcm1". This fragment can be placed in the same CLI command multiple
times, as long as each having a unique name value.

Signed-off-by: Fan Zhang 
---
 lib/librte_cryptodev/rte_cryptodev.c | 45 
 lib/librte_cryptodev/rte_cryptodev.h |  7 +++--
 lib/librte_cryptodev/rte_cryptodev_pmd.h |  7 +
 3 files changed, 55 insertions(+), 4 deletions(-)

diff --git a/lib/librte_cryptodev/rte_cryptodev.c 
b/lib/librte_cryptodev/rte_cryptodev.c
index 127e8d0..3b6da8b 100644
--- a/lib/librte_cryptodev/rte_cryptodev.c
+++ b/lib/librte_cryptodev/rte_cryptodev.c
@@ -101,11 +101,13 @@ struct rte_cryptodev_callback {
uint32_t active;/**< Callback is executing */
 };
 
+#define RTE_CRYPTODEV_VDEV_NAME("name")
 #define RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG   ("max_nb_queue_pairs")
 #define RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG ("max_nb_sessions")
 #define RTE_CRYPTODEV_VDEV_SOCKET_ID   ("socket_id")
 
 static const char *cryptodev_vdev_valid_params[] = {
+   RTE_CRYPTODEV_VDEV_NAME,
RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG,
RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG,
RTE_CRYPTODEV_VDEV_SOCKET_ID
@@ -143,6 +145,18 @@ parse_integer_arg(const char *key __rte_unused,
return 0;
 }
 
+/** Parse name */
+static int
+parse_name_arg(const char *key __rte_unused,
+   const char *value, void *extra_args)
+{
+   struct rte_crypto_vdev_init_params *params = extra_args;
+
+   strncpy(params->name, value, RTE_CRYPTODEV_NAME_MAX_LEN);
+
+   return 0;
+}
+
 int
 rte_cryptodev_parse_vdev_init_params(struct rte_crypto_vdev_init_params 
*params,
const char *input_args)
@@ -179,6 +193,12 @@ rte_cryptodev_parse_vdev_init_params(struct 
rte_crypto_vdev_init_params *params,
if (ret < 0)
goto free_kvlist;
 
+   ret = rte_kvargs_process(kvlist, RTE_CRYPTODEV_VDEV_NAME,
+   &parse_name_arg,
+   params);
+   if (ret < 0)
+   goto free_kvlist;
+
if (params->socket_id >= number_of_sockets()) {
CDEV_LOG_ERR("Invalid socket id specified to create "
"the virtual crypto device on");
@@ -1205,3 +1225,28 @@ rte_crypto_op_pool_create(const char *name, enum 
rte_crypto_op_type type,
 
return mp;
 }
+
+int
+rte_cryptodev_pmd_create_dev_name(char *name, const char *dev_name_prefix)
+{
+   struct rte_cryptodev *dev = NULL;
+   uint32_t i = 0;
+
+   if (name == NULL)
+   return -EINVAL;
+
+   for (i = 0; i < RTE_CRYPTO_MAX_DEVS; i++) {
+   int ret = snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN,
+   "%s_%u", dev_name_prefix, i);
+
+   if (ret < 0)
+   return ret;
+
+   dev = rte_cryptodev_pmd_get_named_dev(name);
+   if (!dev)
+   return 0;
+   }
+
+   return -1;
+}
+
diff --git a/lib/librte_cryptodev/rte_cryptodev.h 
b/lib/librte_cryptodev/rte_cryptodev.h
index 8f63e8f..b5399af 100644
--- a/lib/librte_cryptodev/rte_cryptodev.h
+++ b/lib/librte_cryptodev/rte_cryptodev.h
@@ -300,6 +300,8 @@ struct rte_cryptodev_stats {
/**< Total error count on operations dequeued */
 };
 
+#define RTE_CRYPTODEV_NAME_MAX_LEN (64)
+/**< Max length of name of crypto PMD */
 #define RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_QUEUE_PAIRS  8
 #define RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS 2048
 
@@ -311,6 +313,7 @@ struct rte_crypto_vdev_init_params {
unsigned max_nb_queue_pairs;
unsigned max_nb_sessions;
uint8_t socket_id;
+   char name[RTE_CRYPTODEV_NAM

[dpdk-dev] [PATCH 2/2] crypto: add user defined name initializing parameter parsing to software PMDs

2017-01-11 Thread Fan Zhang

This patch adds user defined name parsing feature to software PMDs.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/aesni_gcm/aesni_gcm_pmd.c   | 58 ++--
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 61 ++
 drivers/crypto/kasumi/rte_kasumi_pmd.c | 58 +++-
 drivers/crypto/null/null_crypto_pmd.c  | 55 ++-
 drivers/crypto/openssl/rte_openssl_pmd.c   | 55 ++-
 drivers/crypto/snow3g/rte_snow3g_pmd.c | 59 +++--
 drivers/crypto/zuc/rte_zuc_pmd.c   | 59 +++--
 7 files changed, 148 insertions(+), 257 deletions(-)

diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c 
b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
index dba5e15..ddb2e0e 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
@@ -43,27 +43,6 @@
 
 #include "aesni_gcm_pmd_private.h"
 
-/**
- * Global static parameter used to create a unique name for each AES-NI multi
- * buffer crypto device.
- */
-static unsigned unique_name_id;
-
-static inline int
-create_unique_device_name(char *name, size_t size)
-{
-   int ret;
-
-   if (name == NULL)
-   return -EINVAL;
-
-   ret = snprintf(name, size, "%s_%u", 
RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD),
-   unique_name_id++);
-   if (ret < 0)
-   return ret;
-   return 0;
-}
-
 static int
 aesni_gcm_calculate_hash_sub_key(uint8_t *hsubkey, unsigned hsubkey_length,
uint8_t *aeskey, unsigned aeskey_length)
@@ -407,14 +386,23 @@ aesni_gcm_pmd_dequeue_burst(void *queue_pair,
 static int aesni_gcm_remove(const char *name);
 
 static int
-aesni_gcm_create(const char *name,
-   struct rte_crypto_vdev_init_params *init_params)
+aesni_gcm_create(struct rte_crypto_vdev_init_params *init_params)
 {
struct rte_cryptodev *dev;
-   char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct aesni_gcm_private *internals;
enum aesni_gcm_vector_mode vector_mode;
 
+   if (init_params->name[0] == '\0') {
+   int ret = rte_cryptodev_pmd_create_dev_name(
+   init_params->name,
+   RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));
+
+   if (ret < 0) {
+   GCM_LOG_ERR("failed to create unique name");
+   return ret;
+   }
+   }
+
/* Check CPU for support for AES instruction set */
if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {
GCM_LOG_ERR("AES instructions not supported by CPU");
@@ -433,15 +421,7 @@ aesni_gcm_create(const char *name,
return -EFAULT;
}
 
-   /* create a unique device name */
-   if (create_unique_device_name(crypto_dev_name,
-   RTE_CRYPTODEV_NAME_MAX_LEN) != 0) {
-   GCM_LOG_ERR("failed to create unique cryptodev name");
-   return -EINVAL;
-   }
-
-
-   dev = rte_cryptodev_pmd_virtual_dev_init(crypto_dev_name,
+   dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
sizeof(struct aesni_gcm_private), 
init_params->socket_id);
if (dev == NULL) {
GCM_LOG_ERR("failed to create cryptodev vdev");
@@ -484,9 +464,9 @@ aesni_gcm_create(const char *name,
return 0;
 
 init_error:
-   GCM_LOG_ERR("driver %s: create failed", name);
+   GCM_LOG_ERR("driver %s: create failed", init_params->name);
 
-   aesni_gcm_remove(crypto_dev_name);
+   aesni_gcm_remove(init_params->name);
return -EFAULT;
 }
 
@@ -496,19 +476,23 @@ aesni_gcm_probe(const char *name, const char *input_args)
struct rte_crypto_vdev_init_params init_params = {
RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_QUEUE_PAIRS,
RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS,
-   rte_socket_id()
+   rte_socket_id(),
+   {0}
};
 
rte_cryptodev_parse_vdev_init_params(&init_params, input_args);
 
RTE_LOG(INFO, PMD, "Initialising %s on NUMA node %d\n", name,
init_params.socket_id);
+   if (init_params.name[0] != '\0')
+   RTE_LOG(INFO, PMD, "  User defined name = %s\n",
+   init_params.name);
RTE_LOG(INFO, PMD, "  Max number of queue pairs = %d\n",
init_params.max_nb_queue_pairs);
RTE_LOG(INFO, PMD, "  Max number of sessions = %d\n",
init_params.max_nb_sessions);
 
-   return aesni_gcm_create(name, &init_params);
+   return aesni_gcm_create(&init_params);
 }
 
 static int
diff --git a/drivers/crypto/aesni_

[dpdk-dev] [PATCH 0/2] crypto: add user defined name initializing parameter

2017-01-11 Thread Fan Zhang

This patchset adds a user defined name initializing parameter to all
software cryptodevs.

Fan Zhang (2):
  cryptodev: add user defined name initializing parameter to software
PMD
  crypto: add user defined name initializing parameter parsing to
software PMDs

 drivers/crypto/aesni_gcm/aesni_gcm_pmd.c   | 58 ++--
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 61 ++
 drivers/crypto/kasumi/rte_kasumi_pmd.c | 58 +++-
 drivers/crypto/null/null_crypto_pmd.c  | 55 ++-
 drivers/crypto/openssl/rte_openssl_pmd.c   | 55 ++-
 drivers/crypto/snow3g/rte_snow3g_pmd.c | 59 +++--
 drivers/crypto/zuc/rte_zuc_pmd.c   | 59 +++--
 lib/librte_cryptodev/rte_cryptodev.c   | 45 ++
 lib/librte_cryptodev/rte_cryptodev.h   |  7 ++--
 lib/librte_cryptodev/rte_cryptodev_pmd.h   |  7 
 10 files changed, 203 insertions(+), 261 deletions(-)

-- 
2.7.4

[dpdk-dev] [PATCH v2 2/2] crypto: add user defined name initializing parameter parsing to software PMDs

2017-01-12 Thread Fan Zhang

This patch adds user defined name parsing feature to software PMDs.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/aesni_gcm/aesni_gcm_pmd.c   | 58 ++--
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 61 ++
 drivers/crypto/kasumi/rte_kasumi_pmd.c | 58 +++-
 drivers/crypto/null/null_crypto_pmd.c  | 55 ++-
 drivers/crypto/openssl/rte_openssl_pmd.c   | 55 ++-
 drivers/crypto/snow3g/rte_snow3g_pmd.c | 59 +++--
 drivers/crypto/zuc/rte_zuc_pmd.c   | 59 +++--
 7 files changed, 148 insertions(+), 257 deletions(-)

diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c 
b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
index dba5e15..ddb2e0e 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
@@ -43,27 +43,6 @@
 
 #include "aesni_gcm_pmd_private.h"
 
-/**
- * Global static parameter used to create a unique name for each AES-NI multi
- * buffer crypto device.
- */
-static unsigned unique_name_id;
-
-static inline int
-create_unique_device_name(char *name, size_t size)
-{
-   int ret;
-
-   if (name == NULL)
-   return -EINVAL;
-
-   ret = snprintf(name, size, "%s_%u", 
RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD),
-   unique_name_id++);
-   if (ret < 0)
-   return ret;
-   return 0;
-}
-
 static int
 aesni_gcm_calculate_hash_sub_key(uint8_t *hsubkey, unsigned hsubkey_length,
uint8_t *aeskey, unsigned aeskey_length)
@@ -407,14 +386,23 @@ aesni_gcm_pmd_dequeue_burst(void *queue_pair,
 static int aesni_gcm_remove(const char *name);
 
 static int
-aesni_gcm_create(const char *name,
-   struct rte_crypto_vdev_init_params *init_params)
+aesni_gcm_create(struct rte_crypto_vdev_init_params *init_params)
 {
struct rte_cryptodev *dev;
-   char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct aesni_gcm_private *internals;
enum aesni_gcm_vector_mode vector_mode;
 
+   if (init_params->name[0] == '\0') {
+   int ret = rte_cryptodev_pmd_create_dev_name(
+   init_params->name,
+   RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));
+
+   if (ret < 0) {
+   GCM_LOG_ERR("failed to create unique name");
+   return ret;
+   }
+   }
+
/* Check CPU for support for AES instruction set */
if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {
GCM_LOG_ERR("AES instructions not supported by CPU");
@@ -433,15 +421,7 @@ aesni_gcm_create(const char *name,
return -EFAULT;
}
 
-   /* create a unique device name */
-   if (create_unique_device_name(crypto_dev_name,
-   RTE_CRYPTODEV_NAME_MAX_LEN) != 0) {
-   GCM_LOG_ERR("failed to create unique cryptodev name");
-   return -EINVAL;
-   }
-
-
-   dev = rte_cryptodev_pmd_virtual_dev_init(crypto_dev_name,
+   dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
sizeof(struct aesni_gcm_private), 
init_params->socket_id);
if (dev == NULL) {
GCM_LOG_ERR("failed to create cryptodev vdev");
@@ -484,9 +464,9 @@ aesni_gcm_create(const char *name,
return 0;
 
 init_error:
-   GCM_LOG_ERR("driver %s: create failed", name);
+   GCM_LOG_ERR("driver %s: create failed", init_params->name);
 
-   aesni_gcm_remove(crypto_dev_name);
+   aesni_gcm_remove(init_params->name);
return -EFAULT;
 }
 
@@ -496,19 +476,23 @@ aesni_gcm_probe(const char *name, const char *input_args)
struct rte_crypto_vdev_init_params init_params = {
RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_QUEUE_PAIRS,
RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS,
-   rte_socket_id()
+   rte_socket_id(),
+   {0}
};
 
rte_cryptodev_parse_vdev_init_params(&init_params, input_args);
 
RTE_LOG(INFO, PMD, "Initialising %s on NUMA node %d\n", name,
init_params.socket_id);
+   if (init_params.name[0] != '\0')
+   RTE_LOG(INFO, PMD, "  User defined name = %s\n",
+   init_params.name);
RTE_LOG(INFO, PMD, "  Max number of queue pairs = %d\n",
init_params.max_nb_queue_pairs);
RTE_LOG(INFO, PMD, "  Max number of sessions = %d\n",
init_params.max_nb_sessions);
 
-   return aesni_gcm_create(name, &init_params);
+   return aesni_gcm_create(&init_params);
 }
 
 static int
diff --git a/drivers/crypto/aesni_

[dpdk-dev] [PATCH v2 1/2] cryptodev: add user defined name initializing parameter to software PMD

2017-01-12 Thread Fan Zhang

This patch adds a user defined name initializing parameter to cryptodev
library.

Originally, for software cryptodev PMD, the vdev name parameter is
treated as the driver identifier, and will create an unique name for each
device automatically, which is not necessarily as same as the vdev
parameter.

This patch allows the user to either create a unique name for his software
cryptodev, or by default, let the system creates a unique one. This should
help the user managing the created cryptodevs easily.

Examples:
CLI command fragment 1: --vdev "crypto_aesni_gcm_pmd"
The above command will result in creating a AESNI-GCM PMD with name of
"crypto_aesni_gcm_X", where postfix X is the number assigned by the system,
starting from 0. This fragment can be placed in the same CLI command
multiple times, resulting the postfixs incremented by one for each new
device.

CLI command fragment 2: --vdev "crypto_aesni_gcm_pmd,name=gcm1"
The above command will result in creating a AESNI-GCM PMD with name of
"gcm1". This fragment can be placed in the same CLI command multiple
times, as long as each having a unique name value.

Signed-off-by: Fan Zhang 
---
 lib/librte_cryptodev/rte_cryptodev.c   | 44 ++
 lib/librte_cryptodev/rte_cryptodev.h   |  7 ++--
 lib/librte_cryptodev/rte_cryptodev_pmd.h   |  7 
 lib/librte_cryptodev/rte_cryptodev_version.map |  7 
 4 files changed, 61 insertions(+), 4 deletions(-)

diff --git a/lib/librte_cryptodev/rte_cryptodev.c 
b/lib/librte_cryptodev/rte_cryptodev.c
index 127e8d0..08c9eb4 100644
--- a/lib/librte_cryptodev/rte_cryptodev.c
+++ b/lib/librte_cryptodev/rte_cryptodev.c
@@ -101,11 +101,13 @@ struct rte_cryptodev_callback {
uint32_t active;/**< Callback is executing */
 };
 
+#define RTE_CRYPTODEV_VDEV_NAME("name")
 #define RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG   ("max_nb_queue_pairs")
 #define RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG ("max_nb_sessions")
 #define RTE_CRYPTODEV_VDEV_SOCKET_ID   ("socket_id")
 
 static const char *cryptodev_vdev_valid_params[] = {
+   RTE_CRYPTODEV_VDEV_NAME,
RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG,
RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG,
RTE_CRYPTODEV_VDEV_SOCKET_ID
@@ -143,6 +145,18 @@ parse_integer_arg(const char *key __rte_unused,
return 0;
 }
 
+/** Parse name */
+static int
+parse_name_arg(const char *key __rte_unused,
+   const char *value, void *extra_args)
+{
+   struct rte_crypto_vdev_init_params *params = extra_args;
+
+   strncpy(params->name, value, RTE_CRYPTODEV_NAME_MAX_LEN);
+
+   return 0;
+}
+
 int
 rte_cryptodev_parse_vdev_init_params(struct rte_crypto_vdev_init_params 
*params,
const char *input_args)
@@ -179,6 +193,12 @@ rte_cryptodev_parse_vdev_init_params(struct 
rte_crypto_vdev_init_params *params,
if (ret < 0)
goto free_kvlist;
 
+   ret = rte_kvargs_process(kvlist, RTE_CRYPTODEV_VDEV_NAME,
+   &parse_name_arg,
+   params);
+   if (ret < 0)
+   goto free_kvlist;
+
if (params->socket_id >= number_of_sockets()) {
CDEV_LOG_ERR("Invalid socket id specified to create "
"the virtual crypto device on");
@@ -1205,3 +1225,27 @@ rte_crypto_op_pool_create(const char *name, enum 
rte_crypto_op_type type,
 
return mp;
 }
+
+int
+rte_cryptodev_pmd_create_dev_name(char *name, const char *dev_name_prefix)
+{
+   struct rte_cryptodev *dev = NULL;
+   uint32_t i = 0;
+
+   if (name == NULL)
+   return -EINVAL;
+
+   for (i = 0; i < RTE_CRYPTO_MAX_DEVS; i++) {
+   int ret = snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN,
+   "%s_%u", dev_name_prefix, i);
+
+   if (ret < 0)
+   return ret;
+
+   dev = rte_cryptodev_pmd_get_named_dev(name);
+   if (!dev)
+   return 0;
+   }
+
+   return -1;
+}
diff --git a/lib/librte_cryptodev/rte_cryptodev.h 
b/lib/librte_cryptodev/rte_cryptodev.h
index 8f63e8f..b5399af 100644
--- a/lib/librte_cryptodev/rte_cryptodev.h
+++ b/lib/librte_cryptodev/rte_cryptodev.h
@@ -300,6 +300,8 @@ struct rte_cryptodev_stats {
/**< Total error count on operations dequeued */
 };
 
+#define RTE_CRYPTODEV_NAME_MAX_LEN (64)
+/**< Max length of name of crypto PMD */
 #define RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_QUEUE_PAIRS  8
 #define RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS 2048
 
@@ -311,6 +313,7 @@ struct rte_crypto_vdev_init_params {
unsigned max_nb_queue_pairs;
unsigned

[dpdk-dev] [PATCH v2 0/2] crypto: add user defined name initializing parameter

2017-01-12 Thread Fan Zhang

This patchset adds a user defined name initializing parameter to all
software cryptodevs.

v2:
Fixed a line adds whitespace error
Updated rte_cryptodev_version.map

Fan Zhang (2):
  cryptodev: add user defined name initializing parameter to software
PMD
  crypto: add user defined name initializing parameter parsing to
software PMDs

 drivers/crypto/aesni_gcm/aesni_gcm_pmd.c   | 58 +---
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 61 +-
 drivers/crypto/kasumi/rte_kasumi_pmd.c | 58 ++--
 drivers/crypto/null/null_crypto_pmd.c  | 55 +--
 drivers/crypto/openssl/rte_openssl_pmd.c   | 55 +--
 drivers/crypto/snow3g/rte_snow3g_pmd.c | 59 ++---
 drivers/crypto/zuc/rte_zuc_pmd.c   | 59 ++---
 lib/librte_cryptodev/rte_cryptodev.c   | 44 +++
 lib/librte_cryptodev/rte_cryptodev.h   |  7 ++-
 lib/librte_cryptodev/rte_cryptodev_pmd.h   |  7 +++
 lib/librte_cryptodev/rte_cryptodev_version.map |  7 +++
 11 files changed, 209 insertions(+), 261 deletions(-)

-- 
2.7.4

[dpdk-dev] [PATCH v3 0/2] crypto: add user defined name initializing parameter

2017-01-16 Thread Fan Zhang

This patchset adds a user defined name initializing parameter to all
software cryptodevs.

v3:
Added name parameter length check

v2:
Fixed a line adds whitespace error
Updated rte_cryptodev_version.map

Fan Zhang (2):
  cryptodev: add user defined name initializing parameter to software
PMD
  crypto: add user defined name initializing parameter parsing to
software PMDs

 drivers/crypto/aesni_gcm/aesni_gcm_pmd.c   | 58 +---
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 61 +-
 drivers/crypto/kasumi/rte_kasumi_pmd.c | 58 ++--
 drivers/crypto/null/null_crypto_pmd.c  | 55 +--
 drivers/crypto/openssl/rte_openssl_pmd.c   | 55 +--
 drivers/crypto/snow3g/rte_snow3g_pmd.c | 59 ++---
 drivers/crypto/zuc/rte_zuc_pmd.c   | 59 ++---
 lib/librte_cryptodev/rte_cryptodev.c   | 51 +
 lib/librte_cryptodev/rte_cryptodev.h   |  7 ++-
 lib/librte_cryptodev/rte_cryptodev_pmd.h   |  7 +++
 lib/librte_cryptodev/rte_cryptodev_version.map |  7 +++
 11 files changed, 216 insertions(+), 261 deletions(-)

-- 
2.7.4

[dpdk-dev] [PATCH v3 1/2] cryptodev: add user defined name initializing parameter to software PMD

2017-01-16 Thread Fan Zhang

This patch adds a user defined name initializing parameter to cryptodev
library.

Originally, for software cryptodev PMD, the vdev name parameter is
treated as the driver identifier, and will create an unique name for each
device automatically, which is not necessarily as same as the vdev
parameter.

This patch allows the user to either create a unique name for his software
cryptodev, or by default, let the system creates a unique one. This should
help the user managing the created cryptodevs easily.

Examples:
CLI command fragment 1: --vdev "crypto_aesni_gcm_pmd"
The above command will result in creating a AESNI-GCM PMD with name of
"crypto_aesni_gcm_X", where postfix X is the number assigned by the system,
starting from 0. This fragment can be placed in the same CLI command
multiple times, resulting the postfixs incremented by one for each new
device.

CLI command fragment 2: --vdev "crypto_aesni_gcm_pmd,name=gcm1"
The above command will result in creating a AESNI-GCM PMD with name of
"gcm1". This fragment can be placed in the same CLI command multiple
times, as long as each having a unique name value.

Signed-off-by: Fan Zhang 
---
 lib/librte_cryptodev/rte_cryptodev.c   | 51 ++
 lib/librte_cryptodev/rte_cryptodev.h   |  7 ++--
 lib/librte_cryptodev/rte_cryptodev_pmd.h   |  7 
 lib/librte_cryptodev/rte_cryptodev_version.map |  7 
 4 files changed, 68 insertions(+), 4 deletions(-)

diff --git a/lib/librte_cryptodev/rte_cryptodev.c 
b/lib/librte_cryptodev/rte_cryptodev.c
index 127e8d0..d6d7f3d 100644
--- a/lib/librte_cryptodev/rte_cryptodev.c
+++ b/lib/librte_cryptodev/rte_cryptodev.c
@@ -101,11 +101,13 @@ struct rte_cryptodev_callback {
uint32_t active;/**< Callback is executing */
 };
 
+#define RTE_CRYPTODEV_VDEV_NAME("name")
 #define RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG   ("max_nb_queue_pairs")
 #define RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG ("max_nb_sessions")
 #define RTE_CRYPTODEV_VDEV_SOCKET_ID   ("socket_id")
 
 static const char *cryptodev_vdev_valid_params[] = {
+   RTE_CRYPTODEV_VDEV_NAME,
RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG,
RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG,
RTE_CRYPTODEV_VDEV_SOCKET_ID
@@ -143,6 +145,25 @@ parse_integer_arg(const char *key __rte_unused,
return 0;
 }
 
+/** Parse name */
+static int
+parse_name_arg(const char *key __rte_unused,
+   const char *value, void *extra_args)
+{
+   struct rte_crypto_vdev_init_params *params = extra_args;
+
+   if (strlen(value) >= RTE_CRYPTODEV_NAME_MAX_LEN - 1) {
+   CDEV_LOG_ERR("Invalid name %s, should be less than "
+   "%u bytes", value,
+   RTE_CRYPTODEV_NAME_MAX_LEN - 1);
+   return -1;
+   }
+
+   strncpy(params->name, value, RTE_CRYPTODEV_NAME_MAX_LEN);
+
+   return 0;
+}
+
 int
 rte_cryptodev_parse_vdev_init_params(struct rte_crypto_vdev_init_params 
*params,
const char *input_args)
@@ -179,6 +200,12 @@ rte_cryptodev_parse_vdev_init_params(struct 
rte_crypto_vdev_init_params *params,
if (ret < 0)
goto free_kvlist;
 
+   ret = rte_kvargs_process(kvlist, RTE_CRYPTODEV_VDEV_NAME,
+   &parse_name_arg,
+   params);
+   if (ret < 0)
+   goto free_kvlist;
+
if (params->socket_id >= number_of_sockets()) {
CDEV_LOG_ERR("Invalid socket id specified to create "
"the virtual crypto device on");
@@ -1205,3 +1232,27 @@ rte_crypto_op_pool_create(const char *name, enum 
rte_crypto_op_type type,
 
return mp;
 }
+
+int
+rte_cryptodev_pmd_create_dev_name(char *name, const char *dev_name_prefix)
+{
+   struct rte_cryptodev *dev = NULL;
+   uint32_t i = 0;
+
+   if (name == NULL)
+   return -EINVAL;
+
+   for (i = 0; i < RTE_CRYPTO_MAX_DEVS; i++) {
+   int ret = snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN,
+   "%s_%u", dev_name_prefix, i);
+
+   if (ret < 0)
+   return ret;
+
+   dev = rte_cryptodev_pmd_get_named_dev(name);
+   if (!dev)
+   return 0;
+   }
+
+   return -1;
+}
diff --git a/lib/librte_cryptodev/rte_cryptodev.h 
b/lib/librte_cryptodev/rte_cryptodev.h
index 8f63e8f..b5399af 100644
--- a/lib/librte_cryptodev/rte_cryptodev.h
+++ b/lib/librte_cryptodev/rte_cryptodev.h
@@ -300,6 +300,8 @@ struct rte_cryptodev_stats {
/**< Total error count on operations dequeue

[dpdk-dev] [PATCH v3 2/2] crypto: add user defined name initializing parameter parsing to software PMDs

2017-01-16 Thread Fan Zhang

This patch adds user defined name parsing feature to software PMDs.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/aesni_gcm/aesni_gcm_pmd.c   | 58 ++--
 drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 61 ++
 drivers/crypto/kasumi/rte_kasumi_pmd.c | 58 +++-
 drivers/crypto/null/null_crypto_pmd.c  | 55 ++-
 drivers/crypto/openssl/rte_openssl_pmd.c   | 55 ++-
 drivers/crypto/snow3g/rte_snow3g_pmd.c | 59 +++--
 drivers/crypto/zuc/rte_zuc_pmd.c   | 59 +++--
 7 files changed, 148 insertions(+), 257 deletions(-)

diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c 
b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
index dba5e15..ddb2e0e 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
@@ -43,27 +43,6 @@
 
 #include "aesni_gcm_pmd_private.h"
 
-/**
- * Global static parameter used to create a unique name for each AES-NI multi
- * buffer crypto device.
- */
-static unsigned unique_name_id;
-
-static inline int
-create_unique_device_name(char *name, size_t size)
-{
-   int ret;
-
-   if (name == NULL)
-   return -EINVAL;
-
-   ret = snprintf(name, size, "%s_%u", 
RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD),
-   unique_name_id++);
-   if (ret < 0)
-   return ret;
-   return 0;
-}
-
 static int
 aesni_gcm_calculate_hash_sub_key(uint8_t *hsubkey, unsigned hsubkey_length,
uint8_t *aeskey, unsigned aeskey_length)
@@ -407,14 +386,23 @@ aesni_gcm_pmd_dequeue_burst(void *queue_pair,
 static int aesni_gcm_remove(const char *name);
 
 static int
-aesni_gcm_create(const char *name,
-   struct rte_crypto_vdev_init_params *init_params)
+aesni_gcm_create(struct rte_crypto_vdev_init_params *init_params)
 {
struct rte_cryptodev *dev;
-   char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct aesni_gcm_private *internals;
enum aesni_gcm_vector_mode vector_mode;
 
+   if (init_params->name[0] == '\0') {
+   int ret = rte_cryptodev_pmd_create_dev_name(
+   init_params->name,
+   RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));
+
+   if (ret < 0) {
+   GCM_LOG_ERR("failed to create unique name");
+   return ret;
+   }
+   }
+
/* Check CPU for support for AES instruction set */
if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {
GCM_LOG_ERR("AES instructions not supported by CPU");
@@ -433,15 +421,7 @@ aesni_gcm_create(const char *name,
return -EFAULT;
}
 
-   /* create a unique device name */
-   if (create_unique_device_name(crypto_dev_name,
-   RTE_CRYPTODEV_NAME_MAX_LEN) != 0) {
-   GCM_LOG_ERR("failed to create unique cryptodev name");
-   return -EINVAL;
-   }
-
-
-   dev = rte_cryptodev_pmd_virtual_dev_init(crypto_dev_name,
+   dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
sizeof(struct aesni_gcm_private), 
init_params->socket_id);
if (dev == NULL) {
GCM_LOG_ERR("failed to create cryptodev vdev");
@@ -484,9 +464,9 @@ aesni_gcm_create(const char *name,
return 0;
 
 init_error:
-   GCM_LOG_ERR("driver %s: create failed", name);
+   GCM_LOG_ERR("driver %s: create failed", init_params->name);
 
-   aesni_gcm_remove(crypto_dev_name);
+   aesni_gcm_remove(init_params->name);
return -EFAULT;
 }
 
@@ -496,19 +476,23 @@ aesni_gcm_probe(const char *name, const char *input_args)
struct rte_crypto_vdev_init_params init_params = {
RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_QUEUE_PAIRS,
RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS,
-   rte_socket_id()
+   rte_socket_id(),
+   {0}
};
 
rte_cryptodev_parse_vdev_init_params(&init_params, input_args);
 
RTE_LOG(INFO, PMD, "Initialising %s on NUMA node %d\n", name,
init_params.socket_id);
+   if (init_params.name[0] != '\0')
+   RTE_LOG(INFO, PMD, "  User defined name = %s\n",
+   init_params.name);
RTE_LOG(INFO, PMD, "  Max number of queue pairs = %d\n",
init_params.max_nb_queue_pairs);
RTE_LOG(INFO, PMD, "  Max number of sessions = %d\n",
init_params.max_nb_sessions);
 
-   return aesni_gcm_create(name, &init_params);
+   return aesni_gcm_create(&init_params);
 }
 
 static int
diff --git a/drivers/crypto/aesni_

[dpdk-dev] [PATCH v4] Scheduler: add driver for scheduler crypto pmd

2017-01-17 Thread Fan Zhang

This patch provides the initial implementation of the scheduler poll mode
driver using DPDK cryptodev framework.

Scheduler PMD is used to schedule and enqueue the crypto ops to the
hardware and/or software crypto devices attached to it (slaves). The
dequeue operation from the slave(s), and the possible dequeued crypto op
reordering, are then carried out by the scheduler.

As the initial version, the scheduler PMD currently supports only the
Round-robin mode, which distributes the enqueued burst of crypto ops
among its slaves in a round-robin manner. This mode may help to fill
the throughput gap between the physical core and the existing cryptodevs
to increase the overall performance. Moreover, the scheduler PMD is
provided the APIs for user to create his/her own scheduler.

Build instructions:
To build DPDK with CRYTPO_SCHEDULER_PMD the user is required to set
CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y in config/common_base

Notice:
- Scheduler PMD shares same EAL commandline options as other cryptodevs.
  However, apart from socket_id, the rest of cryptodev options are
  ignored. The scheduler PMD's max_nb_queue_pairs and max_nb_sessions
  options are set as the minimum values of the attached slaves'. For
  example, a scheduler cryptodev is attached 2 cryptodevs with
  max_nb_queue_pairs of 2 and 8, respectively. The scheduler cryptodev's
  max_nb_queue_pairs will be automatically updated as 2.

- In addition, an extra option "slave" is added. The user can attach one
  or more slave cryptodevs initially by passing their names with this
  option. Here is an example:

  ... --vdev "crypto_aesni_mb_pmd,name=aesni_mb_1" --vdev "crypto_aesni_
  mb_pmd,name=aesni_mb_2" --vdev "crypto_scheduler_pmd,slave=aesni_mb_1,
  slave=aesni_mb_2" ...

  Remember the software cryptodevs to be attached shall be declared before
  the scheduler PMD, otherwise the scheduler will fail to locate the
  slave(s) and report error.

- The scheduler cryptodev cannot be started unless the scheduling mode
  is set and at least one slave is attached. Also, to configure the
  scheduler in the run-time, like attach/detach slave(s), change
  scheduling mode, or enable/disable crypto op ordering, one should stop
  the scheduler first, otherwise an error will be returned.

Changes in v4:
Fixed a few bugs.
Added slave EAL commandline option support

Changes in v3:
Fixed config/common_base.

Changes in v2:
New approaches in API to suit future scheduling modes.

Signed-off-by: Fan Zhang 
Signed-off-by: Declan Doherty 
---
 config/common_base |   6 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/scheduler/Makefile  |  66 +++
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 461 +++
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h | 167 +++
 .../scheduler/rte_cryptodev_scheduler_operations.h |  71 +++
 .../scheduler/rte_pmd_crypto_scheduler_version.map |  12 +
 drivers/crypto/scheduler/scheduler_pmd.c   | 360 +++
 drivers/crypto/scheduler/scheduler_pmd_ops.c   | 489 +
 drivers/crypto/scheduler/scheduler_pmd_private.h   | 115 +
 drivers/crypto/scheduler/scheduler_roundrobin.c| 417 ++
 lib/librte_cryptodev/rte_cryptodev.h   |   4 +
 mk/rte.app.mk  |   3 +-
 13 files changed, 2171 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/scheduler/Makefile
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.c
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.h
 create mode 100644 
drivers/crypto/scheduler/rte_cryptodev_scheduler_operations.h
 create mode 100644 
drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd.c
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_ops.c
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_private.h
 create mode 100644 drivers/crypto/scheduler/scheduler_roundrobin.c

diff --git a/config/common_base b/config/common_base
index 8e9dcfa..3d33a2d 100644
--- a/config/common_base
+++ b/config/common_base
@@ -409,6 +409,12 @@ CONFIG_RTE_LIBRTE_PMD_KASUMI=n
 CONFIG_RTE_LIBRTE_PMD_KASUMI_DEBUG=n
 
 #
+# Compile PMD for Crypto Scheduler device
+#
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=n
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n
+
+#
 # Compile PMD for ZUC device
 #
 CONFIG_RTE_LIBRTE_PMD_ZUC=n
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 745c614..cdd3c94 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -38,6 +38,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += kasumi
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += zuc
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
 DIRS-$(CONFIG_RTE_L

[dpdk-dev] [PATCH v5] crypto/scheduler: add driver for scheduler crypto pmd

2017-01-17 Thread Fan Zhang

This patch provides the initial implementation of the scheduler poll mode
driver using DPDK cryptodev framework.

Scheduler PMD is used to schedule and enqueue the crypto ops to the
hardware and/or software crypto devices attached to it (slaves). The
dequeue operation from the slave(s), and the possible dequeued crypto op
reordering, are then carried out by the scheduler.

As the initial version, the scheduler PMD currently supports only the
Round-robin mode, which distributes the enqueued burst of crypto ops
among its slaves in a round-robin manner. This mode may help to fill
the throughput gap between the physical core and the existing cryptodevs
to increase the overall performance. Moreover, the scheduler PMD is
provided the APIs for user to create his/her own scheduler.

Build instructions:
To build DPDK with CRYTPO_SCHEDULER_PMD the user is required to set
CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y in config/common_base

Notice:
- Scheduler PMD shares same EAL commandline options as other cryptodevs.
  However, apart from socket_id, the rest of cryptodev options are
  ignored. The scheduler PMD's max_nb_queue_pairs and max_nb_sessions
  options are set as the minimum values of the attached slaves'. For
  example, a scheduler cryptodev is attached 2 cryptodevs with
  max_nb_queue_pairs of 2 and 8, respectively. The scheduler cryptodev's
  max_nb_queue_pairs will be automatically updated as 2.

- In addition, an extra option "slave" is added. The user can attach one
  or more slave cryptodevs initially by passing their names with this
  option. Here is an example:

  ... --vdev "crypto_aesni_mb_pmd,name=aesni_mb_1" --vdev "crypto_aesni_
  mb_pmd,name=aesni_mb_2" --vdev "crypto_scheduler_pmd,slave=aesni_mb_1,
  slave=aesni_mb_2" ...

  Remember the software cryptodevs to be attached shall be declared before
  the scheduler PMD, otherwise the scheduler will fail to locate the
  slave(s) and report error.

- The scheduler cryptodev cannot be started unless the scheduling mode
  is set and at least one slave is attached. Also, to configure the
  scheduler in the run-time, like attach/detach slave(s), change
  scheduling mode, or enable/disable crypto op ordering, one should stop
  the scheduler first, otherwise an error will be returned.

Changes in v5:
Fixed EOF whitespace warning.
Updated Copyright.

Changes in v4:
Fixed a few bugs.
Added slave EAL commandline option support.

Changes in v3:
Fixed config/common_base.

Changes in v2:
New approaches in API to suit future scheduling modes.

Signed-off-by: Fan Zhang 
Signed-off-by: Declan Doherty 
---
 config/common_base |   6 +
 drivers/crypto/Makefile|   1 +
 drivers/crypto/scheduler/Makefile  |  66 +++
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 460 +++
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h | 167 +++
 .../scheduler/rte_cryptodev_scheduler_operations.h |  71 +++
 .../scheduler/rte_pmd_crypto_scheduler_version.map |  12 +
 drivers/crypto/scheduler/scheduler_pmd.c   | 360 +++
 drivers/crypto/scheduler/scheduler_pmd_ops.c   | 489 +
 drivers/crypto/scheduler/scheduler_pmd_private.h   | 115 +
 drivers/crypto/scheduler/scheduler_roundrobin.c| 417 ++
 lib/librte_cryptodev/rte_cryptodev.h   |   4 +
 mk/rte.app.mk  |   3 +-
 13 files changed, 2170 insertions(+), 1 deletion(-)
 create mode 100644 drivers/crypto/scheduler/Makefile
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.c
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.h
 create mode 100644 
drivers/crypto/scheduler/rte_cryptodev_scheduler_operations.h
 create mode 100644 
drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd.c
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_ops.c
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_private.h
 create mode 100644 drivers/crypto/scheduler/scheduler_roundrobin.c

diff --git a/config/common_base b/config/common_base
index 8e9dcfa..3d33a2d 100644
--- a/config/common_base
+++ b/config/common_base
@@ -409,6 +409,12 @@ CONFIG_RTE_LIBRTE_PMD_KASUMI=n
 CONFIG_RTE_LIBRTE_PMD_KASUMI_DEBUG=n
 
 #
+# Compile PMD for Crypto Scheduler device
+#
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=n
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n
+
+#
 # Compile PMD for ZUC device
 #
 CONFIG_RTE_LIBRTE_PMD_ZUC=n
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 745c614..cdd3c94 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -38,6 +38,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += kasumi
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += zuc
+DIRS-$(CON

[dpdk-dev] [PATCH v6 00/11] crypto/scheduler: add driver for scheduler crypto pmd

2017-01-24 Thread Fan Zhang

This patch provides the initial implementation of the scheduler poll mode
driver using DPDK cryptodev framework.

Scheduler PMD is used to schedule and enqueue the crypto ops to the
hardware and/or software crypto devices attached to it (slaves). The
dequeue operation from the slave(s), and the possible dequeued crypto op
reordering, are then carried out by the scheduler.

As the initial version, the scheduler PMD currently supports only the
Round-robin mode, which distributes the enqueued burst of crypto ops
among its slaves in a round-robin manner. This mode may help to fill
the throughput gap between the physical core and the existing cryptodevs
to increase the overall performance. Moreover, the scheduler PMD is
provided the APIs for user to create his/her own scheduler.

Build instructions:
To build DPDK with CRYTPO_SCHEDULER_PMD the user is required to set
CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y in config/common_base

Notice:
- Scheduler PMD shares same EAL commandline options as other cryptodevs.
  However, apart from socket_id, the rest of cryptodev options are
  ignored. The scheduler PMD's max_nb_queue_pairs and max_nb_sessions
  options are set as the minimum values of the attached slaves'. For
  example, a scheduler cryptodev is attached 2 cryptodevs with
  max_nb_queue_pairs of 2 and 8, respectively. The scheduler cryptodev's
  max_nb_queue_pairs will be automatically updated as 2.

- In addition, an extra option "slave" is added. The user can attach one
  or more slave cryptodevs initially by passing their names with this
  option. Here is an example:

  ... --vdev "crypto_aesni_mb_pmd,name=aesni_mb_1" --vdev "crypto_aesni_
  mb_pmd,name=aesni_mb_2" --vdev "crypto_scheduler_pmd,slave=aesni_mb_1,
  slave=aesni_mb_2" ...

  Remember the software cryptodevs to be attached shall be declared before
  the scheduler PMD, otherwise the scheduler will fail to locate the
  slave(s) and report error.

- The scheduler cryptodev cannot be started unless the scheduling mode
  is set and at least one slave is attached. Also, to configure the
  scheduler in the run-time, like attach/detach slave(s), change
  scheduling mode, or enable/disable crypto op ordering, one should stop
  the scheduler first, otherwise an error will be returned.

- Enabling crypto ops reordering will cause overwriting the userdata field
  of each mbuf.

Fan Zhang (11):

Changes in v6:
Split into multiple patches.
Added documentation.
Added unit test.

Changes in v5:
Fixed EOF whitespace warning.
Updated Copyright.

Changes in v4:
Fixed a few bugs.
Added slave EAL commandline option support.

Changes in v3:
Fixed config/common_base.

Changes in v2:
New approaches in API to suit future scheduling modes.

  cryptodev: add scheduler PMD name and type
  crypto/scheduler: add APIs for scheduler
  crypto/scheduler: add internal structure declarations
  crypto/scheduler: add scheduler API implementations
  crypto/scheduler: add round-robin scheduling mode
  crypto/scheduler: register scheduler vdev driver
  crypto/scheduler: register operation function pointer table
  crypto/scheduler: add scheduler PMD to DPDK compile system
  crypto/scheduler: add scheduler PMD config options
  app/test: add unit test for cryptodev scheduler PMD
  crypto/scheduler: add documentation

 app/test/test_cryptodev.c  | 241 +-
 app/test/test_cryptodev_aes_test_vectors.h | 101 +++--
 app/test/test_cryptodev_blockcipher.c  |   6 +-
 app/test/test_cryptodev_blockcipher.h  |   3 +-
 app/test/test_cryptodev_hash_test_vectors.h|  38 +-
 config/common_base |   8 +-
 doc/guides/cryptodevs/img/scheduler-overview.svg   | 277 
 doc/guides/cryptodevs/index.rst|   3 +-
 doc/guides/cryptodevs/scheduler.rst| 128 ++
 drivers/crypto/Makefile|   3 +-
 drivers/crypto/scheduler/Makefile  |  66 +++
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 471 
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h | 165 +++
 .../scheduler/rte_cryptodev_scheduler_operations.h |  71 +++
 .../scheduler/rte_pmd_crypto_scheduler_version.map |  12 +
 drivers/crypto/scheduler/scheduler_pmd.c   | 361 +++
 drivers/crypto/scheduler/scheduler_pmd_ops.c   | 490 +
 drivers/crypto/scheduler/scheduler_pmd_private.h   | 115 +
 drivers/crypto/scheduler/scheduler_roundrobin.c| 435 ++
 lib/librte_cryptodev/rte_cryptodev.h   |   3 +
 mk/rte.app.mk  |   6 +-
 21 files changed, 2948 insertions(+), 55 deletions(-)
 create mode 100644 doc/guides/cryptodevs/img/scheduler-overview.svg
 create mode 100644 doc/guides/cryptodevs/scheduler.rst
 create mode 100644 drivers/crypto/scheduler/Makefile
 create mode 100644 drivers/crypto/

[dpdk-dev] [PATCH v6 01/11] cryptodev: add scheduler PMD name and type

2017-01-24 Thread Fan Zhang

This patch adds the cryptodev scheduler PMD name and type identifier to
librte_cryptodev.

Signed-off-by: Fan Zhang 
---
 lib/librte_cryptodev/rte_cryptodev.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/librte_cryptodev/rte_cryptodev.h 
b/lib/librte_cryptodev/rte_cryptodev.h
index f284668..618f302 100644
--- a/lib/librte_cryptodev/rte_cryptodev.h
+++ b/lib/librte_cryptodev/rte_cryptodev.h
@@ -68,6 +68,8 @@ extern "C" {
 /**< KASUMI PMD device name */
 #define CRYPTODEV_NAME_ARMV8_PMD   crypto_armv8
 /**< ARMv8 Crypto PMD device name */
+#define CRYPTODEV_NAME_SCHEDULER_PMD   crypto_scheduler
+/**< Scheduler Crypto PMD device name */
 
 /** Crypto device type */
 enum rte_cryptodev_type {
@@ -80,6 +82,7 @@ enum rte_cryptodev_type {
RTE_CRYPTODEV_ZUC_PMD,  /**< ZUC PMD */
RTE_CRYPTODEV_OPENSSL_PMD,/**<  OpenSSL PMD */
RTE_CRYPTODEV_ARMV8_PMD,/**< ARMv8 crypto PMD */
+   RTE_CRYPTODEV_SCHEDULER_PMD,/**< Crypto Scheduler PMD */
 };
 
 extern const char **rte_cyptodev_names;
-- 
2.7.4

[dpdk-dev] [PATCH v6 02/11] crypto/scheduler: add APIs for scheduler

2017-01-24 Thread Fan Zhang

Adds APIs and function prototypes for the scheduler PMD to perform extra
operations other than standard cryptodev APIs.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h | 162 +
 .../scheduler/rte_cryptodev_scheduler_operations.h |  71 +
 .../scheduler/rte_pmd_crypto_scheduler_version.map |  12 ++
 3 files changed, 245 insertions(+)
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.h
 create mode 100644 
drivers/crypto/scheduler/rte_cryptodev_scheduler_operations.h
 create mode 100644 
drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map

diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h 
b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
new file mode 100644
index 000..b18fc48
--- /dev/null
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
@@ -0,0 +1,162 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CRYPTO_SCHEDULER_H
+#define _RTE_CRYPTO_SCHEDULER_H
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Crypto scheduler PMD operation modes
+ */
+enum rte_cryptodev_scheduler_mode {
+   CDEV_SCHED_MODE_NOT_SET = 0,
+   CDEV_SCHED_MODE_USERDEFINED,
+
+   CDEV_SCHED_MODE_COUNT /* number of modes */
+};
+
+#define RTE_CRYPTODEV_SCHEDULER_NAME_MAX_LEN   (64)
+#define RTE_CRYPTODEV_SCHEDULER_DESC_MAX_LEN   (256)
+
+struct rte_cryptodev_scheduler;
+
+/**
+ * Load a user defined scheduler
+ *
+ * @param  scheduler_idThe target scheduler device ID
+ * scheduler   Pointer to the user defined scheduler
+ *
+ * @return
+ * 0 if loading successful, negative integer if otherwise.
+ */
+int
+rte_cryptodev_scheduler_load_user_scheduler(uint8_t scheduler_id,
+   struct rte_cryptodev_scheduler *scheduler);
+
+/**
+ * Attach a pre-configured crypto device to the scheduler
+ *
+ * @param  scheduler_idThe target scheduler device ID
+ * slave_idcrypto device ID to be attached
+ *
+ * @return
+ * 0 if attaching successful, negative int if otherwise.
+ */
+int
+rte_cryptodev_scheduler_slave_attach(uint8_t scheduler_id, uint8_t slave_id);
+
+/**
+ * Detach a attached crypto device to the scheduler
+ *
+ * @param  scheduler_idThe target scheduler device ID
+ * slave_idcrypto device ID to be detached
+ *
+ * @return
+ * 0 if detaching successful, negative int if otherwise.
+ */
+int
+rte_cryptodev_scheduler_slave_detach(uint8_t scheduler_id, uint8_t slave_id);
+
+/**
+ * Set the scheduling mode
+ *
+ * @param  scheduler_idThe target scheduler device ID
+ * modeThe scheduling mode
+ *
+ * @return
+ * 0 if attaching successful, negative integer if otherwise.
+ */
+int
+rte_crpytodev_scheduler_mode_set(uint8_t scheduler_id,
+   enum rte_cryptodev_scheduler_mode mode);
+
+/**
+ * Get the current scheduling mode
+ *
+ * @param  scheduler_idThe target scheduler device ID
+ * modePointer to write the scheduling mode
+ */
+enum rte_cryptodev_scheduler_mode
+rte_crpytodev_scheduler_mode_get(uint8_t scheduler_id);
+
+/**
+ * Set the crypto ops reordering feature on/off
+ *
+ * @param  dev_id  The target

[dpdk-dev] [PATCH v6 03/11] crypto/scheduler: add internal structure declarations

2017-01-24 Thread Fan Zhang

Adds a number of internal structures for the cryptodev scheduler PMD. The
structures include the scheduler context, slave, queue pair context,
and session.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/scheduler/scheduler_pmd_private.h | 115 +++
 1 file changed, 115 insertions(+)
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_private.h

diff --git a/drivers/crypto/scheduler/scheduler_pmd_private.h 
b/drivers/crypto/scheduler/scheduler_pmd_private.h
new file mode 100644
index 000..ac4690e
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_pmd_private.h
@@ -0,0 +1,115 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCHEDULER_PMD_PRIVATE_H
+#define _SCHEDULER_PMD_PRIVATE_H
+
+#include 
+#include 
+#include 
+
+/**< Maximum number of bonded devices per devices */
+#ifndef MAX_SLAVES_NUM
+#define MAX_SLAVES_NUM (8)
+#endif
+
+#define PER_SLAVE_BUFF_SIZE(256)
+
+#define CS_LOG_ERR(fmt, args...)   \
+   RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
+   RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),  \
+   __func__, __LINE__, ## args)
+
+#ifdef RTE_LIBRTE_CRYPTO_SCHEDULER_DEBUG
+#define CS_LOG_INFO(fmt, args...)  \
+   RTE_LOG(INFO, CRYPTODEV, "[%s] %s() line %u: " fmt "\n",\
+   RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),  \
+   __func__, __LINE__, ## args)
+
+#define CS_LOG_DBG(fmt, args...)   \
+   RTE_LOG(DEBUG, CRYPTODEV, "[%s] %s() line %u: " fmt "\n",   \
+   RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),  \
+   __func__, __LINE__, ## args)
+#else
+#define CS_LOG_INFO(fmt, args...)
+#define CS_LOG_DBG(fmt, args...)
+#endif
+
+struct scheduler_slave {
+   uint8_t dev_id;
+   uint16_t qp_id;
+   uint32_t nb_inflight_cops;
+
+   enum rte_cryptodev_type dev_type;
+};
+
+struct scheduler_ctx {
+   void *private_ctx;
+   /**< private scheduler context pointer */
+
+   struct rte_cryptodev_capabilities *capabilities;
+   uint32_t nb_capabilities;
+
+   uint32_t max_nb_queue_pairs;
+
+   struct scheduler_slave slaves[MAX_SLAVES_NUM];
+   uint32_t nb_slaves;
+
+   enum rte_cryptodev_scheduler_mode mode;
+
+   struct rte_cryptodev_scheduler_ops ops;
+
+   uint8_t reordering_enabled;
+
+   char name[RTE_CRYPTODEV_SCHEDULER_NAME_MAX_LEN];
+   char description[RTE_CRYPTODEV_SCHEDULER_DESC_MAX_LEN];
+} __rte_cache_aligned;
+
+struct scheduler_qp_ctx {
+   void *private_qp_ctx;
+
+   rte_cryptodev_scheduler_burst_enqueue_t schedule_enqueue;
+   rte_cryptodev_scheduler_burst_dequeue_t schedule_dequeue;
+
+   struct rte_reorder_buffer *reorder_buf;
+   uint32_t seqn;
+} __rte_cache_aligned;
+
+struct scheduler_session {
+   struct rte_cryptodev_sym_session *sessions[MAX_SLAVES_NUM];
+};
+
+/** device specific operations function pointer structure */
+extern struct rte_cryptodev_ops *rte_crypto_scheduler_pmd_ops;
+
+#endif /* _SCHEDULER_PMD_PRIVATE_H */
-- 
2.7.4

[dpdk-dev] [PATCH v6 05/11] crypto/scheduler: add round-robin scheduling mode

2017-01-24 Thread Fan Zhang

Implements round-robin scheduling mode and register into cryptodev
scheduler ops structure. This mode enqueues a burst of operation
to one of its slaves, and iterates the next burst to the other
slave. Same procedure is done on dequeueing operations.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c |   7 +
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h |   3 +
 drivers/crypto/scheduler/scheduler_roundrobin.c| 435 +
 3 files changed, 445 insertions(+)
 create mode 100644 drivers/crypto/scheduler/scheduler_roundrobin.c

diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.c 
b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
index ae6f032..e0ca029 100644
--- a/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
@@ -329,6 +329,13 @@ rte_crpytodev_scheduler_mode_set(uint8_t scheduler_id,
return 0;
 
switch (mode) {
+   case CDEV_SCHED_MODE_ROUNDROBIN:
+   if (rte_cryptodev_scheduler_load_user_scheduler(scheduler_id,
+   roundrobin_scheduler) < 0) {
+   CS_LOG_ERR("Failed to load scheduler");
+   return -1;
+   }
+   break;
default:
CS_LOG_ERR("Not yet supported");
return -ENOTSUP;
diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h 
b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
index b18fc48..7ef44e7 100644
--- a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
@@ -46,6 +46,7 @@ extern "C" {
 enum rte_cryptodev_scheduler_mode {
CDEV_SCHED_MODE_NOT_SET = 0,
CDEV_SCHED_MODE_USERDEFINED,
+   CDEV_SCHED_MODE_ROUNDROBIN,
 
CDEV_SCHED_MODE_COUNT /* number of modes */
 };
@@ -156,6 +157,8 @@ struct rte_cryptodev_scheduler {
struct rte_cryptodev_scheduler_ops *ops;
 };
 
+extern struct rte_cryptodev_scheduler *roundrobin_scheduler;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/drivers/crypto/scheduler/scheduler_roundrobin.c 
b/drivers/crypto/scheduler/scheduler_roundrobin.c
new file mode 100644
index 000..1f2e709
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_roundrobin.c
@@ -0,0 +1,435 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+#include "rte_cryptodev_scheduler_operations.h"
+#include "scheduler_pmd_private.h"
+
+struct rr_scheduler_qp_ctx {
+   struct scheduler_slave slaves[MAX_SLAVES_NUM];
+   uint32_t nb_slaves;
+
+   uint32_t last_enq_slave_idx;
+   uint32_t last_deq_slave_idx;
+};
+
+static uint16_t
+schedule_enqueue(void *qp_ctx, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+   struct rr_scheduler_qp_ctx *rr_qp_ctx =
+   ((struct scheduler_qp_ctx *)qp_ctx)->private_qp_ctx;
+   uint32_t slave_idx = rr_qp_ctx->last_enq_slave_idx;
+   struct scheduler_slave *slave = &rr_qp_ctx->slaves[slave_idx];
+   uint16_t i, processed_ops;
+   struct rte_cryptodev_sym_session *sessions[nb_ops];
+   struct scheduler_session *sess0, *sess1, *sess2, *sess3;
+
+   if (unlikely(nb_ops == 0))
+   return 0;
+
+

[dpdk-dev] [PATCH v6 04/11] crypto/scheduler: add scheduler API implementations

2017-01-24 Thread Fan Zhang

Adds the implementations of the APIs for scheduler cryptodev PMD.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 464 +
 1 file changed, 464 insertions(+)
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.c

diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.c 
b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
new file mode 100644
index 000..ae6f032
--- /dev/null
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
@@ -0,0 +1,464 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "scheduler_pmd_private.h"
+
+/** update the scheduler pmd's capability with attaching device's
+ *  capability.
+ *  For each device to be attached, the scheduler's capability should be
+ *  the common capability set of all slaves
+ **/
+static uint32_t
+sync_caps(struct rte_cryptodev_capabilities *caps,
+   uint32_t nb_caps,
+   const struct rte_cryptodev_capabilities *slave_caps)
+{
+   uint32_t sync_nb_caps = nb_caps, nb_slave_caps = 0;
+   uint32_t i;
+
+   while (slave_caps[nb_slave_caps].op != RTE_CRYPTO_OP_TYPE_UNDEFINED)
+   nb_slave_caps++;
+
+   if (nb_caps == 0) {
+   rte_memcpy(caps, slave_caps, sizeof(*caps) * nb_slave_caps);
+   return nb_slave_caps;
+   }
+
+   for (i = 0; i < sync_nb_caps; i++) {
+   struct rte_cryptodev_capabilities *cap = &caps[i];
+   uint32_t j;
+
+   for (j = 0; j < nb_slave_caps; j++) {
+   const struct rte_cryptodev_capabilities *s_cap =
+   &slave_caps[i];
+
+   if (s_cap->op != cap->op || s_cap->sym.xform_type !=
+   cap->sym.xform_type)
+   continue;
+
+   if (s_cap->sym.xform_type ==
+   RTE_CRYPTO_SYM_XFORM_AUTH) {
+   if (s_cap->sym.auth.algo !=
+   cap->sym.auth.algo)
+   continue;
+
+   cap->sym.auth.digest_size.min =
+   s_cap->sym.auth.digest_size.min <
+   cap->sym.auth.digest_size.min ?
+   s_cap->sym.auth.digest_size.min :
+   cap->sym.auth.digest_size.min;
+   cap->sym.auth.digest_size.max =
+   s_cap->sym.auth.digest_size.max <
+   cap->sym.auth.digest_size.max ?
+   s_cap->sym.auth.digest_size.max :
+   cap->sym.auth.digest_size.max;
+
+   }
+
+   if (s_cap->sym.xform_type ==
+   RTE_CRYPTO_SYM_XFORM_CIPHER)
+   if (s_cap->sym.cipher.algo !=
+   cap->sym.cipher.algo)
+

[dpdk-dev] [PATCH v6 06/11] crypto/scheduler: register scheduler vdev driver

2017-01-24 Thread Fan Zhang

Adds crypto scheduler's PMD's probe and remove function and the device's
enqueue and dequeue burst functions. A cryptodev scheduler PMD is
then registered in the end.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/scheduler/scheduler_pmd.c | 361 +++
 1 file changed, 361 insertions(+)
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd.c

diff --git a/drivers/crypto/scheduler/scheduler_pmd.c 
b/drivers/crypto/scheduler/scheduler_pmd.c
new file mode 100644
index 000..62418d0
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_pmd.c
@@ -0,0 +1,361 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "scheduler_pmd_private.h"
+
+struct scheduler_init_params {
+   struct rte_crypto_vdev_init_params def_p;
+   uint32_t nb_slaves;
+   uint8_t slaves[MAX_SLAVES_NUM];
+};
+
+#define RTE_CRYPTODEV_VDEV_NAME("name")
+#define RTE_CRYPTODEV_VDEV_SLAVE   ("slave")
+#define RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG   ("max_nb_queue_pairs")
+#define RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG ("max_nb_sessions")
+#define RTE_CRYPTODEV_VDEV_SOCKET_ID   ("socket_id")
+
+const char *scheduler_valid_params[] = {
+   RTE_CRYPTODEV_VDEV_NAME,
+   RTE_CRYPTODEV_VDEV_SLAVE,
+   RTE_CRYPTODEV_VDEV_MAX_NB_QP_ARG,
+   RTE_CRYPTODEV_VDEV_MAX_NB_SESS_ARG,
+   RTE_CRYPTODEV_VDEV_SOCKET_ID
+};
+
+static uint16_t
+scheduler_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
+   uint16_t nb_ops)
+{
+   struct scheduler_qp_ctx *qp_ctx = queue_pair;
+   uint16_t processed_ops;
+
+   processed_ops = (*qp_ctx->schedule_enqueue)(qp_ctx, ops,
+   nb_ops);
+
+   return processed_ops;
+}
+
+static uint16_t
+scheduler_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,
+   uint16_t nb_ops)
+{
+   struct scheduler_qp_ctx *qp_ctx = queue_pair;
+   uint16_t processed_ops;
+
+   processed_ops = (*qp_ctx->schedule_dequeue)(qp_ctx, ops,
+   nb_ops);
+
+   return processed_ops;
+}
+
+static int
+attach_init_slaves(uint8_t scheduler_id,
+   const uint8_t *slaves, const uint8_t nb_slaves)
+{
+   uint8_t i;
+
+   for (i = 0; i < nb_slaves; i++) {
+   struct rte_cryptodev *dev =
+   rte_cryptodev_pmd_get_dev(slaves[i]);
+   int status = rte_cryptodev_scheduler_slave_attach(
+   scheduler_id, slaves[i]);
+
+   if (status < 0 || !dev) {
+   CS_LOG_ERR("Failed to attach slave cryptodev "
+   "%u.\n", slaves[i]);
+   return status;
+   }
+
+   RTE_LOG(INFO, PMD, "  Attached slave cryptodev %s\n",
+   dev->data->name);
+   }
+
+   return 0;
+}
+
+static int
+cryptodev_scheduler_create(const char *name,
+   struct scheduler_init_params *init_params)
+{
+   char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
+   struct rte

[dpdk-dev] [PATCH v6 07/11] crypto/scheduler: register operation function pointer table

2017-01-24 Thread Fan Zhang

Implements all standard operations required for cryptodev,
and register them to cryptodev operation function pointer table.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/scheduler/scheduler_pmd_ops.c | 490 +++
 1 file changed, 490 insertions(+)
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_ops.c

diff --git a/drivers/crypto/scheduler/scheduler_pmd_ops.c 
b/drivers/crypto/scheduler/scheduler_pmd_ops.c
new file mode 100644
index 000..56624c7
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_pmd_ops.c
@@ -0,0 +1,490 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "scheduler_pmd_private.h"
+
+/** Configure device */
+static int
+scheduler_pmd_config(struct rte_cryptodev *dev)
+{
+   struct scheduler_ctx *sched_ctx = dev->data->dev_private;
+   uint32_t i;
+   int ret = 0;
+
+   for (i = 0; i < sched_ctx->nb_slaves; i++) {
+   uint8_t slave_dev_id = sched_ctx->slaves[i].dev_id;
+   struct rte_cryptodev *slave_dev =
+   rte_cryptodev_pmd_get_dev(slave_dev_id);
+
+   ret = (*slave_dev->dev_ops->dev_configure)(slave_dev);
+   if (ret < 0)
+   break;
+   }
+
+   return ret;
+}
+
+static int
+update_reorder_buff(struct rte_cryptodev *dev, uint16_t qp_id)
+{
+   struct scheduler_ctx *sched_ctx = dev->data->dev_private;
+   struct scheduler_qp_ctx *qp_ctx = dev->data->queue_pairs[qp_id];
+
+   if (sched_ctx->reordering_enabled) {
+   char reorder_buff_name[RTE_CRYPTODEV_NAME_MAX_LEN];
+   uint32_t buff_size = sched_ctx->nb_slaves * PER_SLAVE_BUFF_SIZE;
+
+   if (qp_ctx->reorder_buf) {
+   rte_reorder_free(qp_ctx->reorder_buf);
+   qp_ctx->reorder_buf = NULL;
+   }
+
+   if (!buff_size)
+   return 0;
+
+   if (snprintf(reorder_buff_name, RTE_CRYPTODEV_NAME_MAX_LEN,
+   "%s_rb_%u_%u", RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),
+   dev->data->dev_id, qp_id) < 0) {
+   CS_LOG_ERR("failed to create unique reorder buffer "
+   "name");
+   return -ENOMEM;
+   }
+
+   qp_ctx->reorder_buf = rte_reorder_create(reorder_buff_name,
+   rte_socket_id(), buff_size);
+   if (!qp_ctx->reorder_buf) {
+   CS_LOG_ERR("failed to create reorder buffer");
+   return -ENOMEM;
+   }
+   } else {
+   if (qp_ctx->reorder_buf) {
+   rte_reorder_free(qp_ctx->reorder_buf);
+   qp_ctx->reorder_buf = NULL;
+   }
+   }
+
+   return 0;
+}
+
+/** Start device */
+static int
+scheduler_pmd_start(struct rte_cryptodev *dev)
+{
+   struct scheduler_ctx *sched_ctx = dev->data->dev_private;
+   uint32_t i;
+   int ret;
+
+   if (dev->data->dev_started)
+   r

[dpdk-dev] [PATCH v6 08/11] crypto/scheduler: add scheduler PMD to DPDK compile system

2017-01-24 Thread Fan Zhang

Adds Makefile for scheduler cryptodev PMD, and updates existing
Makefiles. Different than other cryptodev PMDs, scheduler PMD
is required to be built as shared libraries.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/Makefile   |  3 +-
 drivers/crypto/scheduler/Makefile | 66 +++
 mk/rte.app.mk |  6 +++-
 3 files changed, 73 insertions(+), 2 deletions(-)
 create mode 100644 drivers/crypto/scheduler/Makefile

diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 77b02cf..a5a246b 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -1,6 +1,6 @@
 #   BSD LICENSE
 #
-#   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
+#   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
 #   All rights reserved.
 #
 #   Redistribution and use in source and binary forms, with or without
@@ -36,6 +36,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += kasumi
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += zuc
diff --git a/drivers/crypto/scheduler/Makefile 
b/drivers/crypto/scheduler/Makefile
new file mode 100644
index 000..0cce6f2
--- /dev/null
+++ b/drivers/crypto/scheduler/Makefile
@@ -0,0 +1,66 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2017 Intel Corporation. All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+# * Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in
+#   the documentation and/or other materials provided with the
+#   distribution.
+# * Neither the name of Intel Corporation nor the names of its
+#   contributors may be used to endorse or promote products derived
+#   from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_crypto_scheduler.a
+
+# build flags
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+
+# library version
+LIBABIVER := 1
+
+# versioning export map
+EXPORT_MAP := rte_pmd_crypto_scheduler_version.map
+
+#
+# Export include files
+#
+SYMLINK-y-include += rte_cryptodev_scheduler_operations.h
+SYMLINK-y-include += rte_cryptodev_scheduler.h
+
+# library source files
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler_pmd.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler_pmd_ops.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += rte_cryptodev_scheduler.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler_roundrobin.c
+
+# library dependencies
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_cryptodev
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_eal
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_kvargs
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_mbuf
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_mempool
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_reorder
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index a5daa84..0d0a970 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -70,7 +70,6 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PORT)   += -lrte_port
 
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PDUMP)  += -lrte_pdump
 _LDLIBS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR)+= -lrte_distributor
-_LDLIBS-$(CONFIG_RTE_LIBRTE_REORDER)+= -lrte_reorder
 _LDLIBS-$(CONFIG_RTE_LIBRTE_IP_FRAG)+= -lrte_ip_frag
 _LDLIBS-$(CONFIG_RTE_LIBRTE_METER)  += -lrte_meter
 _LDLIBS-$(CONFIG_RTE_LIBRTE_SCHED)  += -lrte_sched
@@ -99,10 +98,15 @@ _LDLIBS-$(CONFIG_RTE_L

[dpdk-dev] [PATCH v6 10/11] app/test: add unit test for cryptodev scheduler PMD

2017-01-24 Thread Fan Zhang

Same as other cryptodev PMDs, it is necessary to carry out the unit
test for scheduler PMD. Currently the test is designed to attach 2
AESNI-MB cryptodev PMDs as slaves, sets the scheduling mode as round-
robin, and runs almost all AESNI-MB test items (except for sessionless
tests). In the end, the slaves are detached.

Signed-off-by: Fan Zhang 
---
 app/test/test_cryptodev.c   | 241 +++-
 app/test/test_cryptodev_aes_test_vectors.h  | 101 
 app/test/test_cryptodev_blockcipher.c   |   6 +-
 app/test/test_cryptodev_blockcipher.h   |   3 +-
 app/test/test_cryptodev_hash_test_vectors.h |  38 +++--
 5 files changed, 338 insertions(+), 51 deletions(-)

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 0f0cf4d..bf44928 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  *
- *   Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ *   Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
  *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
@@ -40,6 +40,11 @@
 #include 
 #include 
 
+#ifdef RTE_LIBRTE_PMD_CRYPTO_SCHEDULER
+#include 
+#include 
+#endif
+
 #include "test.h"
 #include "test_cryptodev.h"
 
@@ -159,7 +164,7 @@ testsuite_setup(void)
 {
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct rte_cryptodev_info info;
-   unsigned i, nb_devs, dev_id;
+   uint32_t i = 0, nb_devs, dev_id;
int ret;
uint16_t qp_id;
 
@@ -370,6 +375,29 @@ testsuite_setup(void)
}
}
 
+#ifdef RTE_LIBRTE_PMD_CRYPTO_SCHEDULER
+   if (gbl_cryptodev_type == RTE_CRYPTODEV_SCHEDULER_PMD) {
+
+#ifndef RTE_LIBRTE_PMD_AESNI_MB
+   RTE_LOG(ERR, USER1, "CONFIG_RTE_LIBRTE_PMD_AESNI_MB must be"
+   " enabled in config file to run this testsuite.\n");
+   return TEST_FAILED;
+#endif
+   nb_devs = rte_cryptodev_count_devtype(
+   RTE_CRYPTODEV_SCHEDULER_PMD);
+   if (nb_devs < 1) {
+   ret = rte_eal_vdev_init(
+   RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),
+   NULL);
+
+   TEST_ASSERT(ret == 0,
+   "Failed to create instance %u of"
+   " pmd : %s",
+   i, RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD));
+   }
+   }
+#endif /* RTE_LIBRTE_PMD_CRYPTO_SCHEDULER */
+
 #ifndef RTE_LIBRTE_PMD_QAT
if (gbl_cryptodev_type == RTE_CRYPTODEV_QAT_SYM_PMD) {
RTE_LOG(ERR, USER1, "CONFIG_RTE_LIBRTE_PMD_QAT must be enabled "
@@ -1535,6 +1563,58 @@ test_AES_chain_mb_all(void)
return TEST_SUCCESS;
 }
 
+#ifdef RTE_LIBRTE_PMD_CRYPTO_SCHEDULER
+
+static int
+test_AES_cipheronly_scheduler_all(void)
+{
+   struct crypto_testsuite_params *ts_params = &testsuite_params;
+   int status;
+
+   status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+   ts_params->op_mpool, ts_params->valid_devs[0],
+   RTE_CRYPTODEV_SCHEDULER_PMD,
+   BLKCIPHER_AES_CIPHERONLY_TYPE);
+
+   TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+   return TEST_SUCCESS;
+}
+
+static int
+test_AES_chain_scheduler_all(void)
+{
+   struct crypto_testsuite_params *ts_params = &testsuite_params;
+   int status;
+
+   status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+   ts_params->op_mpool, ts_params->valid_devs[0],
+   RTE_CRYPTODEV_SCHEDULER_PMD,
+   BLKCIPHER_AES_CHAIN_TYPE);
+
+   TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+   return TEST_SUCCESS;
+}
+
+static int
+test_authonly_scheduler_all(void)
+{
+   struct crypto_testsuite_params *ts_params = &testsuite_params;
+   int status;
+
+   status = test_blockcipher_all_tests(ts_params->mbuf_pool,
+   ts_params->op_mpool, ts_params->valid_devs[0],
+   RTE_CRYPTODEV_SCHEDULER_PMD,
+   BLKCIPHER_AUTHONLY_TYPE);
+
+   TEST_ASSERT_EQUAL(status, 0, "Test failed");
+
+   return TEST_SUCCESS;
+}
+
+#endif /* RTE_LIBRTE_PMD_CRYPTO_SCHEDULER */
+
 static int
 test_AES_chain_openssl_all(void)
 {
@@ -7292,6 +7372,150 @@ 
auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt(void)
&aes128cbc_hmac_sha1_test_vector);
 }
 
+#ifdef RTE_LIBRTE_PMD_CRYPTO_SCHEDULER
+
+/* global AESNI slave IDs for the scheduler test */
+uint8_t aesni_ids[2];
+
+static int
+test_scheduler_attach_slave_op(void)
+{
+   struct crypto_testsuite_params *ts_params = &testsuite_params;
+   u

[dpdk-dev] [PATCH v6 09/11] crypto/scheduler: add scheduler PMD config options

2017-01-24 Thread Fan Zhang

Adds scheduler PMD enable and debug flags to config/common_base.

Signed-off-by: Fan Zhang 
---
 config/common_base | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/config/common_base b/config/common_base
index b9fb8e2..cd4a0f3 100644
--- a/config/common_base
+++ b/config/common_base
@@ -1,6 +1,6 @@
 #   BSD LICENSE
 #
-#   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
+#   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
 #   All rights reserved.
 #
 #   Redistribution and use in source and binary forms, with or without
@@ -434,6 +434,12 @@ CONFIG_RTE_LIBRTE_PMD_ZUC=n
 CONFIG_RTE_LIBRTE_PMD_ZUC_DEBUG=n
 
 #
+# Compile PMD for Crypto Scheduler device
+#
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=n
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n
+
+#
 # Compile PMD for NULL Crypto device
 #
 CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y
-- 
2.7.4

[dpdk-dev] [PATCH v6 11/11] crypto/scheduler: add documentation

2017-01-24 Thread Fan Zhang

Adds the description of the cryptodev scheduler PMD overview,
limitations, build, instructions, modes, etc.

Signed-off-by: Fan Zhang 
---
 doc/guides/cryptodevs/img/scheduler-overview.svg | 277 +++
 doc/guides/cryptodevs/index.rst  |   3 +-
 doc/guides/cryptodevs/scheduler.rst  | 128 +++
 3 files changed, 407 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/cryptodevs/img/scheduler-overview.svg
 create mode 100644 doc/guides/cryptodevs/scheduler.rst

diff --git a/doc/guides/cryptodevs/img/scheduler-overview.svg 
b/doc/guides/cryptodevs/img/scheduler-overview.svg
new file mode 100644
index 000..82bb775
--- /dev/null
+++ b/doc/guides/cryptodevs/img/scheduler-overview.svg
@@ -0,0 +1,277 @@
+
+http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd";>
+
+http://www.w3.org/2000/svg"; 
xmlns:xlink="http://www.w3.org/1999/xlink"; 
xmlns:ev="http://www.w3.org/2001/xml-events";
+   
xmlns:v="http://schemas.microsoft.com/visio/2003/SVGExtensions/"; 
width="6.81229in" height="3.40992in"
+   viewBox="0 0 490.485 245.514" xml:space="preserve" 
color-interpolation-filters="sRGB" class="st10">
+   
+
+   
+   <![CDATA[
+   .st1 {visibility:visible}
+   .st2 
{fill:#fec000;fill-opacity:0.25;filter:url(#filter_2);stroke:#fec000;stroke-opacity:0.25}
+   .st3 {fill:#cc3399;stroke:#ff8c00;stroke-width:3}
+   .st4 {fill:#ff;font-family:Calibri;font-size:1.3em}
+   .st5 {fill:#ff9900;stroke:#ff8c00;stroke-width:3}
+   .st6 
{fill:#ff;font-family:Calibri;font-size:1.3em;font-weight:bold}
+   .st7 
{fill:#ffc000;stroke:#ff;stroke-linecap:round;stroke-linejoin:round;stroke-width:0.5}
+   .st8 
{marker-end:url(#mrkr4-40);stroke:#ff;stroke-linecap:round;stroke-linejoin:round;stroke-width:1.5}
+   .st9 
{fill:#ff;fill-opacity:1;stroke:#ff;stroke-opacity:1;stroke-width:0.37313432835821}
+   .st10 
{fill:none;fill-rule:evenodd;font-size:12px;overflow:visible;stroke-linecap:square;stroke-miterlimit:3}
+   ]]>
+   
+
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   Page-1
+   
+   
+   
+   Rounded Rectangle.55
+   User Application
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   User 
Application  
+   
+   Rounded Rectangle.135
+   Cryptodev
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   
+   Cryptodev

[dpdk-dev] [PATCH v7 00/11] crypto/scheduler: add driver for scheduler crypto pmd

2017-01-24 Thread Fan Zhang

This patch provides the initial implementation of the scheduler poll mode
driver using DPDK cryptodev framework.

Scheduler PMD is used to schedule and enqueue the crypto ops to the
hardware and/or software crypto devices attached to it (slaves). The
dequeue operation from the slave(s), and the possible dequeued crypto op
reordering, are then carried out by the scheduler.

As the initial version, the scheduler PMD currently supports only the
Round-robin mode, which distributes the enqueued burst of crypto ops
among its slaves in a round-robin manner. This mode may help to fill
the throughput gap between the physical core and the existing cryptodevs
to increase the overall performance. Moreover, the scheduler PMD is
provided the APIs for user to create his/her own scheduler.

Build instructions:
To build DPDK with CRYTPO_SCHEDULER_PMD the user is required to set
CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y in config/common_base

Notice:
- Scheduler PMD shares same EAL commandline options as other cryptodevs.
  However, apart from socket_id, the rest of cryptodev options are
  ignored. The scheduler PMD's max_nb_queue_pairs and max_nb_sessions
  options are set as the minimum values of the attached slaves'. For
  example, a scheduler cryptodev is attached 2 cryptodevs with
  max_nb_queue_pairs of 2 and 8, respectively. The scheduler cryptodev's
  max_nb_queue_pairs will be automatically updated as 2.

- In addition, an extra option "slave" is added. The user can attach one
  or more slave cryptodevs initially by passing their names with this
  option. Here is an example:

  ... --vdev "crypto_aesni_mb_pmd,name=aesni_mb_1" --vdev "crypto_aesni_
  mb_pmd,name=aesni_mb_2" --vdev "crypto_scheduler_pmd,slave=aesni_mb_1,
  slave=aesni_mb_2" ...

  Remember the software cryptodevs to be attached shall be declared before
  the scheduler PMD, otherwise the scheduler will fail to locate the
  slave(s) and report error.

- The scheduler cryptodev cannot be started unless the scheduling mode
  is set and at least one slave is attached. Also, to configure the
  scheduler in the run-time, like attach/detach slave(s), change
  scheduling mode, or enable/disable crypto op ordering, one should stop
  the scheduler first, otherwise an error will be returned.

- Enabling crypto ops reordering will cause overwriting the userdata field
  of each mbuf.

Fan Zhang (11):

Changes in v7:
Added missed sign-off

Changes in v6:
Split into multiple patches.
Added documentation.
Added unit test.

Changes in v5:
Fixed EOF whitespace warning.
Updated Copyright.

Changes in v4:
Fixed a few bugs.
Added slave EAL commandline option support.

Changes in v3:
Fixed config/common_base.

Changes in v2:
New approaches in API to suit future scheduling modes.

Fan Zhang (11):
  cryptodev: add scheduler PMD name and type
  crypto/scheduler: add APIs for scheduler
  crypto/scheduler: add internal structure declarations
  crypto/scheduler: add scheduler API implementations
  crypto/scheduler: add round-robin scheduling mode
  crypto/scheduler: register scheduler vdev driver
  crypto/scheduler: register operation function pointer table
  crypto/scheduler: add scheduler PMD to DPDK compile system
  crypto/scheduler: add scheduler PMD config options
  app/test: add unit test for cryptodev scheduler PMD
  crypto/scheduler: add documentation

 app/test/test_cryptodev.c  | 241 +-
 app/test/test_cryptodev_aes_test_vectors.h | 101 +++--
 app/test/test_cryptodev_blockcipher.c  |   6 +-
 app/test/test_cryptodev_blockcipher.h  |   3 +-
 app/test/test_cryptodev_hash_test_vectors.h|  38 +-
 config/common_base |   8 +-
 doc/guides/cryptodevs/img/scheduler-overview.svg   | 277 
 doc/guides/cryptodevs/index.rst|   3 +-
 doc/guides/cryptodevs/scheduler.rst| 128 ++
 drivers/crypto/Makefile|   3 +-
 drivers/crypto/scheduler/Makefile  |  66 +++
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 471 
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h | 165 +++
 .../scheduler/rte_cryptodev_scheduler_operations.h |  71 +++
 .../scheduler/rte_pmd_crypto_scheduler_version.map |  12 +
 drivers/crypto/scheduler/scheduler_pmd.c   | 361 +++
 drivers/crypto/scheduler/scheduler_pmd_ops.c   | 490 +
 drivers/crypto/scheduler/scheduler_pmd_private.h   | 115 +
 drivers/crypto/scheduler/scheduler_roundrobin.c| 435 ++
 lib/librte_cryptodev/rte_cryptodev.h   |   3 +
 mk/rte.app.mk  |   6 +-
 21 files changed, 2948 insertions(+), 55 deletions(-)
 create mode 100644 doc/guides/cryptodevs/img/scheduler-overview.svg
 create mode 100644 doc/guides/cryptodevs/scheduler.rst
 create mode 100644 drivers/crypt

[dpdk-dev] [PATCH v7 01/11] cryptodev: add scheduler PMD name and type

2017-01-24 Thread Fan Zhang

This patch adds the cryptodev scheduler PMD name and type identifier to
librte_cryptodev.

Signed-off-by: Fan Zhang 
---
 lib/librte_cryptodev/rte_cryptodev.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/librte_cryptodev/rte_cryptodev.h 
b/lib/librte_cryptodev/rte_cryptodev.h
index f284668..618f302 100644
--- a/lib/librte_cryptodev/rte_cryptodev.h
+++ b/lib/librte_cryptodev/rte_cryptodev.h
@@ -68,6 +68,8 @@ extern "C" {
 /**< KASUMI PMD device name */
 #define CRYPTODEV_NAME_ARMV8_PMD   crypto_armv8
 /**< ARMv8 Crypto PMD device name */
+#define CRYPTODEV_NAME_SCHEDULER_PMD   crypto_scheduler
+/**< Scheduler Crypto PMD device name */
 
 /** Crypto device type */
 enum rte_cryptodev_type {
@@ -80,6 +82,7 @@ enum rte_cryptodev_type {
RTE_CRYPTODEV_ZUC_PMD,  /**< ZUC PMD */
RTE_CRYPTODEV_OPENSSL_PMD,/**<  OpenSSL PMD */
RTE_CRYPTODEV_ARMV8_PMD,/**< ARMv8 crypto PMD */
+   RTE_CRYPTODEV_SCHEDULER_PMD,/**< Crypto Scheduler PMD */
 };
 
 extern const char **rte_cyptodev_names;
-- 
2.7.4

[dpdk-dev] [PATCH v7 03/11] crypto/scheduler: add internal structure declarations

2017-01-24 Thread Fan Zhang

Adds a number of internal structures for the cryptodev scheduler PMD. The
structures include the scheduler context, slave, queue pair context,
and session.

Signed-off-by: Fan Zhang 
Signed-off-by: Declan Doherty 
---
 drivers/crypto/scheduler/scheduler_pmd_private.h | 115 +++
 1 file changed, 115 insertions(+)
 create mode 100644 drivers/crypto/scheduler/scheduler_pmd_private.h

diff --git a/drivers/crypto/scheduler/scheduler_pmd_private.h 
b/drivers/crypto/scheduler/scheduler_pmd_private.h
new file mode 100644
index 000..ac4690e
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_pmd_private.h
@@ -0,0 +1,115 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCHEDULER_PMD_PRIVATE_H
+#define _SCHEDULER_PMD_PRIVATE_H
+
+#include 
+#include 
+#include 
+
+/**< Maximum number of bonded devices per devices */
+#ifndef MAX_SLAVES_NUM
+#define MAX_SLAVES_NUM (8)
+#endif
+
+#define PER_SLAVE_BUFF_SIZE(256)
+
+#define CS_LOG_ERR(fmt, args...)   \
+   RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
+   RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),  \
+   __func__, __LINE__, ## args)
+
+#ifdef RTE_LIBRTE_CRYPTO_SCHEDULER_DEBUG
+#define CS_LOG_INFO(fmt, args...)  \
+   RTE_LOG(INFO, CRYPTODEV, "[%s] %s() line %u: " fmt "\n",\
+   RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),  \
+   __func__, __LINE__, ## args)
+
+#define CS_LOG_DBG(fmt, args...)   \
+   RTE_LOG(DEBUG, CRYPTODEV, "[%s] %s() line %u: " fmt "\n",   \
+   RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),  \
+   __func__, __LINE__, ## args)
+#else
+#define CS_LOG_INFO(fmt, args...)
+#define CS_LOG_DBG(fmt, args...)
+#endif
+
+struct scheduler_slave {
+   uint8_t dev_id;
+   uint16_t qp_id;
+   uint32_t nb_inflight_cops;
+
+   enum rte_cryptodev_type dev_type;
+};
+
+struct scheduler_ctx {
+   void *private_ctx;
+   /**< private scheduler context pointer */
+
+   struct rte_cryptodev_capabilities *capabilities;
+   uint32_t nb_capabilities;
+
+   uint32_t max_nb_queue_pairs;
+
+   struct scheduler_slave slaves[MAX_SLAVES_NUM];
+   uint32_t nb_slaves;
+
+   enum rte_cryptodev_scheduler_mode mode;
+
+   struct rte_cryptodev_scheduler_ops ops;
+
+   uint8_t reordering_enabled;
+
+   char name[RTE_CRYPTODEV_SCHEDULER_NAME_MAX_LEN];
+   char description[RTE_CRYPTODEV_SCHEDULER_DESC_MAX_LEN];
+} __rte_cache_aligned;
+
+struct scheduler_qp_ctx {
+   void *private_qp_ctx;
+
+   rte_cryptodev_scheduler_burst_enqueue_t schedule_enqueue;
+   rte_cryptodev_scheduler_burst_dequeue_t schedule_dequeue;
+
+   struct rte_reorder_buffer *reorder_buf;
+   uint32_t seqn;
+} __rte_cache_aligned;
+
+struct scheduler_session {
+   struct rte_cryptodev_sym_session *sessions[MAX_SLAVES_NUM];
+};
+
+/** device specific operations function pointer structure */
+extern struct rte_cryptodev_ops *rte_crypto_scheduler_pmd_ops;
+
+#endif /* _SCHEDULER_PMD_PRIVATE_H */
-- 
2.7.4

[dpdk-dev] [PATCH v7 04/11] crypto/scheduler: add scheduler API implementations

2017-01-24 Thread Fan Zhang

Adds the implementations of the APIs for scheduler cryptodev PMD.

Signed-off-by: Fan Zhang 
---
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 464 +
 1 file changed, 464 insertions(+)
 create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.c

diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.c 
b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
new file mode 100644
index 000..14f0983
--- /dev/null
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
@@ -0,0 +1,464 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "scheduler_pmd_private.h"
+
+/** update the scheduler pmd's capability with attaching device's
+ *  capability.
+ *  For each device to be attached, the scheduler's capability should be
+ *  the common capability set of all slaves
+ **/
+static uint32_t
+sync_caps(struct rte_cryptodev_capabilities *caps,
+   uint32_t nb_caps,
+   const struct rte_cryptodev_capabilities *slave_caps)
+{
+   uint32_t sync_nb_caps = nb_caps, nb_slave_caps = 0;
+   uint32_t i;
+
+   while (slave_caps[nb_slave_caps].op != RTE_CRYPTO_OP_TYPE_UNDEFINED)
+   nb_slave_caps++;
+
+   if (nb_caps == 0) {
+   rte_memcpy(caps, slave_caps, sizeof(*caps) * nb_slave_caps);
+   return nb_slave_caps;
+   }
+
+   for (i = 0; i < sync_nb_caps; i++) {
+   struct rte_cryptodev_capabilities *cap = &caps[i];
+   uint32_t j;
+
+   for (j = 0; j < nb_slave_caps; j++) {
+   const struct rte_cryptodev_capabilities *s_cap =
+   &slave_caps[i];
+
+   if (s_cap->op != cap->op || s_cap->sym.xform_type !=
+   cap->sym.xform_type)
+   continue;
+
+   if (s_cap->sym.xform_type ==
+   RTE_CRYPTO_SYM_XFORM_AUTH) {
+   if (s_cap->sym.auth.algo !=
+   cap->sym.auth.algo)
+   continue;
+
+   cap->sym.auth.digest_size.min =
+   s_cap->sym.auth.digest_size.min <
+   cap->sym.auth.digest_size.min ?
+   s_cap->sym.auth.digest_size.min :
+   cap->sym.auth.digest_size.min;
+   cap->sym.auth.digest_size.max =
+   s_cap->sym.auth.digest_size.max <
+   cap->sym.auth.digest_size.max ?
+   s_cap->sym.auth.digest_size.max :
+   cap->sym.auth.digest_size.max;
+
+   }
+
+   if (s_cap->sym.xform_type ==
+   RTE_CRYPTO_SYM_XFORM_CIPHER)
+   if (s_cap->sym.cipher.algo !=
+   cap->sym.cipher.algo)
+

[dpdk-dev] [PATCH v7 05/11] crypto/scheduler: add round-robin scheduling mode

2017-01-24 Thread Fan Zhang

Implements round-robin scheduling mode and register into cryptodev
scheduler ops structure. This mode enqueues a burst of operation
to one of its slaves, and iterates the next burst to the other
slave. Same procedure is done on dequeueing operations.

Signed-off-by: Fan Zhang 
Signed-off-by: Declan Doherty 
---
 drivers/crypto/scheduler/rte_cryptodev_scheduler.c |   7 +
 drivers/crypto/scheduler/rte_cryptodev_scheduler.h |   3 +
 drivers/crypto/scheduler/scheduler_roundrobin.c| 435 +
 3 files changed, 445 insertions(+)
 create mode 100644 drivers/crypto/scheduler/scheduler_roundrobin.c

diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.c 
b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
index 14f0983..11e8143 100644
--- a/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
@@ -329,6 +329,13 @@ rte_crpytodev_scheduler_mode_set(uint8_t scheduler_id,
return 0;
 
switch (mode) {
+   case CDEV_SCHED_MODE_ROUNDROBIN:
+   if (rte_cryptodev_scheduler_load_user_scheduler(scheduler_id,
+   roundrobin_scheduler) < 0) {
+   CS_LOG_ERR("Failed to load scheduler");
+   return -1;
+   }
+   break;
default:
CS_LOG_ERR("Not yet supported");
return -ENOTSUP;
diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h 
b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
index b18fc48..7ef44e7 100644
--- a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
@@ -46,6 +46,7 @@ extern "C" {
 enum rte_cryptodev_scheduler_mode {
CDEV_SCHED_MODE_NOT_SET = 0,
CDEV_SCHED_MODE_USERDEFINED,
+   CDEV_SCHED_MODE_ROUNDROBIN,
 
CDEV_SCHED_MODE_COUNT /* number of modes */
 };
@@ -156,6 +157,8 @@ struct rte_cryptodev_scheduler {
struct rte_cryptodev_scheduler_ops *ops;
 };
 
+extern struct rte_cryptodev_scheduler *roundrobin_scheduler;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/drivers/crypto/scheduler/scheduler_roundrobin.c 
b/drivers/crypto/scheduler/scheduler_roundrobin.c
new file mode 100644
index 000..1f2e709
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_roundrobin.c
@@ -0,0 +1,435 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+#include "rte_cryptodev_scheduler_operations.h"
+#include "scheduler_pmd_private.h"
+
+struct rr_scheduler_qp_ctx {
+   struct scheduler_slave slaves[MAX_SLAVES_NUM];
+   uint32_t nb_slaves;
+
+   uint32_t last_enq_slave_idx;
+   uint32_t last_deq_slave_idx;
+};
+
+static uint16_t
+schedule_enqueue(void *qp_ctx, struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+   struct rr_scheduler_qp_ctx *rr_qp_ctx =
+   ((struct scheduler_qp_ctx *)qp_ctx)->private_qp_ctx;
+   uint32_t slave_idx = rr_qp_ctx->last_enq_slave_idx;
+   struct scheduler_slave *slave = &rr_qp_ctx->slaves[slave_idx];
+   uint16_t i, processed_ops;
+   struct rte_cryptodev_sym_session *sessions[nb_ops];
+   struct scheduler_session *sess0, *sess1, *sess2, *sess3;
+
+   if (unlikely(nb_ops =

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