Paul Emmerich wrote:
> Stephen Hemminger wrote:
>
>> Your excess polling consumes PCI bandwidth which is a fixed resource.
>
> I doubt that this is the problem for three reasons:
>
4th: polling should not cause a PCIe access as all the required information is
written
to memory by the NIC
Stephen Hemminger wrote:
> Your excess polling consumes PCI bandwidth which is a fixed resource.
I doubt that this is the problem for three reasons:
* The poll rate would regulate itself if the PCIe bus was the bottleneck
* This problem only occurs with 82599 chips, not with X540 chips
Hi Stephen,
Thanks, that was an informative talk. In this case, are you referring to your
comments about the thermal budget?
That?s definitely interesting, but there must be more to it than that. Again,
if I loop over all 6 ports (i.e., continue to keep the CPU busy), it works
around the
On Thu, 9 Apr 2015 15:26:23 -0300
Aaron Campbell wrote:
> Hi Stephen,
>
> Thanks, that was an informative talk. In this case, are you referring to
> your comments about the thermal budget?
>
> That?s definitely interesting, but there must be more to it than that.
> Again, if I loop over
> -Original Message-
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of Aaron Campbell
> Sent: Wednesday, April 08, 2015 5:36 PM
> To: dev at dpdk.org
> Subject: [dpdk-dev] Polling too often at lower packet rates?
>
> Hi,
>
> I have a machine with 6
We use adaptive polling loop similar to l3fwd-power example.
See:
http://video.fosdem.org/2015/devroom-network_management_and_sdn/
On Wed, Apr 8, 2015 at 9:35 AM, Aaron Campbell wrote:
> Hi,
>
> I have a machine with 6 DPDK ports (4 igb, 2 ixgbe), with 1.23Mpps traffic
> offered to only one
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