VariableReadLib is a phase agnostic libary for reading UEFI
Variables. This library provides the
MinGetVariable() and MinGetNextVariableName() APIs which
are usable PEI, DXE, and SMM.
Cc: Chasel Chiu
Cc: Liming Gao
Cc: Eric Dong
Cc: Michael Kubacki
Cc: Isaac Oram
Signed-off-by: Nate DeSimone
This patch series introduces libaries that enable large data sets
to be stored using the UEFI Variable Services. At present, most
UEFI Variable Services implementations have a maximum variable
size of <=64KB. The exact value varies depending on platform.
These libaries enable a data set to use as
VariableWriteLib is a phase agnostic library for writing
to UEFI Variables. This library provides the MinSetVariable(),
MinQueryVariableInfo(), MinIsVariableRequestToLockSupported(),
and MinVariableRequestToLock() APIs which are usable in DXE
and SMM.
Cc: Chasel Chiu
Cc: Liming Gao
Cc: Eric Dong
LargeVariableReadLib is used to retrieve large data sets using
the UEFI Variable Services. At time of writting, most UEFI
Variable Services implementations to not allow more than 64KB
of data to be stored in a single UEFI variable. This library
will split data sets across multiple variables as need
LargeVariableWriteLib is used to store large data sets using
the UEFI Variable Services. At time of writting, most UEFI
Variable Services implementations to not allow more than 64KB
of data to be stored in a single UEFI variable. This library
will split data sets across multiple variables as needed
The baud rate divisor calculation for mini UART on BCM2711 is the same
as on older models since this commit:
https://github.com/raspberrypi/firmware/commit/1e5456a
Signed-off-by: Mario Bălănică
---
Platform/RaspberryPi/Library/DualSerialPortLib/DualSerialPortLib.c | 15
+++
Platfo
The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16
The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform
The RD-N1-Edge platform includes two clusters with four single-thread
CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-N1-Edge platform
The RD-N2 platform includes sixteen single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 32MB. Add PPTT
table for RD-N2 platform with this information.
Signed-off-by: Pranav Madhu
---
.../A
Processor Properties Topology Table (PPTT) describes the topological
structure of processors, and their shared resources such as caches.
This patch series adds PPTT table for Arm's SGI/RD platforms.
The first patch in this series adds helper macros for PPTT table, and
the subsequent patches in thi
Add helper macros for the creation for PPTT table. These macros help
with initializing processor hierarchy node structure, cache type
structure and ID structure.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 163 +++-
1 file changed, 162 insertions
The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512K
The RD-V1 platform includes sixteen single-thread CPUs. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB
L2 cache. The platform also includes a system level cache of 16MB.
Add PPTT table for RD-V1 platform with this information.
Signed-off-by: Pranav Madhu
---
.../A
From: Pranav Madhu
The SGI-575 platform includes two clusters with four single-thread CPUs.
Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table
for SGI-575 platform with this information.
Signed-off-by: P
Hi, Nate,
Yes, It was an error message. I'm sorry about this, because I didn't operate
git cherry pick well, resulting in the wrong patches. But I have corrected it.
Please ignore it.
Thanks,
Ling
> -原始邮件-
> 发件人: "Desimone, Nathaniel L"
> 发送时间: 2021-04-02 03:19:58 (星期五)
> 收件人: "Ling J
Hi liming,
Could you help push the patch since I don't have the privilege to set the push
label?
Thanks,
Jiaxin
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of
> gaoliming
> Sent: Friday, April 2, 2021 2:24 PM
> To: Wu, Jiaxin ; devel@edk2.groups.io
> Cc: Kinney, Micha
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