RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
TDX guest supports LocalApicTimer. But in current OvmfPkg the supported
timer is 8254TimerDxe. So gUefiOvmfPkgTokenSpaceGuid.PcdTimerSelector
is introduced to select the running Timer. The Timer driver will check
the TimerSelector in its
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
The IOMMU protocol driver provides capabilities to set a DMA access
attribute and methods to allocate, free, map and unmap the DMA memory
for the PCI Bus devices.
The current IoMmuDxe driver supports DMA operations inside SEV guest.
To
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In the previous QemuFwCfgDxe only SEV is supported. This commit
introduce TDX support in QemuFwCfgDxe.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James Bottomley
Cc: Jiewen Yao
Cc: Tom Lendacky
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Add Intel TDXhelper library. The library provides the routines to:
- set or clear Shared bit for a given memory region.
- query whether TDX is enabled.
Cc: Ard Biesheuvel
Cc: Jordan Justen
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In TDX the guest firmware is designed to publish a multiprocessor-wakeup
structure to let the guest-bootstrap processor wake up guest-application
processors with a mailbox. The mailbox is memory that the guest firmware
can reserve so each
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Intel TDX has its own requirement in InitializePlatform (PlatformPei).
1. Publish the ram region
Host VMM pass the memory region to TDVF in TD Hob. These memory
are accepted by TDVF before they're available for access. TDVF
publish
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
TdxDxe driver is dispatched early in DXE, due to being list in APRIORI.
This module is responsible for below features:
- Sets max logical cpus based on TDINFO
- Sets PCI PCDs based on resource hobs
Besides above features, TdxDxe driver
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In TDX IA32_ERER is RO to host VMM. It could not be changed.
PcdIa32EferChangeAllowed is added in MdeModulePkg.dec and it is to be set
to FALSE in Tdx guest.
Cc: Jian J Wang
Cc: Hao A Wu
Cc: Brijesh Singh
Cc: Erdem Aktas
Cc: James
Add a new ConfidentialComputingGuestAttr PCD that can be used to query
the memory encryption attribute. (This is AMD's patch)
Signed-off-by: Brijesh Singh
---
OvmfPkg/PlatformPei/IntelTdx.c| 8 ++
OvmfPkg/PlatformPei/PlatformPei.inf | 2 +-
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
If TDX is enabled then we do not support DMA operation in PEI phase.
This is mainly because DMA in TDX guest requires using bounce buffer
(which need to allocate dynamic memory and allocating a PAGE size'd
buffer can be challenge in PEI
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
When host VMM create the Td guest, the system memory informations are
stored in TdHob, which is a memory region described in Tdx metadata.
The system memory region in TdHob should be accepted before it can be
accessed. So the major task of
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
EFI_RESOURCE_ATTRIBUTE_ENCRYPTED is Physical memory encrypted attribute.
It indicates the memory uses platform encrpytion capabilities for
protection. If this bit is clear, the memory does not use platform
encryption protection.
Cc: Ard
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In Tdx BSP may issues commands to APs for some task, for example, to
accept pages paralelly. BSP also need to wait until all the APs have
done the task. TdxMailboxLib wraps these common funtions for BSP.
Cc: Ard Biesheuvel
Cc: Jordan
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
IntelTdx.h defines the defitions used by TDX in OvmfPkg:
- Mailbox related defitions,such as the data structure, command code,
AP relocation defitions.
- EFI_HOB_PLATFORM_INFO describes the TDX platform information
Cc: Ard Biesheuvel
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In TDX BSP and APs goes to the same entry point in SecEntry.nasm.
BSP initialize the temporary stack and then jumps to SecMain, just as
legacy Ovmf does.
APs spin in a modified mailbox loop using initial mailbox structure.
Its structure
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
In TDVF BSP and APs are simplified. BSP is the vCPU-0, while the others
are treated as APs.
So MP intialization is rather simple. The processor info is retrieved by
TDCALL, ApWorker is not supported, BSP is always the working processor,
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Add base support to handle #VE exceptions. Update the common exception
handlers to invoke the VmTdExitHandleVe () function of the VmTdExitLib
library when a #VE is encountered. A non-zero return code will propagate
to the targeted exception
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
The base VmTdExitLib library provides a default limited interface. As
it does not provide full support, create an OVMF version of this library
to begin the process of providing full support of TDX within OVMF.
PcdIgnoreVeHalt is created in
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Various CpuExceptionHandlerLib libraries will updated to use the new
VmTdExitLib library. To prevent any build breakage, update the OvmfPkg
DSC files that use a form of the CpuExceptionHandlerLib library to
include the VmTdExitLib library.
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Various CpuExceptionHandlerLib libraries will updated to use the new
VmTdExitLib library. To prevent any build breakage, update the
UefiPayloadPkg.dsc that use a form of the CpuExceptionHandlerLib
library to include the VmTdExitLib library.
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
VmTdExitLib performs the necessary processing to handle a #VE exception.
VmTdExitLibNull is a NULL instance of VmTdExitLib which provides a default
limited interface. A full feature version of VmTdExitLib should be created
later (for
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed
directly from/to CPU. Some should be accessed via explicit requests
from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the
help of TdxLib.
Cc: Eric Dong
Cc:
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Intel TDX architecture does not prescribe a specific software convention
to perform I/O from the guest TD. Guest TD providers have many choices to
provide I/O to the guest. The common I/O models are emulated devices,
para-virtualized
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
TdxLib is created with functions to perform the related Tdx operation.
This includes functions for:
- TdCall : Cause a VM exit to the Intel TDX module.
- TdVmCall: It helps invoke services from the host VMM to pass/
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429
Tdx.h includes the Intel Trust Domain Extension definitions.
Detailed information can be found in below document:
https://software.intel.com/content/dam/develop/external/us/en/
documents/tdx-module-1eas-v0.85.039.pdf
Cc: Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3249
Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology
that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory
Encryption (MKTME) with a new kind of virutal machines guest called a
Trust Domain (TD). A
Signed-off-by: Min Xu
---
OvmfPkg/ResetVector/ResetVector.nasmb| 13 -
OvmfPkg/ResetVector/X64/IntelTdxMetadata.asm | 28 +---
2 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb
Signed-off-by: Min Xu
---
OvmfPkg/OvmfPkg.dec | 9 +
OvmfPkg/OvmfPkgDefines.fdf.inc | 9 +
OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 39 +++
OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm | 11 +
OvmfPkg/ResetVector/Ia32/IntelTdx.asm| 235
Signed-off-by: Min Xu
---
OvmfPkg/ResetVector/Main.asm | 103 +++
1 file changed, 103 insertions(+)
create mode 100644 OvmfPkg/ResetVector/Main.asm
diff --git a/OvmfPkg/ResetVector/Main.asm b/OvmfPkg/ResetVector/Main.asm
new file mode 100644
index
Thanks, Rebecca for the patch.
Acked-by: Nhi Pham
Best regards,
Nhi
On 05/10/2021 01:00, Sami Mujawar wrote:
Hi Rebecca,
Thank you for this patch. These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/10/2021 05:22 PM, Rebecca Cran wrote:
According to
BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Groups.io Inc//Groups.io Calendar//EN
METHOD:CANCELLED
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-PUBLISHED-TTL:PT1H
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
LAST-MODIFIED:20201011T015911Z
On Mon, Oct 04, 2021 at 07:28:27PM +0800, Daniel Schaefer wrote:
> Cc: Abner Chang
> Cc: Sunil V L
> Cc: Leif Lindholm
>
> Signed-off-by: Daniel Schaefer
> ---
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 7
> ++-
>
On Mon, Oct 04, 2021 at 01:23:58AM +0800, Daniel Schaefer wrote:
> Otherwise it will crash on QEMU 6.0 with:
>
> > Loading driver at 0x000BF814000 EntryPoint=0x000BF81428A
> > PciHostBridgeDxe.efi
> > InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF BF351F98
> >
On Mon, Oct 04, 2021 at 01:23:59AM +0800, Daniel Schaefer wrote:
> Otherwise we can't load a 3rd party image because we're still in DXE.
> MdeModulePkg/Universal/SecurityStubDxe/Defer3rdPartyImageLoad.c prevents
> that.
>
> Cc: Abner Chang
> Cc: Sunil V L
> Cc: Leif Lindholm
>
>
On Mon, Oct 04, 2021 at 01:23:56AM +0800, Daniel Schaefer wrote:
> While enumerating the PCIe devices, the driver tries to set some caching
> attributes on the memory.
>
> Cc: Abner Chang
> Cc: Sunil V L
> Cc: Leif Lindholm
>
> Signed-off-by: Daniel Schaefer
> ---
>
On Mon, Oct 04, 2021 at 01:23:57AM +0800, Daniel Schaefer wrote:
> Cc: Abner Chang
> Cc: Sunil V L
> Cc: Leif Lindholm
>
> Signed-off-by: Daniel Schaefer
> ---
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 7
> +++
>
The patch set for edk2 looks fine to me.
Reviewed-by: Sunil V L
Thanks
Sunil
On Thu, Sep 30, 2021 at 08:45:36AM +0800, Abner Chang wrote:
> In V3: Address comments on V2.
> In V2: Remove HPE license on the files that just moved around or
>the changes in the file are just code removal.
Looks good to me.
Reviewed-by: Sunil V L
Thanks
Sunil
On Mon, Oct 04, 2021 at 01:23:55AM +0800, Daniel Schaefer wrote:
> Not DiskIoDxe because we don't have a disk, just for loading from
> Ramdisks.
>
> Cc: Abner Chang
> Cc: Sunil V L
> Cc: Leif Lindholm
>
> Signed-off-by: Daniel Schaefer
Yao,
I think this series has the needed R-b's and should be commit-able.
Cheers!
Stefan
On 9/24/21 7:42 AM, Stefan Berger wrote:
This series of patches disables the TPM 2 platform hierarchy.
We just added the same functionality to the OvmfPkg. However, on x86, we
could use the
Hi Omkar,
This patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 24/08/2021 07:00 AM, Omkar Anand Kulkarni wrote:
Allow platforms to define the base address and size of the memory region
that is reserved for MM drivers to populate the GHES generic error
status
Hi Abner,
Thank you for this patch. This change looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/10/2021 10:29 AM, Abner Chang wrote:
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that
Hi Rebecca,
Thank you for this patch. These changes look good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/10/2021 05:22 PM, Rebecca Cran wrote:
According to the SMBIOS specification, the ExtendedBiosSize field should
be zero when the BIOS size is less than 16MB:
"Size (n)
Hi Omkar,
Thank you for adding this description. This is really helpful to
understand the framework.
I have a few minor suggestions marked inline as [SAMI].
With those changed,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 24/08/2021 06:34 AM, Omkar Anand Kulkarni wrote:
Added a
Hi Omkar,
Please find my feedback inline marked [SAMI].
Regards,
Sami Mujawar
On 24/08/2021 06:34 AM, Omkar Anand Kulkarni wrote:
Add the protocol definition of the MM_HEST_ERROR_SOURCE_DESC_PROTOCOL
protocol. This protocol can be implemented by MM drivers to publish
error source
Hi Omkar,
This patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 24/08/2021 06:34 AM, Omkar Anand Kulkarni wrote:
Add helper macros for the generation of the HEST ACPI table. Macros to
initialize the HEST GHESv2 Notification Structure and Error Status
Structure are
Hi Omkar,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 24/08/2021 06:34 AM, Omkar Anand Kulkarni wrote:
Add a driver that retreives error source descriptors from MM and
populates those into the HEST ACPI table. The error source descriptors
that are available from
Hi Omkar,
Please find my feedback inline marked [SAMI].
Regards,
Sami Mujawar
On 24/08/2021 06:33 AM, Omkar Anand Kulkarni wrote:
Introduce the HEST table generation protocol that allows platforms to
build the table with multiple error source descriptors and install the
table. The protocol
Hi Omkar,
The subject for this patch series should be fixed. These patches are not
for edk2-platforms.
Regards,
Sami Mujawar
On 24/08/2021 06:33 AM, Omkar Anand Kulkarni wrote:
Changes since v2:
- Addressed the comments given by Sami.
- Added Readme file with all cover letter information.
According to the SMBIOS specification, the ExtendedBiosSize field should
be zero when the BIOS size is less than 16MB:
"Size (n) where 64K * (n+1) is the size of the
physical device containing the BIOS, in
bytes.
FFh - size is 16MB or greater, see Extended
BIOS ROM Size for actual size."
Fix the
04.10.2021 17:23:47 Kuo, IanX :
> Hi Marvin
>
> Reply in mail
>
> Thanks,
> Ian Kuo
>
> -Original Message-
> From: Marvin Häuser
> Sent: Monday, October 4, 2021 8:56 PM
> To: devel@edk2.groups.io; Kuo, IanX
> Cc: Chan, Amy ; Ni, Ray ; Kinney,
> Michael D ; Liming Gao
> ; Liu, Zhiguang
Hi Marvin
Reply in mail
Thanks,
Ian Kuo
-Original Message-
From: Marvin Häuser
Sent: Monday, October 4, 2021 8:56 PM
To: devel@edk2.groups.io; Kuo, IanX
Cc: Chan, Amy ; Ni, Ray ; Kinney, Michael
D ; Liming Gao ; Liu,
Zhiguang
Subject: Re: [edk2-devel] [PATCH v5 1/4]
Good day IanX,
On 04/10/2021 07:03, IanX Kuo wrote:
From: IanX Kuo
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675
Remove MdeModulePkg dependency
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Signed-off-by: IanX Kuo
---
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
Good day IanX,
On 04/10/2021 07:03, IanX Kuo wrote:
From: IanX Kuo
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675
Add QuickSort function into BaseLib
Cc: Ray Ni
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Signed-off-by: IanX Kuo
---
MdePkg/Include/Library/BaseLib.h
Hi Omkar,
Please find my feedback inline marked [SAMI].
Regards,
Sami Mujawar
On 24/08/2021 07:00 AM, Omkar Anand Kulkarni wrote:
Enables firmware first error handling on the given platform. Installs
and publishes the SDEI and HEST ACPI tables required for firmware first
error handling.
Hi Omkar,
I have a minor suggestion marked inline as [SAMI].
Other than that this patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 24/08/2021 07:00 AM, Omkar Anand Kulkarni wrote:
Enable the use of HEST table generation protocol, GHES error source
descriptor
Hi Omkar,
Thank you for this patch.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 24/08/2021 07:00 AM, Omkar Anand Kulkarni wrote:
For ACPI tables that are generated dynamically, define the ACPI table
header values that have to be used to build the table header.
Co-authored-by:
Hi Leif,
There are two comments that I would like to clarify with you.
On 23/09/2021 20:49, Leif Lindholm wrote:
+VOID
+Ac01PcieMmioWr (
+ UINT64 Addr,
+ UINT32 Val
+ )
+{
+ Ac01PcieCsrOut32Serdes ((VOID *)Addr, (UINT32)Val);
+}
+
+VOID
+Ac01PciePuts (
Wait, what. We have *two* sets of
Hi Leif,
Thanks a lot for your review. We are heading to improve the Ac01PcieLib
and addressing your comments in the PciSegmentLib, by decoupling the
Ac01PcieLib into hierarchical modules. Hoping it will look better to you.
Best regards,
Nhi
On 28/09/2021 17:34, Leif Lindholm wrote:
Otherwise we can't load a 3rd party image because we're still in DXE.
MdeModulePkg/Universal/SecurityStubDxe/Defer3rdPartyImageLoad.c prevents
that.
Cc: Abner Chang
Cc: Sunil V L
Cc: Leif Lindholm
Reviewed-By: Sunil V L
Signed-off-by: Daniel Schaefer
---
While enumerating the PCIe devices, the driver tries to set some caching
attributes on the memory.
Cc: Abner Chang
Cc: Sunil V L
Cc: Leif Lindholm
Reviewed-By: Sunil V L
Signed-off-by: Daniel Schaefer
---
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 4 ++--
1 file changed, 2
Cc: Abner Chang
Cc: Sunil V L
Cc: Leif Lindholm
Signed-off-by: Daniel Schaefer
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 7
++-
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 1 +
Otherwise it will crash on QEMU 6.0 with:
> Loading driver at 0x000BF814000 EntryPoint=0x000BF81428A PciHostBridgeDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF BF351F98
> ProtectUefiImageCommon - 0xBF365BC0
> - 0xBF814000 - 0x000124C0
> PROGRESS CODE:
Not DiskIoDxe because we don't have a disk, just for loading from
Ramdisks.
Cc: Abner Chang
Cc: Sunil V L
Cc: Leif Lindholm
Reviewed-By: Sunil V L
Signed-off-by: Daniel Schaefer
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 7
++-
Changes from v1:
- Remove ShellLib override in 3/5
Tested on the unpublshed riscvvirt branch and it can still boot to
Linux.
Cc: Abner Chang
Cc: Sunil V L
Cc: Leif Lindholm
Daniel Schaefer (5):
U540, U500: Add filesystem drivers
RISC-V/CpuDxe: Ignore set memory attributes failure
U540,
> -Original Message-
> From: Sunil V L [mailto:suni...@ventanamicro.com]
> Sent: Monday, October 4, 2021 7:02 PM
> To: Schaefer, Daniel
> Cc: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> ; Leif Lindholm
> Subject: Re: [PATCH v1 4/5] U540: BuildCpuHob with 48 to
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
BZ:#3665 is to migrate some modules from ArmVirtPkg
to under OvmfPkg for the upcoming RiscVVirtPkg that can leverage
those modules without the dependency with Arm*Pkg.
Refer to below message of the pacthes of edk2 portion.
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
QemuFwCfg is relocated from ArmVirtPkg to OvmfPkg/Library/QemuFwCfgLib and
renamed as QemuFwCfgMmio, use the OvmfPkg one
instead of the one under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PciPcdProducerLib is relocated from ArmVirtPkg to OvmfPkg/Fdt, use
OvmfPkg one instead.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Daniel Schaefer
---
Platform/Comcast/RDKQemu/RDKQemu.dsc |
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
HighMemDxe is relocated from ArmVirtPkg to OvmfPkg/Fdt, use the
OvmfPkg one instead.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Daniel Schaefer
---
Platform/Comcast/RDKQemu/RDKQemu.dsc | 2
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg instead the one
under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Leif Lindholm
Cc: Peng
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Thomas
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Leif Lindholm
Cc: Ard
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
PcdPciIoTranslation PCD is relocated to MdePkg that leveraged by
both ARM and RISC-V arch. This patch uses the one from MdePkg
instead the one under ArmVirtPkg.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif
Complaint with BZ: #3665
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
FdtClientDxe is relocated to under EmbeddedPkg.
Signed-off-by: Abner Chang
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Daniel Schaefer
---
Platform/Comcast/RDKQemu/RDKQemu.dsc | 2 +-
1 file changed, 1 insertion(+), 1
https://bugzilla.tianocore.org/show_bug.cgi?id=3665
BZ:#3665 is to migrate some modules from ArmVirtPkg
to under OvmfPkg for the upcoming RiscVVirtPkg that can leverage
those modules without the dependency with Arm*Pkg.
Refer to below message of the pacthes of edk2 portion.
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