REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3757
Add registers of boot partition feature which defined in NVM Express 1.4 Spec
Cc: Liming Gao
Cc: Michael D Kinney
Cc: Zhiguang Liu
Signed-off-by: Maggie Chu
---
MdePkg/Include/IndustryStandard/Nvme.h | 113 -
1
Prefer the e820 map provided via qemu firmware config interface
for memory detection. Use rtc cmos only as fallback, which should
be rarely needed these days as qemu supports etc/e820 since 2013.
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3593
Signed-off-by: Gerd Hoffmann
Reviewed-by:
Not needed for qemu 1.7 (released in 2013) and newer.
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3593
Signed-off-by: Gerd Hoffmann
---
OvmfPkg/PlatformPei/MemDetect.c | 59 +++--
1 file changed, 4 insertions(+), 55 deletions(-)
diff --git
Add a bool parameter to ScanOrAdd64BitE820Ram to explicitly specify
whenever ScanOrAdd64BitE820Ram should add HOBs for high memory (above
4G) or scan only.
Also add a lowmem parameter so ScanOrAdd64BitE820Ram
can report the memory size below 4G.
This allows a more flexible usage of
Don't use cmos for memory detection if possible.
qemu provides the etc/e820 firmware config file
as alternative since 2013.
v4:
- uncrustify & rebase to latest master.
v3:
- fix CI failure.
v2:
- fix lowmem detection.
- pick up review tags.
- add rfc patch to completely drop cmos support.
Nate,
I don't consider it as a hack. UefiPayloadPkg requires that bootloader produces
all ACPI tables.
Now we are in a middle stage. So, only the MCFG and FADT are produced (as
gUniversalPayloadAcpiTableGuid HOB) in PEI phase.
Thanks,
Ray
-Original Message-
From: devel@edk2.groups.io
On December 7, 2021 4:05 PM, Gerd Hoffmann wrote:
> > [Jiewen] OK, I talked with Min again. 12ms is not right data today.
> > We have bigger number, but I cannot share the data according to legal
> reason.
> >
> > But I agree with your statement that, if the data is small enough, then we
> don't
Hi Chandni,
One input,
On Sat, Dec 4, 2021 at 04:31 AM, chandni cherukuri wrote:
>
> This patch implements the configuration manager for Morello
> SoC platform. It enables support for generating the following
> ACPI tables for Morello SoC Platform:
> 1. FADT
> 2. DSDT
> 3. GTDT
> 4. MADT
> 5.
Exactly. That sounds good.
--
Rebecca Cran
On 12/5/21 12:23 AM, Michael D Kinney wrote:
Rebecca,
I am guessing that you just ran Doxygen against the tree without the
processing of DEC files that provides the LibraryClass, Protocol, PPI, GUID
and PCD information from each package.
These are
I have a doxyfile at https://bsdio.com/edk2/docs/master.doxyfile which
generates it.
I run "doxygen ../master.doxyfile" from the root of an edk2 clone.
--
Rebecca Cran
On 12/5/21 12:09 AM, Michael D Kinney wrote:
Rebecca,
I like that combined version.
How did you package them together?
I have a doxyfile at https://bsdio.com/edk2/docs/master.doxyfile which
generates it.
I run "doxygen ../master.doxyfile" from the root of an edk2 clone.
--
Rebecca Cran
On 12/5/21 12:09 AM, Michael D Kinney wrote:
Rebecca,
I like that combined version.
How did you package them together?
Hi Sami, Chandni,
There was a suggestion from Pierre on a similar patch for N1SDP to remove
PCIExpressLib.c and move to workarounds to PCISegmentLib.c,
https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273
I
BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Groups.io Inc//Groups.io Calendar//EN
METHOD:PUBLISH
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-PUBLISHED-TTL:PT1H
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
LAST-MODIFIED:20201011T015911Z
This seems like a hack to me. One of the major goals of the Minimum Platform
Architecture is consistency. A board override for the MinPlatform provided
installation of the MCFG table runs counter to that goal. Every field in the
MCFG table produced by MinPlatform's implementation is fully
Pushed: https://github.com/tianocore/edk2-platforms/commit/15d8aa1
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Nate
> DeSimone
> Sent: Wednesday, December 1, 2021 2:52 PM
> To: devel@edk2.groups.io
> Cc: Bi, Dandan ; Liming Gao
> ; Jadhav, Manoj D
> ; Chiu, Chasel
>
Hi Andrew,
I just sent the patch: https://edk2.groups.io/g/devel/message/84476
There's a rendered version of the file on my wiki fork:
https://github.com/makubacki/tianocore.github.io/blob/add_uncrustify_instructions/EDK-II-Code-Formatting.md
Thanks,
Michael
On 12/7/2021 4:04 PM, Andrew Fish
From: Michael Kubacki
This wiki page describes how Uncrustify is used in EDK II and how
to install and use Uncrustify during the EDK II code development
process.
Cc: Andrew Fish
Cc: Leif Lindholm
Cc: Michael D Kinney
Cc: Liming Gao
Signed-off-by: Michael Kubacki
---
> On Dec 7, 2021, at 12:35 PM, Michael Kubacki
> wrote:
>
> I will send a patch for the Tianocore Wiki shortly.
>
OK thanks. I can test on Linux and macOS.
Maybe I’ll try using VS Code as my editor now….
Thanks,
Andrew Fish
> Thanks,
> Michael
>
> On 12/7/2021 2:27 PM, Andrew Fish via
Hi Brijesh,
Yes. Your branch can be rebased on top of edk2/master after uncrustify changes.
You have added new c/h files, so those files need to be run through uncrustify
locally and
your patch updated with those formatting changes.
The following command updates every c/h file except
Hi Chandni,
Thank you for this patch.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
Morello SoC platform support has added and also
boot flow modified to reflect the new boot flow
for both Morello FVP and Morello SoC platforms
Hi Chandni,
Please find my feedback inline marked [SAMI].
With those fixed,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
From: sah01
Support has been added to parse NT_FW_CONFIG DTB to get the
platform information.
Signed-off-by:
Hi Chandni,
Please find my feedback marked inline as [SAMI].
With that fixed,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
From: Anurag Koul
Add definitions for both PCIe and CCIX Root Complex in PciHostBridge
Library. Also, use
Hi Chandni,
Thank you for this patch.
Please find my feedback inline marked [SAMI].
With those addressed.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
From: Anurag Koul
Morello platform requires a custom platform-specific PCI Express
Hi Chandni,
Thank you for this patch.
I have a minor suggestion marked inline as [SAMI].
Otherwise this patch looks good to me.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
From: Anurag Koul
A custom PCI Segment library is required
Hi Chandni,
I would suggest adding a brief introduction about the Morello SoC
platform in the commit message.
Otherwise, this patch looks good to me.
With the commit message updated.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
This
Hi Chandni,
Since you have the CPU information in MADT.GICC and the PPTT table, it
should be possible to use the SSDT CPU generator to create the AML
description for the CPUs. This patch series can go ahead. However, you
may want to consider using the SSDT Cpu Generator in the furture.
Hi Brijesh,
A Tianocore wiki article is being prepared but the background and
instructions for what to do were sent in this mail regarding the hard
freeze being lifted - https://edk2.groups.io/g/devel/message/84458.
Do you have questions after reading through that?
Thanks,
Michael
On
Hi Chandni,
Please find my feedback inline marked [SAMI].
With that fixed,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
This patch adds PlatformDxe support for Morello SoC platform.
It includes the registration of ramdisk device.
Hi Chandni,
Thank you for this patch.
Please find my feedback inline marked [SAMI].
With that updated,
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
It includes virutal memory map for Morello SoC platform.
Signed-off-by: Chandni
Hi Chandni,
Thank you for this patch.
I think the following change from "[edk2-platforms][PATCH V1 05/11]
Platform/ARM/Morello: Add initial support for Morello SoC" should be
part of this patch.
diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc
I will send a patch for the Tianocore Wiki shortly.
Thanks,
Michael
On 12/7/2021 2:27 PM, Andrew Fish via groups.io wrote:
On Dec 7, 2021, at 11:22 AM, Michael D Kinney
wrote:
Hello,
Thank you to everyone for their patience and for everyone who helped with the
development
and review of
Hi All,
I am rebasing the SNP series and encountering the error like below from
the CI. I am not sure what I am missing. For testing purpose, I just
tried one commit and CI Windows build complains about this. This is the
same patch which passed all the CI. Any idea what I maybe missing ?
> On Dec 7, 2021, at 11:22 AM, Michael D Kinney
> wrote:
>
> Hello,
>
> Thank you to everyone for their patience and for everyone who helped with the
> development
> and review of this important update to the edk2 repository.
>
> The last 2 PR series have completed review, passed EDK II
Hello,
Thank you to everyone for their patience and for everyone who helped with the
development
and review of this important update to the edk2 repository.
The last 2 PR series have completed review, passed EDK II CI checks, passed
CompareBuild
verifications, and been pushed.
This commit will add a protocol/PPI definition which will provide a generic and
unified way to get information about dies installed in the system(PCH, SoC,
CPU).
It will be implemented per generation in silicon packages.
v4 changes:
- removed Signature field
v3 changes:
- added EDKII_ prefix
Added IntelDieInfo header into IntelSiliconPkg tree.
The purpose is to have generic and unified interface for getting
information about dies installed in the system.
It will be implemented by silicon code.
Cc: Ray Ni
Cc: Rangasai V Chaganty
Signed-off-by: Maciej Czajkowski
---
Notes:
v4:
Hi Mike,
Thanks a lot for these changes.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 06/12/2021, 01:18, "devel@edk2.groups.io on behalf of Michael D Kinney via
groups.io" wrote:
Hello EDK II Maintainers,
A detailed evaluation of the DEBUG_CODE() formatting issue has been
Update VTd register structs accroding to VTd spec ver 3.3
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3765
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Jenny Huang
Cc: Robert Kowalewski
Signed-off-by: Sheng Wei
---
.../Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.c | 3 +-
It is DRHD(DMA Remapping Hardware Unit Definition).
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3622
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Jenny Huang
Cc: Robert Kowalewski
Signed-off-by: Sheng Wei
---
.../IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/DmarTable.c | 12 ++--
VTdInfoNotify may be called manay times, PEI DMA buffer should be
generated only once.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3667
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Jenny Huang
Cc: Robert Kowalewski
Signed-off-by: Sheng Wei
---
.../Feature/VTd/IntelVTdDmarPei/DmarTable.c
If VTd ECAP_REG.ADMS bit is set, abort DMA mode is supported.
When VTd Abort DMA Mode is enabled, hardware will abort all DMA
operations without the need to set up a root-table with each
entry marked as not-present.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3766
Cc: Ray Ni
Cc:
[PATCH 1/4] IntelSiliconPkg/VTd: Fix typos
[PATCH 2/4] IntelSiliconPkg/VTd: Update VTd register structs
[PATCH 3/4] IntelSiliconPkg/VTd: Support VTd Abort DMA Mode
[PATCH 4/4] IntelSiliconPkg/VTd: Only generate PEI DMA buffer once.
Patch v2 update:
Fix build error in [PATCH 2/4] and [PATCH 4/4]
Hi,
> [Jiewen] OK, I talked with Min again. 12ms is not right data today.
> We have bigger number, but I cannot share the data according to legal reason.
>
> But I agree with your statement that, if the data is small enough, then we
> don't need MP in sec.
>
> I propose this way:
> 1) In
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