-off-by: Dhaval Sharma
---
MdeModulePkg/Core/Dxe/Mem/Page.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MdeModulePkg/Core/Dxe/Mem/Page.c b/MdeModulePkg/Core/Dxe/Mem/Page.c
index 5a51d9df1a29..e4daa741b971 100644
--- a/MdeModulePkg/Core/Dxe/Mem/Page.c
+++ b/MdeModulePkg/Core/Dxe/Mem
Most of the times it is desirable not to use special purpose
memory for regular edk2 usages. That memory (HBm/CXL) are
either meant for special purposes or are less reliable to
be used. So avoid using them as long as possible. We could
also introduce PCD for this control.
Provide commandline configuration to select proper platform file.
Cc: Gua Guo
Cc: Guo Dong
Cc: James Lu
Cc: Sean Rhodes
Signed-off-by: Dhaval Sharma
---
UefiPayloadPkg/UniversalPayloadBuild.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/UefiPayloadPkg
Related to this, I also faced this issue where in order to prevent edk2 from
allocating this memory I had to modify CoreFindFreePagesI
//
// Don't allocate out of Special-Purpose memory.
//
if ((Entry->Attribute & EFI_MEMORY_SP) != 0) {
continue;
}
Can't we add PCD based logic here to selectively
I also believe this code needs to go through crustify etc to ensure it
follows all edk2 standards?
On Mon, Jun 3, 2024 at 4:57 PM Dhaval Sharma wrote:
> BuildFitLoadablesFvHob:
>
>- Fdt variable is not initialized.
>- It ONLY gets initialized if GuidHob is
me x86 specific function in the x86 folder.
> Create HandOffHob via FDT memory node.
>
> Cc: Benny Lin
> Cc: Gua Guo
> Cc: Chasel Chiu
> Cc: James Lu
> Cc: Dhaval Sharma
>
> Signed-off-by: Linus Liu
> ---
> UefiPayloadPkg/UefiPayloadEn
Hi,
Is there any plan to upstream these HEST/ACPI patches? They seem to be arch
agnostic.
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Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval Sharma
Reviewed-by: Gua Guo
---
Notes:
v1:
- Updated RB tab
UefiPayloadPkg
Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval Sharma
Dhaval (1):
UefiPayloadPkg: Make Dsc accomodative of other archs
Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval Sharma
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 48 +++-
1 file
Current DSC files contains a lot of files which are
specific to X86 arch. Need to move around files under
arch specific sections.
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval Sharma
Dhaval (1):
UefiPayloadPkg: Make Dsc accomodative of other archs
Current implementation makes assumptions about arch it will be built
for. Need to make it more generic to add follow up support for RISCV.
Right now it does not build for RV until relevant dsc file is available.
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval
Current implementation makes assumptions about arch it will be built
for. Need to make it more generic to add follow up support for RISCV.
Right now it does not build for RV until relevant dsc file is available.
https://github.com/tianocore/edk2/pull/5395
Cc: Guo Dong
Cc: Sean Rhodes
Cc: James
.groups.io
Signed-off-by: Dhaval Sharma
Acked-by: Chasel Chiu
---
Notes:
v5:
- If DSDT is not found, throw error and continue to build other tables
v4:
- Fix typos and commit message adding more clarity to patch subject
v3:
- Added description of ACPI spec clarification based
.groups.io
Signed-off-by: Dhaval Sharma
Acked-by: Chasel Chiu
Notes:
v5:
- If DSDT is not found, throw error and continue to build other tables with
an error log
v4:
- Fix typos and commit message adding more clarity to patch subject
v3:
- Added description of ACPI spec
"The CpuDxe interface will be the wrapper." Yes, of course. It needs to be
added. I was just saying that maybe any CMO checking is not required there
as cmo library will take care of it.
On Tue, Jan 23, 2024 at 10:24 PM Sunil V L wrote:
> On Tue, Jan 23, 2024 at 11:42:57AM +0530,
gger message. Eventually platform/drivers need to have
> > better guard for such functionality.
> >
> > Signed-off-by: Dhaval Sharma
> > Cc: Liming Gao
> > Cc: Michael D Kinney
> > Cc: Zhiguang Liu
> > Cc: Sunil V L
> > Cc: Andrei Warkentin
> > Cc: L
Hi Pedro,
Agree Assert is slightly more enforcing over logs, but you could still get
away with even Assert in release mode.
One alternative is to convert VERBOSE into WARNING?
=D
On Thu, Jan 18, 2024 at 9:28 PM Pedro Falcato
wrote:
> On Thu, Jan 18, 2024 at 9:50 AM Dhaval wrote:
> >
> > Some
-off-by: Dhaval Sharma
Cc: Liming Gao
Cc: Michael D Kinney
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Andrei Warkentin
Cc: Laszlo Ersek
Cc: Pedro Falcato
Cc: Yang Cheng
---
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff
environment. While it is not an issue in production environment, there
is a recommendation to convert this assert in to a harmless logger message.
Eventually platform/drivers need to have better guard for such functionality.
Signed-off-by: Dhaval Sharma
Cc: Liming Gao
Cc: Michael D Kinney
Cc
ject: Re: [edk2-devel] [PATCH v10 4/5] MdePkg: Utilize Cache
> > Management Operations Implementation For RISC-V
> >
> > On Mon, Jan 08, 2024 at 09:53:46PM +, Pedro Falcato wrote:
> > > On Mon, Jan 8, 2024 at 4:23 PM Dhaval Sharma
> > wrote:
> >
Hi yangcheng/Pedro,
Thanks for bringing this up. I understand the issue and probably we could just
keep it simple with a warning instead of an assert. But wanted to mention a
couple of points:
1. I think initially even in my patchset it was DEBUG message but there was a
comment to turn it into
Reviewed-by: Dhaval Sharma
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Signed-off-by: Dhaval Sharma
Acked-by: Chasel Chiu
---
Notes:
v4:
- Fix typos and commit message adding more clarity to patch subject
v3:
- Added description of ACPI spec clarification based on which this patch is
created
- Optimizing if-else flow
v2:
- Added
Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9. https://github.com/tianocore/edk2/pull/5235
Dhaval (1):
MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing
tables
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c |
in a single line works better please feel free to update.
And Thanks!
On Tue, Dec 19, 2023 at 12:59 PM Sunil V L wrote:
> On Wed, Dec 13, 2023 at 08:29:30PM +0530, Dhaval Sharma wrote:
> > Use newly defined cache management operations for RISC-V where possible
> > It builds up
: Jordan Justen
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Cc: Laszlo Ersek
Cc: Pedro Falcato
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
Reviewed-by: Andrei Warkentin
---
Notes:
V10:
- Only keep CMO feature bitmask bit to disabled. Unimplemented bits
remain
: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Cc: Pedro Falcato
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
Reviewed-by: Sunil V L
Reviewed-by: Jingyu Li
---
Notes:
v8:
- Add *asm* postfix to cmo functions
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Cc: Pedro Falcato
Signed-off-by: Dhaval Sharma
Acked
, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Cc: Pedro Falcato
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
---
Notes:
V8:
- Update function name to udpate *asm
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Cc: Pedro Falcato
Signed-off-by: Dhaval Sharma
Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction
Thanks for the review. My comments inline:
On Fri, Dec 8, 2023 at 9:58 AM Sunil V L wrote:
> On Thu, Dec 07, 2023 at 10:31:48AM +0530, Dhaval Sharma wrote:
> > Comments inline:
> >
> >
> > On Wed, Dec 6, 2023 at 7:50 PM Sunil V L
> wrote:
> >
> > &g
Comments inline:
On Wed, Dec 6, 2023 at 7:50 PM Sunil V L wrote:
> Hi Dhaval,
>
> Thank you very much for fixing the issue with instruction cache
> invalidation and confirming with the spec owner. Few minor comments
> below.
>
> On Mon, Dec 04, 2023 at 01:59:49PM +0530
: Jordan Justen
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
Reviewed-by: Andrei Warkentin
---
Notes:
V8:
- Added RV tag
V7:
- Added RB tag
v6:
- Modify PCD name according to changes made
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
---
Notes
: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
Reviewed-by: Sunil V L
Reviewed-by: Jingyu Li
---
Notes:
v8:
- Add *asm* postfix to cmo functions
- Add reviewed by tags
, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
---
Notes:
V8:
- Update function name to udpate *asm* in the end
V7
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed
Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction
As per ACPI Spec 6.5+ Table 5-9 if xDSDT is available,
it should be used first. Handle required flow when xDSDT
is absent or present.
Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Dandan Bi
Signed-off-by: Dhaval Sharma
Acked
Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9.
Dhaval (1):
MdeModulePkg/AcpiTableDxe: Prefer xDSDT over DSDT when installing
tables
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 23
++--
1 file changed,
> Chasel
> >
> >
> >> -Original Message-
> >> From: devel@edk2.groups.io On Behalf Of Dhaval
> >> Sharma
> >> Sent: Friday, November 17, 2023 3:35 AM
> >> To: devel@edk2.groups.io
> >> Cc: Gao, Liming ; Liu, Zhiguang
> >&
:55 PM Laszlo Ersek wrote:
> On 11/17/23 09:07, Dhaval Sharma wrote:
> > Hi,
> > I wanted to revisit this thread and I am maintaining the context as
> > there are a lot of details already mentioned here
> regarding EFI_MEMORY_SP.
> > Other than what has been addr
As per ACPI Spec 6.5+ Table 5-9 if xDSDT is avaialble,
it should be used first. Handle required flow when xDSDT
is abscent or present.
Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Dandan Bi
Signed-off-by: Dhaval Sharma
Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9.
Dhaval (1):
MdeModulePkg: Fix issue with ACPI table creation
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 22
+---
1 file changed, 15 insertions(+), 7
As per ACPI Spec 6.5+ Table 5-9 if xDSDT is avaialble,
it should be used first. Handle required flow when xDSDT
is abscent or present.
Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Dandan Bi
Signed-off-by: Dhaval Sharma
Enable detection of XDSDT table from ACPI HOB and use it to comply
with ACPI spec 6.5+ Table 5-9.
Dhaval (1):
MdeModulePkg: Fix issue with ACPI table creation
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 22
+---
1 file changed, 15 insertions(+), 7
As per spec if xDSDT is avaialble, it should be used first.
Handle required flow when xDSDT is abscent or present.
Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Dandan Bi
Signed-off-by: Dhaval Sharma
---
Notes:
v2
Enable detection of XDSDT table from ACPI HOB and use it
if it is available: https://github.com/tianocore/edk2/pull/5051
Dhaval (1):
MdeModulePkg: Fix issue with ACPI table creation
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 13 -
1 file changed, 12
Hi,
I wanted to revisit this thread and I am maintaining the context as there are a
lot of details already mentioned here regarding EFI_MEMORY_SP.
Other than what has been addressed here, we also would like to have an option
in edk2 to *avoid* using this type of memory for its own purposes. This
: Jordan Justen
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
Reviewed-by: Andrei Warkentin
---
Notes:
V8:
- Added RV tag
V7:
- Added RB tag
v6:
- Modify PCD name according to changes made
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
---
Notes
: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
Reviewed-by: Sunil V L
Reviewed-by: Jingyu Li
---
Notes:
v8:
- Add *asm* postfix to cmo functions
- Add reviewed by tags
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed
, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
---
Notes:
V8:
- Update function name to udpate *asm* in the end
V7
Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction
e something like “If
> PcdPtrValue != NULL && ((struct cast *) PcdPtrValue)->LegibleFieldName”. I
> think this would do wonders for code maintainability. The cost of course is
> in having to initialize the Pcd now at runtime, and the additional
> dereference, but that seems like
; >
> > On 10/29/23 20:12, Pedro Falcato wrote:
> > > On Sun, Oct 29, 2023 at 2:46 PM Dhaval Sharma
> wrote:
> > >>
> > >> Implement Cache Management Operations (CMO) defined by
> > >> RISC-V spec https://github.com/riscv/riscv-CMOs.
>
Can we define these bits in the header file so that the definitions can
be used by multiple modules?
[Dhaval] I could put it un Baselib.h (MDE_CPU_RISCV64) but sounds like right
now BaseLib.h is free of such #defines. If you think it is still better would
do it. I do not have any preference.
NIT: I am wondering whether PcdRiscVCpuFeatureDisable is better so that
it is explicit.
[Dhaval] Well setting it to 1 would mean feature is enabled. Do it would be
confusing to see PcdRiscVCpuFeatureDisable == 1 means feature is enabled.
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Thanks. This PCD is for Virt platform only. Or maybe I am missing the point.
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Here we go. https://github.com/tianocore/edk2/pull/4974
On Tue, Oct 31, 2023 at 9:46 AM Warkentin, Andrei <
andrei.warken...@intel.com> wrote:
> Hi Dhaval,
>
> Do you mind sharing the repo with the full patch set? Like a github link?
>
> A
>
> > -Original Message-
> > From: Dhaval
> >
Replied inline. Most of the cases I have addressed in the new patch I
submitted.
On Wed, Oct 25, 2023 at 1:39 AM Pedro Falcato
wrote:
> On Sat, Oct 21, 2023 at 6:33 PM Dhaval Sharma wrote:
> >
> > Use newly defined cache management operations for RISC-V where possible
&
: Jordan Justen
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
---
Notes:
V7:
- Added RB tag
v6:
- Modify PCD name according to changes made in Baselib implementation
V5:
- Introduce PCD
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
---
Notes
D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
---
Notes:
V7:
- Modify instruction names as per feedback from V6
- Added RB
V6:
- Implement Cache management instructions
, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo Ersek
---
Notes:
V7:
- Add RB tag
V6:
- As part of restructuring
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed
Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction
: Jordan Justen
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
---
Notes:
v2:
- Modify PCD name according to changes made in Baselib implementation
V1:
- Introduce PCD for platform
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
---
Notes:
V1:
- Utilize
D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
---
Notes:
V1:
- Implement Cache management instructions in Baselib
MdePkg/Library/BaseLib/BaseLib.inf| 2 +-
MdePkg/Include
, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Sunil V L
Cc: Daniel Schaefer
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
---
Notes:
V6:
- As part of restructuring, adding cache instruction differentiation
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
---
Notes:
V5
Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction
Laszlo Ersek wrote:
> On 10/19/23 11:22, Laszlo Ersek wrote:
> > On 10/19/23 08:48, Dhaval Sharma wrote:
>
> >> (11) I agree that we should use symbolic names rather than
> >> magic constants, but raw encodings of machine instructions don't belong
> >>
Inconsistent spelling in the patch subject: "RISCV CMO". ditto;
should be RISC-V.ditto, should be PcdRiscVFeatureOverride *Done*
(32-33) Total inconsistency, RV64_ versus RV_. Should be RiscVIsCMOEnabled
(upper case V). *Done*
On Tue, Oct 17, 2023 at 8:09 PM Laszlo Ersek wrote:
>
Justen
Gerd Hoffmann
Sunil V L
Andrei Warkentin
Signed-off-by: Dhaval Sharma
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index fe320525153f..8b5e010316ba 100644
. Not able to verify actual instruction in HW as Qemu ignores
any actual cache operations.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Cc: Sunil V L
Cc: Andrei Warkentin
Signed-off-by: Dhaval Sharma
---
Notes:
v5:
- Addressed comments from v4
- Use #defines
Implementing code to support Cache Management Operations (CMO) defined by RV
spec https://github.com/riscv/riscv-CMOs
Notes:
CMO only supports block based Operations. Meaning complete cache
flush/invd/clean Operations are not available. In that case we fallback on
fence.i instructions.
Rely on
Reviewed-by: Dhaval Sharma
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Hi everyone,
A gentle remonder to review the patch..
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Group Owner:
As per spec if xDSDT is avaialble, it should be used first.
Handle required flow when xDSDT is abscent or present.
Test: Tested on RISCV64 Qemu platform with xDSDT and booted to
linux kernel.
Cc: Jian J Wang
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Dandan Bi
Signed-off-by: Dhaval Sharma
Enable detection of XDSDT table from ACPI HOB
Dhaval (1):
MdeModulePkg: Fix issue with ACPI table creation
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c | 15
++-
1 file changed, 14 insertions(+), 1 deletion(-)
Cc: Jian J Wang
Cc: Liming Gao
Cc: Zhiguang Liu
with SENVCFG. Will fix it in the next
revision after #2 is addressed.
On Mon, Jul 24, 2023 at 10:03 AM Sunil V L wrote:
> Hi Dhaval,
>
> On Thu, Jul 13, 2023 at 03:03:31PM +0530, Dhaval wrote:
> > From: Dhaval Sharma
> >
> > Implementing code to support Cache Man
From: Dhaval Sharma
Implementing code to support Cache Management Operations
(CMO) defined by RV spec https://github.com/riscv/riscv-CMOs
Notes:
1. CMO only supports block based Operations. Meaning complete
cache flush/invd/clean Operations are not available. In that case
we fallback
instruction in HW as Qemu ignores any actual cache
operations.
Dhaval Sharma (1):
MdePkg:Implement RISCV CMO
MdePkg/Library/BaseLib/BaseLib.inf | 2 +-
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 4 +
MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 200
Added required Dxe and Arch Proto drivers to ensure we
are able to boot to Shell.
Test: Able to boot to UEFI Shell
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Cc: Sunil V
Signed-off-by: Dhaval Sharma
---
UefiPayloadPkg/UefiPayloadPkgRV64.dsc | 33
RV CPU driver requires access to HartID and FDT passed by BL.
Set it through FirmwareContext. In future this should be passed
as part of FDT itself to avoid any custome structures.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Cc: Sunil V
Signed-off-by: Dhaval Sharma
: James Lu
Cc: Gua Guo
Cc: Sunil V
Signed-off-by: Dhaval Sharma
---
UefiPayloadPkg/UefiPayloadEntry/RiscV64/DxeLoadFunc.c | 46 ++
UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c | 149
+++-
2 files changed, 194 insertions(+), 1 deletion(-)
diff --git
: Tested that code compiles UPL Pkg with RV64 GCC5
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Cc: Sunil V
Signed-off-by: Dhaval Sharma
---
UefiPayloadPkg/UefiPayloadPkgRV64.dsc | 637
UefiPayloadPkg/UefiPayloadPkgRV64.fdf
Signed-off-by: Dhaval Sharma
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +-
UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf | 6 +
UefiPayloadPkg/UefiPayloadEntry/Ia32/Ia32FdtParserLib.c| 33 ++
UefiPayloadPkg/UefiPayloadEntry/RiscV64/Rv64FdtParserLib.c
Cc: Gua Guo
Cc: Sunil V
Signed-off-by: Dhaval Sharma
---
UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.c
b/UefiPayloadPkg/UefiPayloadEntry
8259 is very arch specific programming. It needs to be moved out to
the respective arch flow. Added in both x64 and x32 paths
Test: Able to boot UEFI shell with Coreboot Tianocore payload on
x86 qemu
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval
and x64 eventually this should be
removed once BL impelement this logic.
Test: Verified booting UEFI shell on coreboot on qemu.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval Sharma
Reviewed-by: Gua Guo
Reviewed-by: James Lu
---
Notes:
v3
fashion for RV to get to early debug logs from FDT described serial device.
It will require modifications to work on other Archs.
Branch https://github.com/rivosinc/edk2/tree/upl-rv64-enable-compilation-v1
Dhaval Sharma (8):
UefiPayloadPkg: Remove FP Init from UPL entry
UefiPayloadPkg: Move
and x64 eventually this should be
removed once BL impelement this logic.
Test: Verified booting UEFI shell on coreboot on qemu.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: Dhaval Sharma
Reviewed-by: Gua Guo
Reviewed-by: James Lu
---
Notes:
v3
fashion for RV to get to early debug logs from FDT described serial device.
It will require modifications to work on other Archs.
Branch https://github.com/rivosinc/edk2/tree/upl-rv64-enable-compilation-v1
Dhaval Sharma (8):
UefiPayloadPkg: Remove FP Init from UPL entry
UefiPayloadPkg: Move
Ping..Do we have approval yet for GCC12?
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