-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port
SmmControl protocol to PPI for S3
@Chaganty, Rangasai V<mailto:rangasai.v.chaga...@intel.com> Is it fair to say
that the build time address for ACPI BAR is the cross silicon design? I think
it is and therefore we should move t
asai V
Subject: Re: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port
SmmControl protocol to PPI for S3
Right, but Kabylake has a different implementation that retrieves it from HW
registers - PchAcpiBaseGet(). This is probably optional, there is a PCD, but
it's in a different package
roups.io On Behalf Of Benjamin
> Doron
> Sent: Monday, August 29, 2022 1:36 PM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L ; Sinha, Ankit <
> ankit.si...@intel.com>; Ni, Ray ; Chaganty, Rangasai V <
> rangasai.v.chaga...@intel.com>; Oram, Isaac W
>
][PATCH v1 2/5] Silicon/Intel: Port
SmmControl protocol to PPI for S3
S3 resume may require communication with SMM, for which we need the SmmControl
PPI. Therefore, port the DXE drivers to a library, like there is for SMM Access.
As the registers are common across Intel platforms in the tree, while
S3 resume may require communication with SMM, for which we need the
SmmControl PPI. Therefore, port the DXE drivers to a library, like there
is for SMM Access.
As the registers are common across Intel platforms in the tree, while
a helper function definition is not, implement a new library as a
