On Fri, 19 Apr 2024 19:50:13 +0200
Ard Biesheuvel wrote:
> From: Ard Biesheuvel
>
> The optimization that enabled entry with MMU and caches enabled at EL1
> removed the strict alignment requirement for XIP code (roughly, any code
> that might execute with the MMU and caches off, which means
From: Ard Biesheuvel
The optimization that enabled entry with MMU and caches enabled at EL1
removed the strict alignment requirement for XIP code (roughly, any code
that might execute with the MMU and caches off, which means SEC and PEI
phase modules but also *all* BASE libraries), on the basis
