Thanks Gerd, I will refine the code logic.
> -Original Message-
> From: Gerd Hoffmann
> Sent: Friday, January 13, 2023 5:51 PM
> To: Wu, Jiaxin
> Cc: devel@edk2.groups.io; Dong, Eric ; Ni, Ray
> ; Zeng, Star ; Laszlo Ersek
> ; Kumar, Rahul R
> Subject: Re: [PATCH v1 2/4] UefiCpuPkg/PiS
Hi,
> + } else {
> +mSmmInitialized = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) *
> mMaxNumberOfCpus);
> +ASSERT (mSmmInitialized != NULL);
ASSERT is not sufficient error handling.
take care,
Gerd
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SMM CPU driver will retrieve the SMBASE addresses from SMM Base Hob
and installs the SMI handler at [SMBASE+8000h] for each processor
instead of relocating SMM Base addresses from SMRAM again.
With SMM Base Hob, SMM CPU driver does not need the RSM instruction
to reload the SMBASE register with th
