Patch pushed: 69e6a5e160551fdd09ce367e9c97c25d8683a3ac
Thanks,
Chasel
> -Original Message-
> From: Benjamin Doron
> Sent: Friday, July 23, 2021 10:27 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Liming Gao ;
> Dong, Eric
> Subject: [PATCH v2]
ect: [edk2-devel] [PATCH v2] MinPlatformPkg/PciHostBridgeLibSimple:
> Fix Mem.Limit assignment
>
> In the case where the root bridge's Mem.Limit is the base address of PCIe
> MMIO, subtract one to make a valid end address.
>
> This fixes an issue where CpuDxe returns "Length(0x
Thanks for fixing this issue! Reviewed-by: Chasel Chiu
> -Original Message-
> From: Benjamin Doron
> Sent: Friday, July 23, 2021 10:27 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Liming Gao
> ; Dong, Eric
> Subject: [PATCH v2]
In the case where the root bridge's Mem.Limit is the base address of
PCIe MMIO, subtract one to make a valid end address.
This fixes an issue where CpuDxe returns "Length(0x5001) is not
aligned!" when PciHostBridgeDxe attempts to make this range uncacheable.
Cc: Chasel Chiu
Cc: Nate
