A32_PG_P) == 0 || (Pml5[Pml5Index] &
>> IA32_PG_PMNT) != 0) {
>>//
>>// If the PML5 entry is not present or is masked, skip it
>>
>> Best regards,
>>
>> Mike
>>
>>> -----Original Message-
>>> From: devel@edk2
Ray ; Kinney, Michael D
>
> Cc: Dong, Eric ; Laszlo Ersek
> Subject: RE: [edk2-devel] [PATCH v2 3/3] UefiCpuPkg/PiSmmCpu: Enable 5 level
> paging when CPU supports
>
> Hi Ray,
>
> I noticed a Linux/GCC build issue with this patch when using GCC version:
>
> g
t; To: devel@edk2.groups.io
> Cc: Dong, Eric ; Laszlo Ersek
>
> Subject: [edk2-devel] [PATCH v2 3/3] UefiCpuPkg/PiSmmCpu:
> Enable 5 level paging when CPU supports
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946
>
> The patch changes SMM environment to use 5 level
Reviewed-by: Eric Dong
> -Original Message-
> From: Ni, Ray
> Sent: Wednesday, July 3, 2019 2:54 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Laszlo Ersek
> Subject: [PATCH v2 3/3] UefiCpuPkg/PiSmmCpu: Enable 5 level paging when
> CPU supports
>
>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946
The patch changes SMM environment to use 5 level paging when CPU
supports it.
Signed-off-by: Ray Ni
Cc: Eric Dong
Regression-tested-by: Laszlo Ersek
---
.../PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 20 +-
