czw., 16 maj 2019 o 16:02 Ard Biesheuvel napisał(a):
>
> On Thu, 9 May 2019 at 11:54, Marcin Wojtas wrote:
> >
> > From: Ard Biesheuvel
> >
> > Implement a special version of PciExpressLib that takes the quirky
> > nature of the Synopsys Designware PCIe IP into account. In particular,
> > we
On Thu, 9 May 2019 at 11:54, Marcin Wojtas wrote:
>
> From: Ard Biesheuvel
>
> Implement a special version of PciExpressLib that takes the quirky
> nature of the Synopsys Designware PCIe IP into account. In particular,
> we need to ignores config space accesses to all devices on the first
Hi Leif,
pt., 10 maj 2019 o 17:25 Leif Lindholm napisał(a):
>
> On Thu, May 09, 2019 at 11:53:34AM +0200, Marcin Wojtas wrote:
> > From: Ard Biesheuvel
> >
> > Implement a special version of PciExpressLib that takes the quirky
> > nature of the Synopsys Designware PCIe IP into account. In
On Thu, May 09, 2019 at 11:53:34AM +0200, Marcin Wojtas wrote:
> From: Ard Biesheuvel
>
> Implement a special version of PciExpressLib that takes the quirky
> nature of the Synopsys Designware PCIe IP into account. In particular,
> we need to ignores config space accesses to all devices on the
From: Ard Biesheuvel
Implement a special version of PciExpressLib that takes the quirky
nature of the Synopsys Designware PCIe IP into account. In particular,
we need to ignores config space accesses to all devices on the first
bus except device 0, because the broadcast nature of type 0
