forms] [PATCH v3 2/3] Platform/ARM/SgiPkg:
Add HMAT ACPI table for RdN1EdgeX2
Hi Vijay,
+#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+ ) \
+{ \
+ TotalCacheLevels, CacheLevel, CacheAssoci
Hi Vijay,
>
> +#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy,
> CacheLineSize \
> + ) \
> +{ \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy,
> CacheLineSize \
> +}
This macros is
Add HMAT table support for RD-N1-Edge dual-chip platform. The latencies
mentioned in the table are hypothetical values and represents typical
latency between two chips. These values are applicable only for
RD-N1-Edge dual-chip fixed virtual and should not be reused for other
platforms.
