On Wed, Sep 04, 2019 at 06:43:07PM +0800, Abner Chang wrote:
> Add RISC-V processor binding and RISC-V processor specific definitions and
> macros.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Abner Chang
> ---
> MdePkg/Library/BaseLib/BaseLib.inf
Add RISC-V processor binding and RISC-V processor specific definitions and
macros.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang
---
MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 33 ++