On Mon, Mar 4, 2024 at 6:24 PM Tom Lendacky wrote:
>
> On 3/4/24 07:09, Gerd Hoffmann wrote:
> >Hi,
> >
> >>> 23:16 GuestPhysAddrSize Maximum guest physical address size in bits.
> >>> This number applies only to guests using
> >>> nested
> >>>
On 3/4/24 07:09, Gerd Hoffmann wrote:
Hi,
23:16 GuestPhysAddrSize Maximum guest physical address size in bits.
This number applies only to guests using nested
paging. When this field is zero, refer to the
Hi,
> >23:16 GuestPhysAddrSize Maximum guest physical address size in bits.
> >This number applies only to guests using nested
> >paging. When this field is zero, refer to the
> >PhysAddrSize field for the
On Thu, Feb 22, 2024 at 5:13 PM Paolo Bonzini wrote:
> Also, to clarify the hardware behavior, if hCR4.LA57=0 and host
> PhysAddrSize==52, then will guest physical addresses above 2^48
>
> 1) cause a reserved #PF in the guest, or
>
> 2) cause a non-present NPF exit in the hypervisor?
>
> I
On 2/22/24 16:44, Tom Lendacky wrote:
On 2/22/24 05:24, Gerd Hoffmann wrote:
Hi,
+ if (Cr4.Bits.LA57) {
+ if (PhysBits > 48) {
+ /*
+ * Some Intel CPUs support 5-level paging, have more than 48
+ * phys-bits but support only 4-level EPT, which effectively
+
On 2/22/24 05:24, Gerd Hoffmann wrote:
Hi,
+if (Cr4.Bits.LA57) {
+ if (PhysBits > 48) {
+/*
+ * Some Intel CPUs support 5-level paging, have more than 48
+ * phys-bits but support only 4-level EPT, which effectively
+ * limits guest phys-bits to 48.
Hi,
> +if (Cr4.Bits.LA57) {
> + if (PhysBits > 48) {
> +/*
> + * Some Intel CPUs support 5-level paging, have more than 48
> + * phys-bits but support only 4-level EPT, which effectively
> + * limits guest phys-bits to 48.
> + *
> + * AMD
